pinctrl-meson.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <log.h>
  8. #include <malloc.h>
  9. #include <dm/device-internal.h>
  10. #include <dm/device_compat.h>
  11. #include <dm/lists.h>
  12. #include <dm/pinctrl.h>
  13. #include <fdt_support.h>
  14. #include <linux/bitops.h>
  15. #include <linux/err.h>
  16. #include <linux/io.h>
  17. #include <linux/libfdt.h>
  18. #include <linux/sizes.h>
  19. #include <asm/gpio.h>
  20. #include "pinctrl-meson.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. static const char *meson_pinctrl_dummy_name = "_dummy";
  23. static char pin_name[PINNAME_SIZE];
  24. int meson_pinctrl_get_groups_count(struct udevice *dev)
  25. {
  26. struct meson_pinctrl *priv = dev_get_priv(dev);
  27. return priv->data->num_groups;
  28. }
  29. const char *meson_pinctrl_get_group_name(struct udevice *dev,
  30. unsigned int selector)
  31. {
  32. struct meson_pinctrl *priv = dev_get_priv(dev);
  33. if (!priv->data->groups[selector].name)
  34. return meson_pinctrl_dummy_name;
  35. return priv->data->groups[selector].name;
  36. }
  37. int meson_pinctrl_get_pins_count(struct udevice *dev)
  38. {
  39. struct meson_pinctrl *priv = dev_get_priv(dev);
  40. return priv->data->num_pins;
  41. }
  42. const char *meson_pinctrl_get_pin_name(struct udevice *dev,
  43. unsigned int selector)
  44. {
  45. struct meson_pinctrl *priv = dev_get_priv(dev);
  46. if (selector > priv->data->num_pins ||
  47. selector > priv->data->funcs[0].num_groups)
  48. snprintf(pin_name, PINNAME_SIZE, "Error");
  49. else
  50. snprintf(pin_name, PINNAME_SIZE, "%s",
  51. priv->data->funcs[0].groups[selector]);
  52. return pin_name;
  53. }
  54. int meson_pinmux_get_functions_count(struct udevice *dev)
  55. {
  56. struct meson_pinctrl *priv = dev_get_priv(dev);
  57. return priv->data->num_funcs;
  58. }
  59. const char *meson_pinmux_get_function_name(struct udevice *dev,
  60. unsigned int selector)
  61. {
  62. struct meson_pinctrl *priv = dev_get_priv(dev);
  63. return priv->data->funcs[selector].name;
  64. }
  65. static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset,
  66. enum meson_reg_type reg_type,
  67. unsigned int *reg, unsigned int *bit)
  68. {
  69. struct meson_pinctrl *priv = dev_get_priv(dev);
  70. struct meson_bank *bank = NULL;
  71. struct meson_reg_desc *desc;
  72. unsigned int pin;
  73. int i;
  74. pin = priv->data->pin_base + offset;
  75. for (i = 0; i < priv->data->num_banks; i++) {
  76. if (pin >= priv->data->banks[i].first &&
  77. pin <= priv->data->banks[i].last) {
  78. bank = &priv->data->banks[i];
  79. break;
  80. }
  81. }
  82. if (!bank)
  83. return -EINVAL;
  84. desc = &bank->regs[reg_type];
  85. *reg = desc->reg * 4;
  86. *bit = desc->bit + pin - bank->first;
  87. return 0;
  88. }
  89. int meson_gpio_get(struct udevice *dev, unsigned int offset)
  90. {
  91. struct meson_pinctrl *priv = dev_get_priv(dev->parent);
  92. unsigned int reg, bit;
  93. int ret;
  94. ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_IN, &reg,
  95. &bit);
  96. if (ret)
  97. return ret;
  98. return !!(readl(priv->reg_gpio + reg) & BIT(bit));
  99. }
  100. int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
  101. {
  102. struct meson_pinctrl *priv = dev_get_priv(dev->parent);
  103. unsigned int reg, bit;
  104. int ret;
  105. ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_OUT, &reg,
  106. &bit);
  107. if (ret)
  108. return ret;
  109. clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
  110. return 0;
  111. }
  112. int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
  113. {
  114. struct meson_pinctrl *priv = dev_get_priv(dev->parent);
  115. unsigned int reg, bit, val;
  116. int ret;
  117. ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_DIR, &reg,
  118. &bit);
  119. if (ret)
  120. return ret;
  121. val = readl(priv->reg_gpio + reg);
  122. return (val & BIT(bit)) ? GPIOF_INPUT : GPIOF_OUTPUT;
  123. }
  124. int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
  125. {
  126. struct meson_pinctrl *priv = dev_get_priv(dev->parent);
  127. unsigned int reg, bit;
  128. int ret;
  129. ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_DIR, &reg,
  130. &bit);
  131. if (ret)
  132. return ret;
  133. setbits_le32(priv->reg_gpio + reg, BIT(bit));
  134. return 0;
  135. }
  136. int meson_gpio_direction_output(struct udevice *dev,
  137. unsigned int offset, int value)
  138. {
  139. struct meson_pinctrl *priv = dev_get_priv(dev->parent);
  140. unsigned int reg, bit;
  141. int ret;
  142. ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_DIR, &reg,
  143. &bit);
  144. if (ret)
  145. return ret;
  146. clrbits_le32(priv->reg_gpio + reg, BIT(bit));
  147. ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_OUT, &reg,
  148. &bit);
  149. if (ret)
  150. return ret;
  151. clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
  152. return 0;
  153. }
  154. static int meson_pinconf_bias_set(struct udevice *dev, unsigned int pin,
  155. unsigned int param)
  156. {
  157. struct meson_pinctrl *priv = dev_get_priv(dev);
  158. unsigned int offset = pin - priv->data->pin_base;
  159. unsigned int reg, bit;
  160. int ret;
  161. ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_PULLEN, &reg, &bit);
  162. if (ret)
  163. return ret;
  164. if (param == PIN_CONFIG_BIAS_DISABLE) {
  165. clrsetbits_le32(priv->reg_pullen + reg, BIT(bit), 0);
  166. return 0;
  167. }
  168. /* othewise, enable the bias and select level */
  169. clrsetbits_le32(priv->reg_pullen + reg, BIT(bit), BIT(bit));
  170. ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_PULL, &reg, &bit);
  171. if (ret)
  172. return ret;
  173. clrsetbits_le32(priv->reg_pull + reg, BIT(bit),
  174. (param == PIN_CONFIG_BIAS_PULL_UP ? BIT(bit) : 0));
  175. return 0;
  176. }
  177. static int meson_pinconf_drive_strength_set(struct udevice *dev,
  178. unsigned int pin,
  179. unsigned int drive_strength_ua)
  180. {
  181. struct meson_pinctrl *priv = dev_get_priv(dev);
  182. unsigned int offset = pin - priv->data->pin_base;
  183. unsigned int reg, bit;
  184. unsigned int ds_val;
  185. int ret;
  186. if (!priv->reg_ds) {
  187. dev_err(dev, "drive-strength-microamp not supported\n");
  188. return -ENOTSUPP;
  189. }
  190. ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DS, &reg, &bit);
  191. if (ret)
  192. return ret;
  193. bit = bit << 1;
  194. if (drive_strength_ua <= 500) {
  195. ds_val = MESON_PINCONF_DRV_500UA;
  196. } else if (drive_strength_ua <= 2500) {
  197. ds_val = MESON_PINCONF_DRV_2500UA;
  198. } else if (drive_strength_ua <= 3000) {
  199. ds_val = MESON_PINCONF_DRV_3000UA;
  200. } else if (drive_strength_ua <= 4000) {
  201. ds_val = MESON_PINCONF_DRV_4000UA;
  202. } else {
  203. dev_warn(dev,
  204. "pin %u: invalid drive-strength-microamp : %d , default to 4mA\n",
  205. pin, drive_strength_ua);
  206. ds_val = MESON_PINCONF_DRV_4000UA;
  207. }
  208. clrsetbits_le32(priv->reg_ds + reg, 0x3 << bit, ds_val << bit);
  209. return 0;
  210. }
  211. int meson_pinconf_set(struct udevice *dev, unsigned int pin,
  212. unsigned int param, unsigned int arg)
  213. {
  214. int ret;
  215. switch (param) {
  216. case PIN_CONFIG_BIAS_DISABLE:
  217. case PIN_CONFIG_BIAS_PULL_UP:
  218. case PIN_CONFIG_BIAS_PULL_DOWN:
  219. ret = meson_pinconf_bias_set(dev, pin, param);
  220. break;
  221. case PIN_CONFIG_DRIVE_STRENGTH_UA:
  222. ret = meson_pinconf_drive_strength_set(dev, pin, arg);
  223. break;
  224. default:
  225. dev_err(dev, "unsupported configuration parameter %u\n", param);
  226. return -EINVAL;
  227. }
  228. return ret;
  229. }
  230. int meson_pinconf_group_set(struct udevice *dev,
  231. unsigned int group_selector,
  232. unsigned int param, unsigned int arg)
  233. {
  234. struct meson_pinctrl *priv = dev_get_priv(dev);
  235. struct meson_pmx_group *grp = &priv->data->groups[group_selector];
  236. int i, ret;
  237. for (i = 0; i < grp->num_pins; i++) {
  238. ret = meson_pinconf_set(dev, grp->pins[i], param, arg);
  239. if (ret)
  240. return ret;
  241. }
  242. return 0;
  243. }
  244. int meson_gpio_probe(struct udevice *dev)
  245. {
  246. struct meson_pinctrl *priv = dev_get_priv(dev->parent);
  247. struct gpio_dev_priv *uc_priv;
  248. uc_priv = dev_get_uclass_priv(dev);
  249. uc_priv->bank_name = priv->data->name;
  250. uc_priv->gpio_count = priv->data->num_pins;
  251. return 0;
  252. }
  253. static fdt_addr_t parse_address(int offset, const char *name, int na, int ns)
  254. {
  255. int index, len = 0;
  256. const fdt32_t *reg;
  257. index = fdt_stringlist_search(gd->fdt_blob, offset, "reg-names", name);
  258. if (index < 0)
  259. return FDT_ADDR_T_NONE;
  260. reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
  261. if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns))))
  262. return FDT_ADDR_T_NONE;
  263. reg += index * (na + ns);
  264. return fdt_translate_address((void *)gd->fdt_blob, offset, reg);
  265. }
  266. int meson_pinctrl_probe(struct udevice *dev)
  267. {
  268. struct meson_pinctrl *priv = dev_get_priv(dev);
  269. struct uclass_driver *drv;
  270. struct udevice *gpio_dev;
  271. fdt_addr_t addr;
  272. int node, gpio = -1, len;
  273. int na, ns;
  274. char *name;
  275. na = fdt_address_cells(gd->fdt_blob, dev_of_offset(dev->parent));
  276. if (na < 1) {
  277. debug("bad #address-cells\n");
  278. return -EINVAL;
  279. }
  280. ns = fdt_size_cells(gd->fdt_blob, dev_of_offset(dev->parent));
  281. if (ns < 1) {
  282. debug("bad #size-cells\n");
  283. return -EINVAL;
  284. }
  285. fdt_for_each_subnode(node, gd->fdt_blob, dev_of_offset(dev)) {
  286. if (fdt_getprop(gd->fdt_blob, node, "gpio-controller", &len)) {
  287. gpio = node;
  288. break;
  289. }
  290. }
  291. if (!gpio) {
  292. debug("gpio node not found\n");
  293. return -EINVAL;
  294. }
  295. addr = parse_address(gpio, "mux", na, ns);
  296. if (addr == FDT_ADDR_T_NONE) {
  297. debug("mux address not found\n");
  298. return -EINVAL;
  299. }
  300. priv->reg_mux = (void __iomem *)addr;
  301. addr = parse_address(gpio, "gpio", na, ns);
  302. if (addr == FDT_ADDR_T_NONE) {
  303. debug("gpio address not found\n");
  304. return -EINVAL;
  305. }
  306. priv->reg_gpio = (void __iomem *)addr;
  307. addr = parse_address(gpio, "pull", na, ns);
  308. /* Use gpio region if pull one is not present */
  309. if (addr == FDT_ADDR_T_NONE)
  310. priv->reg_pull = priv->reg_gpio;
  311. else
  312. priv->reg_pull = (void __iomem *)addr;
  313. addr = parse_address(gpio, "pull-enable", na, ns);
  314. /* Use pull region if pull-enable one is not present */
  315. if (addr == FDT_ADDR_T_NONE)
  316. priv->reg_pullen = priv->reg_pull;
  317. else
  318. priv->reg_pullen = (void __iomem *)addr;
  319. addr = parse_address(gpio, "ds", na, ns);
  320. /* Drive strength region is optional */
  321. if (addr == FDT_ADDR_T_NONE)
  322. priv->reg_ds = NULL;
  323. else
  324. priv->reg_ds = (void __iomem *)addr;
  325. priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev);
  326. /* Lookup GPIO driver */
  327. drv = lists_uclass_lookup(UCLASS_GPIO);
  328. if (!drv) {
  329. puts("Cannot find GPIO driver\n");
  330. return -ENOENT;
  331. }
  332. name = calloc(1, 32);
  333. sprintf(name, "meson-gpio");
  334. /* Create child device UCLASS_GPIO and bind it */
  335. device_bind(dev, priv->data->gpio_driver, name, NULL, gpio, &gpio_dev);
  336. dev_set_of_offset(gpio_dev, gpio);
  337. return 0;
  338. }