pinctrl-mtk-common.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 MediaTek Inc.
  4. * Author: Ryder Lee <ryder.lee@mediatek.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <dm/device-internal.h>
  9. #include <dm/lists.h>
  10. #include <dm/pinctrl.h>
  11. #include <asm/io.h>
  12. #include <asm-generic/gpio.h>
  13. #include <linux/bitops.h>
  14. #include "pinctrl-mtk-common.h"
  15. #if CONFIG_IS_ENABLED(PINCONF)
  16. /**
  17. * struct mtk_drive_desc - the structure that holds the information
  18. * of the driving current
  19. * @min: the minimum current of this group
  20. * @max: the maximum current of this group
  21. * @step: the step current of this group
  22. * @scal: the weight factor
  23. *
  24. * formula: output = ((input) / step - 1) * scal
  25. */
  26. struct mtk_drive_desc {
  27. u8 min;
  28. u8 max;
  29. u8 step;
  30. u8 scal;
  31. };
  32. /* The groups of drive strength */
  33. static const struct mtk_drive_desc mtk_drive[] = {
  34. [DRV_GRP0] = { 4, 16, 4, 1 },
  35. [DRV_GRP1] = { 4, 16, 4, 2 },
  36. [DRV_GRP2] = { 2, 8, 2, 1 },
  37. [DRV_GRP3] = { 2, 8, 2, 2 },
  38. [DRV_GRP4] = { 2, 16, 2, 1 },
  39. };
  40. #endif
  41. static const char *mtk_pinctrl_dummy_name = "_dummy";
  42. static void mtk_w32(struct udevice *dev, u32 reg, u32 val)
  43. {
  44. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  45. __raw_writel(val, priv->base + reg);
  46. }
  47. static u32 mtk_r32(struct udevice *dev, u32 reg)
  48. {
  49. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  50. return __raw_readl(priv->base + reg);
  51. }
  52. static inline int get_count_order(unsigned int count)
  53. {
  54. int order;
  55. order = fls(count) - 1;
  56. if (count & (count - 1))
  57. order++;
  58. return order;
  59. }
  60. void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set)
  61. {
  62. u32 val;
  63. val = mtk_r32(dev, reg);
  64. val &= ~mask;
  65. val |= set;
  66. mtk_w32(dev, reg, val);
  67. }
  68. static int mtk_hw_pin_field_lookup(struct udevice *dev, int pin,
  69. const struct mtk_pin_reg_calc *rc,
  70. struct mtk_pin_field *pfd)
  71. {
  72. const struct mtk_pin_field_calc *c, *e;
  73. u32 bits;
  74. c = rc->range;
  75. e = c + rc->nranges;
  76. while (c < e) {
  77. if (pin >= c->s_pin && pin <= c->e_pin)
  78. break;
  79. c++;
  80. }
  81. if (c >= e)
  82. return -EINVAL;
  83. /* Calculated bits as the overall offset the pin is located at,
  84. * if c->fixed is held, that determines the all the pins in the
  85. * range use the same field with the s_pin.
  86. */
  87. bits = c->fixed ? c->s_bit : c->s_bit + (pin - c->s_pin) * (c->x_bits);
  88. /* Fill pfd from bits. For example 32-bit register applied is assumed
  89. * when c->sz_reg is equal to 32.
  90. */
  91. pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
  92. pfd->bitpos = bits % c->sz_reg;
  93. pfd->mask = (1 << c->x_bits) - 1;
  94. /* pfd->next is used for indicating that bit wrapping-around happens
  95. * which requires the manipulation for bit 0 starting in the next
  96. * register to form the complete field read/write.
  97. */
  98. pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
  99. return 0;
  100. }
  101. static int mtk_hw_pin_field_get(struct udevice *dev, int pin,
  102. int field, struct mtk_pin_field *pfd)
  103. {
  104. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  105. const struct mtk_pin_reg_calc *rc;
  106. if (field < 0 || field >= PINCTRL_PIN_REG_MAX)
  107. return -EINVAL;
  108. if (priv->soc->reg_cal && priv->soc->reg_cal[field].range)
  109. rc = &priv->soc->reg_cal[field];
  110. else
  111. return -EINVAL;
  112. return mtk_hw_pin_field_lookup(dev, pin, rc, pfd);
  113. }
  114. static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
  115. {
  116. *l = 32 - pf->bitpos;
  117. *h = get_count_order(pf->mask) - *l;
  118. }
  119. static void mtk_hw_write_cross_field(struct udevice *dev,
  120. struct mtk_pin_field *pf, int value)
  121. {
  122. int nbits_l, nbits_h;
  123. mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
  124. mtk_rmw(dev, pf->offset, pf->mask << pf->bitpos,
  125. (value & pf->mask) << pf->bitpos);
  126. mtk_rmw(dev, pf->offset + pf->next, BIT(nbits_h) - 1,
  127. (value & pf->mask) >> nbits_l);
  128. }
  129. static void mtk_hw_read_cross_field(struct udevice *dev,
  130. struct mtk_pin_field *pf, int *value)
  131. {
  132. int nbits_l, nbits_h, h, l;
  133. mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
  134. l = (mtk_r32(dev, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);
  135. h = (mtk_r32(dev, pf->offset + pf->next)) & (BIT(nbits_h) - 1);
  136. *value = (h << nbits_l) | l;
  137. }
  138. static int mtk_hw_set_value(struct udevice *dev, int pin, int field,
  139. int value)
  140. {
  141. struct mtk_pin_field pf;
  142. int err;
  143. err = mtk_hw_pin_field_get(dev, pin, field, &pf);
  144. if (err)
  145. return err;
  146. if (!pf.next)
  147. mtk_rmw(dev, pf.offset, pf.mask << pf.bitpos,
  148. (value & pf.mask) << pf.bitpos);
  149. else
  150. mtk_hw_write_cross_field(dev, &pf, value);
  151. return 0;
  152. }
  153. static int mtk_hw_get_value(struct udevice *dev, int pin, int field,
  154. int *value)
  155. {
  156. struct mtk_pin_field pf;
  157. int err;
  158. err = mtk_hw_pin_field_get(dev, pin, field, &pf);
  159. if (err)
  160. return err;
  161. if (!pf.next)
  162. *value = (mtk_r32(dev, pf.offset) >> pf.bitpos) & pf.mask;
  163. else
  164. mtk_hw_read_cross_field(dev, &pf, value);
  165. return 0;
  166. }
  167. static int mtk_get_groups_count(struct udevice *dev)
  168. {
  169. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  170. return priv->soc->ngrps;
  171. }
  172. static const char *mtk_get_pin_name(struct udevice *dev,
  173. unsigned int selector)
  174. {
  175. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  176. if (!priv->soc->grps[selector].name)
  177. return mtk_pinctrl_dummy_name;
  178. return priv->soc->pins[selector].name;
  179. }
  180. static int mtk_get_pins_count(struct udevice *dev)
  181. {
  182. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  183. return priv->soc->npins;
  184. }
  185. static const char *mtk_get_group_name(struct udevice *dev,
  186. unsigned int selector)
  187. {
  188. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  189. if (!priv->soc->grps[selector].name)
  190. return mtk_pinctrl_dummy_name;
  191. return priv->soc->grps[selector].name;
  192. }
  193. static int mtk_get_functions_count(struct udevice *dev)
  194. {
  195. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  196. return priv->soc->nfuncs;
  197. }
  198. static const char *mtk_get_function_name(struct udevice *dev,
  199. unsigned int selector)
  200. {
  201. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  202. if (!priv->soc->funcs[selector].name)
  203. return mtk_pinctrl_dummy_name;
  204. return priv->soc->funcs[selector].name;
  205. }
  206. static int mtk_pinmux_group_set(struct udevice *dev,
  207. unsigned int group_selector,
  208. unsigned int func_selector)
  209. {
  210. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  211. const struct mtk_group_desc *grp =
  212. &priv->soc->grps[group_selector];
  213. int i;
  214. for (i = 0; i < grp->num_pins; i++) {
  215. int *pin_modes = grp->data;
  216. mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE,
  217. pin_modes[i]);
  218. }
  219. return 0;
  220. }
  221. #if CONFIG_IS_ENABLED(PINCONF)
  222. static const struct pinconf_param mtk_conf_params[] = {
  223. { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
  224. { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
  225. { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
  226. { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
  227. { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
  228. { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
  229. { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
  230. { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
  231. { "output-high", PIN_CONFIG_OUTPUT, 1, },
  232. { "output-low", PIN_CONFIG_OUTPUT, 0, },
  233. { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
  234. };
  235. int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg, u32 val)
  236. {
  237. int err, disable, pullup;
  238. disable = (arg == PIN_CONFIG_BIAS_DISABLE);
  239. pullup = (arg == PIN_CONFIG_BIAS_PULL_UP);
  240. if (disable) {
  241. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, 0);
  242. if (err)
  243. return err;
  244. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, 0);
  245. if (err)
  246. return err;
  247. } else {
  248. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, pullup);
  249. if (err)
  250. return err;
  251. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, !pullup);
  252. if (err)
  253. return err;
  254. }
  255. return 0;
  256. }
  257. int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg, u32 val)
  258. {
  259. int err, disable, pullup, r0, r1;
  260. disable = (arg == PIN_CONFIG_BIAS_DISABLE);
  261. pullup = (arg == PIN_CONFIG_BIAS_PULL_UP);
  262. r0 = !!(val & 1);
  263. r1 = !!(val & 2);
  264. if (disable) {
  265. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 0);
  266. if (err)
  267. return err;
  268. } else {
  269. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 1);
  270. if (err)
  271. return err;
  272. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL,
  273. pullup);
  274. if (err)
  275. return err;
  276. }
  277. /* Also set PUPD/R0/R1 if the pin has them */
  278. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup);
  279. if (err != -EINVAL) {
  280. mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0);
  281. mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1);
  282. }
  283. return 0;
  284. }
  285. int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg)
  286. {
  287. int err;
  288. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1);
  289. if (err)
  290. return err;
  291. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0);
  292. if (err)
  293. return err;
  294. return 0;
  295. }
  296. int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg)
  297. {
  298. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  299. const struct mtk_pin_desc *desc = &priv->soc->pins[pin];
  300. const struct mtk_drive_desc *tb;
  301. int err = -ENOTSUPP;
  302. tb = &mtk_drive[desc->drv_n];
  303. /* 4mA when (e8, e4) = (0, 0)
  304. * 8mA when (e8, e4) = (0, 1)
  305. * 12mA when (e8, e4) = (1, 0)
  306. * 16mA when (e8, e4) = (1, 1)
  307. */
  308. if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
  309. arg = (arg / tb->step - 1) * tb->scal;
  310. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E4,
  311. arg & 0x1);
  312. if (err)
  313. return err;
  314. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E8,
  315. (arg & 0x2) >> 1);
  316. if (err)
  317. return err;
  318. }
  319. return 0;
  320. }
  321. int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg)
  322. {
  323. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  324. const struct mtk_pin_desc *desc = &priv->soc->pins[pin];
  325. const struct mtk_drive_desc *tb;
  326. int err = -ENOTSUPP;
  327. tb = &mtk_drive[desc->drv_n];
  328. if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
  329. arg = (arg / tb->step - 1) * tb->scal;
  330. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DRV, arg);
  331. if (err)
  332. return err;
  333. }
  334. return 0;
  335. }
  336. static int mtk_pinconf_set(struct udevice *dev, unsigned int pin,
  337. unsigned int param, unsigned int arg)
  338. {
  339. int err = 0;
  340. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  341. int rev = priv->soc->rev;
  342. switch (param) {
  343. case PIN_CONFIG_BIAS_DISABLE:
  344. case PIN_CONFIG_BIAS_PULL_UP:
  345. case PIN_CONFIG_BIAS_PULL_DOWN:
  346. if (rev == MTK_PINCTRL_V0)
  347. err = mtk_pinconf_bias_set_v0(dev, pin, param, arg);
  348. else
  349. err = mtk_pinconf_bias_set_v1(dev, pin, param, arg);
  350. if (err)
  351. goto err;
  352. break;
  353. case PIN_CONFIG_OUTPUT_ENABLE:
  354. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT, 0);
  355. if (err)
  356. goto err;
  357. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1);
  358. if (err)
  359. goto err;
  360. break;
  361. case PIN_CONFIG_INPUT_ENABLE:
  362. if (rev == MTK_PINCTRL_V1)
  363. err = mtk_pinconf_input_enable_v1(dev, pin, param);
  364. if (err)
  365. goto err;
  366. break;
  367. case PIN_CONFIG_OUTPUT:
  368. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1);
  369. if (err)
  370. goto err;
  371. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DO, arg);
  372. if (err)
  373. goto err;
  374. break;
  375. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  376. /* arg = 1: Input mode & SMT enable ;
  377. * arg = 0: Output mode & SMT disable
  378. */
  379. arg = arg ? 2 : 1;
  380. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR,
  381. arg & 1);
  382. if (err)
  383. goto err;
  384. err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT,
  385. !!(arg & 2));
  386. if (err)
  387. goto err;
  388. break;
  389. case PIN_CONFIG_DRIVE_STRENGTH:
  390. if (rev == MTK_PINCTRL_V0)
  391. err = mtk_pinconf_drive_set_v0(dev, pin, arg);
  392. else
  393. err = mtk_pinconf_drive_set_v1(dev, pin, arg);
  394. if (err)
  395. goto err;
  396. break;
  397. default:
  398. err = -ENOTSUPP;
  399. }
  400. err:
  401. return err;
  402. }
  403. static int mtk_pinconf_group_set(struct udevice *dev,
  404. unsigned int group_selector,
  405. unsigned int param, unsigned int arg)
  406. {
  407. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  408. const struct mtk_group_desc *grp =
  409. &priv->soc->grps[group_selector];
  410. int i, ret;
  411. for (i = 0; i < grp->num_pins; i++) {
  412. ret = mtk_pinconf_set(dev, grp->pins[i], param, arg);
  413. if (ret)
  414. return ret;
  415. }
  416. return 0;
  417. }
  418. #endif
  419. const struct pinctrl_ops mtk_pinctrl_ops = {
  420. .get_pins_count = mtk_get_pins_count,
  421. .get_pin_name = mtk_get_pin_name,
  422. .get_groups_count = mtk_get_groups_count,
  423. .get_group_name = mtk_get_group_name,
  424. .get_functions_count = mtk_get_functions_count,
  425. .get_function_name = mtk_get_function_name,
  426. .pinmux_group_set = mtk_pinmux_group_set,
  427. #if CONFIG_IS_ENABLED(PINCONF)
  428. .pinconf_num_params = ARRAY_SIZE(mtk_conf_params),
  429. .pinconf_params = mtk_conf_params,
  430. .pinconf_set = mtk_pinconf_set,
  431. .pinconf_group_set = mtk_pinconf_group_set,
  432. #endif
  433. .set_state = pinctrl_generic_set_state,
  434. };
  435. static int mtk_gpio_get(struct udevice *dev, unsigned int off)
  436. {
  437. int val, err;
  438. err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DI, &val);
  439. if (err)
  440. return err;
  441. return !!val;
  442. }
  443. static int mtk_gpio_set(struct udevice *dev, unsigned int off, int val)
  444. {
  445. return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DO, !!val);
  446. }
  447. static int mtk_gpio_get_direction(struct udevice *dev, unsigned int off)
  448. {
  449. int val, err;
  450. err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DIR, &val);
  451. if (err)
  452. return err;
  453. return val ? GPIOF_OUTPUT : GPIOF_INPUT;
  454. }
  455. static int mtk_gpio_direction_input(struct udevice *dev, unsigned int off)
  456. {
  457. return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 0);
  458. }
  459. static int mtk_gpio_direction_output(struct udevice *dev,
  460. unsigned int off, int val)
  461. {
  462. mtk_gpio_set(dev, off, val);
  463. /* And set the requested value */
  464. return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 1);
  465. }
  466. static int mtk_gpio_request(struct udevice *dev, unsigned int off,
  467. const char *label)
  468. {
  469. struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent);
  470. return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE,
  471. priv->soc->gpio_mode);
  472. }
  473. static int mtk_gpio_probe(struct udevice *dev)
  474. {
  475. struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent);
  476. struct gpio_dev_priv *uc_priv;
  477. uc_priv = dev_get_uclass_priv(dev);
  478. uc_priv->bank_name = priv->soc->name;
  479. uc_priv->gpio_count = priv->soc->npins;
  480. return 0;
  481. }
  482. static const struct dm_gpio_ops mtk_gpio_ops = {
  483. .request = mtk_gpio_request,
  484. .set_value = mtk_gpio_set,
  485. .get_value = mtk_gpio_get,
  486. .get_function = mtk_gpio_get_direction,
  487. .direction_input = mtk_gpio_direction_input,
  488. .direction_output = mtk_gpio_direction_output,
  489. };
  490. static struct driver mtk_gpio_driver = {
  491. .name = "mediatek_gpio",
  492. .id = UCLASS_GPIO,
  493. .probe = mtk_gpio_probe,
  494. .ops = &mtk_gpio_ops,
  495. };
  496. static int mtk_gpiochip_register(struct udevice *parent)
  497. {
  498. struct uclass_driver *drv;
  499. struct udevice *dev;
  500. int ret;
  501. ofnode node;
  502. drv = lists_uclass_lookup(UCLASS_GPIO);
  503. if (!drv)
  504. return -ENOENT;
  505. dev_for_each_subnode(node, parent)
  506. if (ofnode_read_bool(node, "gpio-controller")) {
  507. ret = 0;
  508. break;
  509. }
  510. if (ret)
  511. return ret;
  512. ret = device_bind_with_driver_data(parent, &mtk_gpio_driver,
  513. "mediatek_gpio", 0, node,
  514. &dev);
  515. if (ret)
  516. return ret;
  517. return 0;
  518. }
  519. int mtk_pinctrl_common_probe(struct udevice *dev,
  520. struct mtk_pinctrl_soc *soc)
  521. {
  522. struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
  523. int ret;
  524. priv->base = dev_read_addr_ptr(dev);
  525. if (!priv->base)
  526. return -EINVAL;
  527. priv->soc = soc;
  528. ret = mtk_gpiochip_register(dev);
  529. if (ret)
  530. return ret;
  531. return 0;
  532. }