pinctrl-mt8516.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 BayLibre, SAS
  4. * Author: Fabien Parent <fparent@baylibre.com>
  5. */
  6. #include <dm.h>
  7. #include "pinctrl-mtk-common.h"
  8. #define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
  9. PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
  10. _x_bits, 16, false)
  11. static const struct mtk_pin_field_calc mt8516_pin_mode_range[] = {
  12. PIN_FIELD_CALC(0, 124, 0x300, 0x10, 0, 3, 15, false),
  13. };
  14. static const struct mtk_pin_field_calc mt8516_pin_dir_range[] = {
  15. PIN_FIELD(0, 124, 0x0, 0x10, 0, 1),
  16. };
  17. static const struct mtk_pin_field_calc mt8516_pin_di_range[] = {
  18. PIN_FIELD(0, 124, 0x200, 0x10, 0, 1),
  19. };
  20. static const struct mtk_pin_field_calc mt8516_pin_do_range[] = {
  21. PIN_FIELD(0, 124, 0x100, 0x10, 0, 1),
  22. };
  23. static const struct mtk_pin_field_calc mt8516_pin_ies_range[] = {
  24. PIN_FIELD(0, 6, 0x900, 0x10, 2, 1),
  25. PIN_FIELD(7, 10, 0x900, 0x10, 3, 1),
  26. PIN_FIELD(11, 13, 0x900, 0x10, 12, 1),
  27. PIN_FIELD(14, 17, 0x900, 0x10, 13, 1),
  28. PIN_FIELD(18, 20, 0x910, 0x10, 10, 1),
  29. PIN_FIELD(21, 23, 0x900, 0x10, 13, 1),
  30. PIN_FIELD(24, 25, 0x900, 0x10, 12, 1),
  31. PIN_FIELD(26, 30, 0x900, 0x10, 0, 1),
  32. PIN_FIELD(31, 33, 0x900, 0x10, 1, 1),
  33. PIN_FIELD(34, 39, 0x900, 0x10, 2, 1),
  34. PIN_FIELD(40, 40, 0x910, 0x10, 11, 1),
  35. PIN_FIELD(41, 43, 0x900, 0x10, 10, 1),
  36. PIN_FIELD(44, 47, 0x900, 0x10, 11, 1),
  37. PIN_FIELD(48, 51, 0x900, 0x10, 14, 1),
  38. PIN_FIELD(52, 53, 0x910, 0x10, 0, 1),
  39. PIN_FIELD(54, 54, 0x910, 0x10, 2, 1),
  40. PIN_FIELD(55, 57, 0x910, 0x10, 4, 1),
  41. PIN_FIELD(58, 59, 0x900, 0x10, 15, 1),
  42. PIN_FIELD(60, 61, 0x910, 0x10, 1, 1),
  43. PIN_FIELD(62, 65, 0x910, 0x10, 5, 1),
  44. PIN_FIELD(66, 67, 0x910, 0x10, 6, 1),
  45. PIN_FIELD(68, 68, 0x930, 0x10, 2, 1),
  46. PIN_FIELD(69, 69, 0x930, 0x10, 1, 1),
  47. PIN_FIELD(70, 70, 0x930, 0x10, 6, 1),
  48. PIN_FIELD(71, 71, 0x930, 0x10, 5, 1),
  49. PIN_FIELD(72, 72, 0x930, 0x10, 4, 1),
  50. PIN_FIELD(73, 73, 0x930, 0x10, 3, 1),
  51. PIN_FIELD(100, 103, 0x910, 0x10, 7, 1),
  52. PIN_FIELD(104, 104, 0x920, 0x10, 12, 1),
  53. PIN_FIELD(105, 105, 0x920, 0x10, 11, 1),
  54. PIN_FIELD(106, 106, 0x930, 0x10, 0, 1),
  55. PIN_FIELD(107, 107, 0x920, 0x10, 15, 1),
  56. PIN_FIELD(108, 108, 0x920, 0x10, 14, 1),
  57. PIN_FIELD(109, 109, 0x920, 0x10, 13, 1),
  58. PIN_FIELD(110, 110, 0x920, 0x10, 9, 1),
  59. PIN_FIELD(111, 111, 0x920, 0x10, 8, 1),
  60. PIN_FIELD(112, 112, 0x920, 0x10, 7, 1),
  61. PIN_FIELD(113, 113, 0x920, 0x10, 6, 1),
  62. PIN_FIELD(114, 114, 0x920, 0x10, 10, 1),
  63. PIN_FIELD(115, 115, 0x920, 0x10, 1, 1),
  64. PIN_FIELD(116, 116, 0x920, 0x10, 0, 1),
  65. PIN_FIELD(117, 117, 0x920, 0x10, 5, 1),
  66. PIN_FIELD(118, 118, 0x920, 0x10, 4, 1),
  67. PIN_FIELD(119, 119, 0x920, 0x10, 3, 1),
  68. PIN_FIELD(120, 120, 0x920, 0x10, 2, 1),
  69. PIN_FIELD(121, 124, 0x910, 0x10, 9, 1),
  70. };
  71. static const struct mtk_pin_field_calc mt8516_pin_smt_range[] = {
  72. PIN_FIELD(0, 6, 0xA00, 0x10, 2, 1),
  73. PIN_FIELD(7, 10, 0xA00, 0x10, 3, 1),
  74. PIN_FIELD(11, 13, 0xA00, 0x10, 12, 1),
  75. PIN_FIELD(14, 17, 0xA00, 0x10, 13, 1),
  76. PIN_FIELD(18, 20, 0xA10, 0x10, 10, 1),
  77. PIN_FIELD(21, 23, 0xA00, 0x10, 13, 1),
  78. PIN_FIELD(24, 25, 0xA00, 0x10, 12, 1),
  79. PIN_FIELD(26, 30, 0xA00, 0x10, 0, 1),
  80. PIN_FIELD(31, 33, 0xA00, 0x10, 1, 1),
  81. PIN_FIELD(40, 40, 0xA10, 0x10, 11, 1),
  82. PIN_FIELD(41, 43, 0xA00, 0x10, 10, 1),
  83. PIN_FIELD(44, 47, 0xA00, 0x10, 11, 1),
  84. PIN_FIELD(48, 51, 0xA00, 0x10, 14, 1),
  85. PIN_FIELD(52, 53, 0xA10, 0x10, 0, 1),
  86. PIN_FIELD(54, 54, 0xA10, 0x10, 2, 1),
  87. PIN_FIELD(55, 57, 0xA10, 0x10, 4, 1),
  88. PIN_FIELD(58, 59, 0xA00, 0x10, 15, 1),
  89. PIN_FIELD(60, 61, 0xA10, 0x10, 1, 1),
  90. PIN_FIELD(62, 65, 0xA10, 0x10, 5, 1),
  91. PIN_FIELD(66, 67, 0xA10, 0x10, 6, 1),
  92. PIN_FIELD(68, 68, 0xA30, 0x10, 2, 1),
  93. PIN_FIELD(69, 69, 0xA30, 0x10, 1, 1),
  94. PIN_FIELD(70, 70, 0xA30, 0x10, 3, 1),
  95. PIN_FIELD(71, 71, 0xA30, 0x10, 4, 1),
  96. PIN_FIELD(72, 72, 0xA30, 0x10, 5, 1),
  97. PIN_FIELD(73, 73, 0xA30, 0x10, 6, 1),
  98. PIN_FIELD(100, 103, 0xA10, 0x10, 7, 1),
  99. PIN_FIELD(104, 104, 0xA20, 0x10, 12, 1),
  100. PIN_FIELD(105, 105, 0xA20, 0x10, 11, 1),
  101. PIN_FIELD(106, 106, 0xA30, 0x10, 13, 1),
  102. PIN_FIELD(107, 107, 0xA20, 0x10, 14, 1),
  103. PIN_FIELD(108, 108, 0xA20, 0x10, 15, 1),
  104. PIN_FIELD(109, 109, 0xA30, 0x10, 0, 1),
  105. PIN_FIELD(110, 110, 0xA20, 0x10, 9, 1),
  106. PIN_FIELD(111, 111, 0xA20, 0x10, 8, 1),
  107. PIN_FIELD(112, 112, 0xA20, 0x10, 7, 1),
  108. PIN_FIELD(113, 113, 0xA20, 0x10, 6, 1),
  109. PIN_FIELD(114, 114, 0xA20, 0x10, 10, 1),
  110. PIN_FIELD(115, 115, 0xA20, 0x10, 1, 1),
  111. PIN_FIELD(116, 116, 0xA20, 0x10, 0, 1),
  112. PIN_FIELD(117, 117, 0xA20, 0x10, 5, 1),
  113. PIN_FIELD(118, 118, 0xA20, 0x10, 4, 1),
  114. PIN_FIELD(119, 119, 0xA20, 0x10, 3, 1),
  115. PIN_FIELD(120, 120, 0xA20, 0x10, 2, 1),
  116. PIN_FIELD(121, 124, 0xA10, 0x10, 9, 1),
  117. };
  118. static const struct mtk_pin_field_calc mt8516_pin_pullen_range[] = {
  119. PIN_FIELD(0, 13, 0x500, 0x10, 0, 1),
  120. PIN_FIELD(18, 20, 0x510, 0x10, 2, 1),
  121. PIN_FIELD(24, 31, 0x510, 0x10, 8, 1),
  122. PIN_FIELD(32, 39, 0x520, 0x10, 0, 1),
  123. PIN_FIELD(44, 47, 0x520, 0x10, 12, 1),
  124. PIN_FIELD(48, 63, 0x530, 0x10, 0, 1),
  125. PIN_FIELD(64, 67, 0x540, 0x10, 0, 1),
  126. PIN_FIELD(100, 103, 0x560, 0x10, 4, 1),
  127. PIN_FIELD(121, 124, 0x570, 0x10, 9, 1),
  128. };
  129. static const struct mtk_pin_field_calc mt8516_pin_pullsel_range[] = {
  130. PIN_FIELD(0, 13, 0x600, 0x10, 0, 1),
  131. PIN_FIELD(18, 20, 0x610, 0x10, 2, 1),
  132. PIN_FIELD(24, 31, 0x610, 0x10, 8, 1),
  133. PIN_FIELD(32, 39, 0x620, 0x10, 0, 1),
  134. PIN_FIELD(44, 47, 0x620, 0x10, 12, 1),
  135. PIN_FIELD(48, 63, 0x630, 0x10, 0, 1),
  136. PIN_FIELD(64, 67, 0x640, 0x10, 0, 1),
  137. PIN_FIELD(100, 103, 0x660, 0x10, 4, 1),
  138. PIN_FIELD(121, 124, 0x670, 0x10, 9, 1),
  139. };
  140. static const struct mtk_pin_field_calc mt8516_pin_drv_range[] = {
  141. PIN_FIELD(0, 4, 0xd00, 0x10, 0, 4),
  142. PIN_FIELD(5, 10, 0xd00, 0x10, 4, 4),
  143. PIN_FIELD(11, 13, 0xd00, 0x10, 8, 4),
  144. PIN_FIELD(14, 17, 0xd00, 0x10, 12, 4),
  145. PIN_FIELD(18, 20, 0xd10, 0x10, 0, 4),
  146. PIN_FIELD(21, 23, 0xd00, 0x10, 12, 4),
  147. PIN_FIELD(24, 25, 0xd00, 0x10, 8, 4),
  148. PIN_FIELD(26, 30, 0xd10, 0x10, 4, 4),
  149. PIN_FIELD(31, 33, 0xd10, 0x10, 8, 4),
  150. PIN_FIELD(34, 35, 0xd10, 0x10, 12, 4),
  151. PIN_FIELD(36, 39, 0xd20, 0x10, 0, 4),
  152. PIN_FIELD(40, 40, 0xd20, 0x10, 4, 4),
  153. PIN_FIELD(41, 43, 0xd20, 0x10, 8, 4),
  154. PIN_FIELD(44, 47, 0xd20, 0x10, 12, 4),
  155. PIN_FIELD(48, 51, 0xd30, 0x10, 0, 4),
  156. PIN_FIELD(54, 54, 0xd30, 0x10, 8, 4),
  157. PIN_FIELD(55, 57, 0xd30, 0x10, 12, 4),
  158. PIN_FIELD(62, 67, 0xd40, 0x10, 8, 4),
  159. PIN_FIELD(68, 68, 0xd40, 0x10, 12, 4),
  160. PIN_FIELD(69, 69, 0xd50, 0x10, 0, 4),
  161. PIN_FIELD(70, 73, 0xd50, 0x10, 4, 4),
  162. PIN_FIELD(100, 103, 0xd50, 0x10, 8, 4),
  163. PIN_FIELD(104, 104, 0xd50, 0x10, 12, 4),
  164. PIN_FIELD(105, 105, 0xd60, 0x10, 0, 4),
  165. PIN_FIELD(106, 109, 0xd60, 0x10, 4, 4),
  166. PIN_FIELD(110, 113, 0xd70, 0x10, 0, 4),
  167. PIN_FIELD(114, 114, 0xd70, 0x10, 4, 4),
  168. PIN_FIELD(115, 115, 0xd60, 0x10, 12, 4),
  169. PIN_FIELD(116, 116, 0xd60, 0x10, 8, 4),
  170. PIN_FIELD(117, 120, 0xd70, 0x10, 0, 4),
  171. };
  172. static const struct mtk_pin_reg_calc mt8516_reg_cals[] = {
  173. [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8516_pin_mode_range),
  174. [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8516_pin_dir_range),
  175. [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8516_pin_di_range),
  176. [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8516_pin_do_range),
  177. [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8516_pin_ies_range),
  178. [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8516_pin_smt_range),
  179. [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8516_pin_pullsel_range),
  180. [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8516_pin_pullen_range),
  181. [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8516_pin_drv_range),
  182. };
  183. static const struct mtk_pin_desc mt8516_pins[] = {
  184. MTK_PIN(0, "EINT0", DRV_GRP0),
  185. MTK_PIN(1, "EINT1", DRV_GRP0),
  186. MTK_PIN(2, "EINT2", DRV_GRP0),
  187. MTK_PIN(3, "EINT3", DRV_GRP0),
  188. MTK_PIN(4, "EINT4", DRV_GRP0),
  189. MTK_PIN(5, "EINT5", DRV_GRP0),
  190. MTK_PIN(6, "EINT6", DRV_GRP0),
  191. MTK_PIN(7, "EINT7", DRV_GRP0),
  192. MTK_PIN(8, "EINT8", DRV_GRP0),
  193. MTK_PIN(9, "EINT9", DRV_GRP0),
  194. MTK_PIN(10, "EINT10", DRV_GRP0),
  195. MTK_PIN(11, "EINT11", DRV_GRP0),
  196. MTK_PIN(12, "EINT12", DRV_GRP0),
  197. MTK_PIN(13, "EINT13", DRV_GRP0),
  198. MTK_PIN(14, "EINT14", DRV_GRP2),
  199. MTK_PIN(15, "EINT15", DRV_GRP2),
  200. MTK_PIN(16, "EINT16", DRV_GRP2),
  201. MTK_PIN(17, "EINT17", DRV_GRP2),
  202. MTK_PIN(18, "EINT18", DRV_GRP0),
  203. MTK_PIN(19, "EINT19", DRV_GRP0),
  204. MTK_PIN(20, "EINT20", DRV_GRP0),
  205. MTK_PIN(21, "EINT21", DRV_GRP2),
  206. MTK_PIN(22, "EINT22", DRV_GRP2),
  207. MTK_PIN(23, "EINT23", DRV_GRP2),
  208. MTK_PIN(24, "EINT24", DRV_GRP0),
  209. MTK_PIN(25, "EINT25", DRV_GRP0),
  210. MTK_PIN(26, "PWRAP_SPI0_MI", DRV_GRP4),
  211. MTK_PIN(27, "PWRAP_SPI0_MO", DRV_GRP4),
  212. MTK_PIN(28, "PWRAP_INT", DRV_GRP4),
  213. MTK_PIN(29, "PWRAP_SPIO0_CK", DRV_GRP4),
  214. MTK_PIN(30, "PWARP_SPI0_CSN", DRV_GRP4),
  215. MTK_PIN(31, "RTC32K_CK", DRV_GRP4),
  216. MTK_PIN(32, "WATCHDOG", DRV_GRP4),
  217. MTK_PIN(33, "SRCLKENA0", DRV_GRP4),
  218. MTK_PIN(34, "URXD2", DRV_GRP0),
  219. MTK_PIN(35, "UTXD2", DRV_GRP0),
  220. MTK_PIN(36, "MRG_CLK", DRV_GRP0),
  221. MTK_PIN(37, "MRG_SYNC", DRV_GRP0),
  222. MTK_PIN(38, "MRG_DI", DRV_GRP0),
  223. MTK_PIN(39, "MRG_DO", DRV_GRP0),
  224. MTK_PIN(40, "KPROW0", DRV_GRP2),
  225. MTK_PIN(41, "KPROW1", DRV_GRP2),
  226. MTK_PIN(42, "KPCOL0", DRV_GRP2),
  227. MTK_PIN(43, "KPCOL1", DRV_GRP2),
  228. MTK_PIN(44, "JMTS", DRV_GRP2),
  229. MTK_PIN(45, "JTCK", DRV_GRP2),
  230. MTK_PIN(46, "JTDI", DRV_GRP2),
  231. MTK_PIN(47, "JTDO", DRV_GRP2),
  232. MTK_PIN(48, "SPI_CS", DRV_GRP2),
  233. MTK_PIN(49, "SPI_CK", DRV_GRP2),
  234. MTK_PIN(50, "SPI_MI", DRV_GRP2),
  235. MTK_PIN(51, "SPI_MO", DRV_GRP2),
  236. MTK_PIN(52, "SDA1", DRV_GRP2),
  237. MTK_PIN(53, "SCL1", DRV_GRP2),
  238. MTK_PIN(54, "DISP_PWM", DRV_GRP2),
  239. MTK_PIN(55, "I2S_DATA_IN", DRV_GRP2),
  240. MTK_PIN(56, "I2S_LRCK", DRV_GRP2),
  241. MTK_PIN(57, "I2S_BCK", DRV_GRP2),
  242. MTK_PIN(58, "SDA0", DRV_GRP2),
  243. MTK_PIN(59, "SCL0", DRV_GRP2),
  244. MTK_PIN(60, "SDA2", DRV_GRP2),
  245. MTK_PIN(61, "SCL2", DRV_GRP2),
  246. MTK_PIN(62, "URXD0", DRV_GRP2),
  247. MTK_PIN(63, "UTXD0", DRV_GRP2),
  248. MTK_PIN(64, "URXD1", DRV_GRP2),
  249. MTK_PIN(65, "UTXD1", DRV_GRP2),
  250. MTK_PIN(66, "LCM_RST", DRV_GRP2),
  251. MTK_PIN(67, "DSI_TE", DRV_GRP2),
  252. MTK_PIN(68, "MSDC2_CMD", DRV_GRP4),
  253. MTK_PIN(69, "MSDC2_CLK", DRV_GRP4),
  254. MTK_PIN(70, "MSDC2_DAT0", DRV_GRP4),
  255. MTK_PIN(71, "MSDC2_DAT1", DRV_GRP4),
  256. MTK_PIN(72, "MSDC2_DAT2", DRV_GRP4),
  257. MTK_PIN(73, "MSDC2_DAT3", DRV_GRP4),
  258. MTK_PIN(74, "TDN3", DRV_GRP0),
  259. MTK_PIN(75, "TDP3", DRV_GRP0),
  260. MTK_PIN(76, "TDN2", DRV_GRP0),
  261. MTK_PIN(77, "TDP2", DRV_GRP0),
  262. MTK_PIN(78, "TCN", DRV_GRP0),
  263. MTK_PIN(79, "TCP", DRV_GRP0),
  264. MTK_PIN(80, "TDN1", DRV_GRP0),
  265. MTK_PIN(81, "TDP1", DRV_GRP0),
  266. MTK_PIN(82, "TDN0", DRV_GRP0),
  267. MTK_PIN(83, "TDP0", DRV_GRP0),
  268. MTK_PIN(84, "RDN0", DRV_GRP0),
  269. MTK_PIN(85, "RDP0", DRV_GRP0),
  270. MTK_PIN(86, "RDN1", DRV_GRP0),
  271. MTK_PIN(87, "RDP1", DRV_GRP0),
  272. MTK_PIN(88, "RCN", DRV_GRP0),
  273. MTK_PIN(89, "RCP", DRV_GRP0),
  274. MTK_PIN(90, "RDN2", DRV_GRP0),
  275. MTK_PIN(91, "RDP2", DRV_GRP0),
  276. MTK_PIN(92, "RDN3", DRV_GRP0),
  277. MTK_PIN(93, "RDP3", DRV_GRP0),
  278. MTK_PIN(94, "RCN_A", DRV_GRP0),
  279. MTK_PIN(95, "RCP_A", DRV_GRP0),
  280. MTK_PIN(96, "RDN1_A", DRV_GRP0),
  281. MTK_PIN(97, "RDP1_A", DRV_GRP0),
  282. MTK_PIN(98, "RDN0_A", DRV_GRP0),
  283. MTK_PIN(99, "RDP0_A", DRV_GRP0),
  284. MTK_PIN(100, "CMDDAT0", DRV_GRP2),
  285. MTK_PIN(101, "CMDDAT1", DRV_GRP2),
  286. MTK_PIN(102, "CMMCLK", DRV_GRP2),
  287. MTK_PIN(103, "CMPCLK", DRV_GRP2),
  288. MTK_PIN(104, "MSDC1_CMD", DRV_GRP4),
  289. MTK_PIN(105, "MSDC1_CLK", DRV_GRP4),
  290. MTK_PIN(106, "MSDC1_DAT0", DRV_GRP4),
  291. MTK_PIN(107, "MSDC1_DAT1", DRV_GRP4),
  292. MTK_PIN(108, "MSDC1_DAT2", DRV_GRP4),
  293. MTK_PIN(109, "MSDC1_DAT3", DRV_GRP4),
  294. MTK_PIN(110, "MSDC0_DAT7", DRV_GRP4),
  295. MTK_PIN(111, "MSDC0_DAT6", DRV_GRP4),
  296. MTK_PIN(112, "MSDC0_DAT5", DRV_GRP4),
  297. MTK_PIN(113, "MSDC0_DAT4", DRV_GRP4),
  298. MTK_PIN(114, "MSDC0_RSTB", DRV_GRP4),
  299. MTK_PIN(115, "MSDC0_CMD", DRV_GRP4),
  300. MTK_PIN(116, "MSDC0_CLK", DRV_GRP4),
  301. MTK_PIN(117, "MSDC0_DAT3", DRV_GRP4),
  302. MTK_PIN(118, "MSDC0_DAT2", DRV_GRP4),
  303. MTK_PIN(119, "MSDC0_DAT1", DRV_GRP4),
  304. MTK_PIN(120, "MSDC0_DAT0", DRV_GRP4),
  305. };
  306. /* List all groups consisting of these pins dedicated to the enablement of
  307. * certain hardware block and the corresponding mode for all of the pins.
  308. * The hardware probably has multiple combinations of these pinouts.
  309. */
  310. /* UART */
  311. static int mt8516_uart0_0_rxd_txd_pins[] = { 62, 63, };
  312. static int mt8516_uart0_0_rxd_txd_funcs[] = { 1, 1, };
  313. static int mt8516_uart1_0_rxd_txd_pins[] = { 64, 65, };
  314. static int mt8516_uart1_0_rxd_txd_funcs[] = { 1, 1, };
  315. static int mt8516_uart2_0_rxd_txd_pins[] = { 34, 35, };
  316. static int mt8516_uart2_0_rxd_txd_funcs[] = { 1, 1, };
  317. /* Joint those groups owning the same capability in user point of view which
  318. * allows that people tend to use through the device tree.
  319. */
  320. static const char *const mt8516_uart_groups[] = { "uart0_0_rxd_txd",
  321. "uart1_0_rxd_txd",
  322. "uart2_0_rxd_txd", };
  323. /* MMC0 */
  324. static int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, 118,
  325. 119, 120, };
  326. static int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
  327. static const struct mtk_group_desc mt8516_groups[] = {
  328. PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8516_uart0_0_rxd_txd),
  329. PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8516_uart1_0_rxd_txd),
  330. PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8516_uart2_0_rxd_txd),
  331. PINCTRL_PIN_GROUP("msdc0", mt8516_msdc0),
  332. };
  333. static const char *const mt8516_msdc_groups[] = { "msdc0" };
  334. static const struct mtk_function_desc mt8516_functions[] = {
  335. {"uart", mt8516_uart_groups, ARRAY_SIZE(mt8516_uart_groups)},
  336. {"msdc", mt8516_msdc_groups, ARRAY_SIZE(mt8516_msdc_groups)},
  337. };
  338. static struct mtk_pinctrl_soc mt8516_data = {
  339. .name = "mt8516_pinctrl",
  340. .reg_cal = mt8516_reg_cals,
  341. .pins = mt8516_pins,
  342. .npins = ARRAY_SIZE(mt8516_pins),
  343. .grps = mt8516_groups,
  344. .ngrps = ARRAY_SIZE(mt8516_groups),
  345. .funcs = mt8516_functions,
  346. .nfuncs = ARRAY_SIZE(mt8516_functions),
  347. .gpio_mode = 0,
  348. .rev = MTK_PINCTRL_V1,
  349. };
  350. static int mtk_pinctrl_mt8516_probe(struct udevice *dev)
  351. {
  352. return mtk_pinctrl_common_probe(dev, &mt8516_data);
  353. }
  354. static const struct udevice_id mt8516_pctrl_match[] = {
  355. { .compatible = "mediatek,mt8516-pinctrl" },
  356. { /* sentinel */ }
  357. };
  358. U_BOOT_DRIVER(mt8516_pinctrl) = {
  359. .name = "mt8516_pinctrl",
  360. .id = UCLASS_PINCTRL,
  361. .of_match = mt8516_pctrl_match,
  362. .ops = &mtk_pinctrl_ops,
  363. .probe = mtk_pinctrl_mt8516_probe,
  364. .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
  365. };