pinctrl-mt8512.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 MediaTek Inc.
  4. * Author: Mingming Lee <mingming.lee@mediatek.com>
  5. */
  6. #include <dm.h>
  7. #include "pinctrl-mtk-common.h"
  8. #define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
  9. PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
  10. _x_bits, 32, false)
  11. #define PIN_FIELDS(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
  12. PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
  13. _x_bits, 32, true)
  14. #define PIN_FIELD30(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
  15. PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
  16. _x_bits, 30, false)
  17. static const struct mtk_pin_field_calc mt8512_pin_mode_range[] = {
  18. PIN_FIELD30(0, 115, 0x1E0, 0x10, 0, 3),
  19. };
  20. static const struct mtk_pin_field_calc mt8512_pin_dir_range[] = {
  21. PIN_FIELD(0, 115, 0x140, 0x10, 0, 1),
  22. };
  23. static const struct mtk_pin_field_calc mt8512_pin_di_range[] = {
  24. PIN_FIELD(0, 115, 0x000, 0x10, 0, 1),
  25. };
  26. static const struct mtk_pin_field_calc mt8512_pin_do_range[] = {
  27. PIN_FIELD(0, 115, 0x0A0, 0x10, 0, 1),
  28. };
  29. static const struct mtk_pin_field_calc mt8512_pin_pullen_range[] = {
  30. PIN_FIELD(0, 115, 0x860, 0x10, 0, 1),
  31. };
  32. static const struct mtk_pin_field_calc mt8512_pin_pullsel_range[] = {
  33. PIN_FIELD(0, 115, 0x900, 0x10, 0, 1),
  34. };
  35. static const struct mtk_pin_field_calc mt8512_pin_ies_range[] = {
  36. PIN_FIELDS(0, 2, 0x410, 0x10, 0, 1),
  37. PIN_FIELDS(3, 5, 0x410, 0x10, 1, 1),
  38. PIN_FIELDS(6, 7, 0x410, 0x10, 2, 1),
  39. PIN_FIELDS(8, 11, 0x410, 0x10, 3, 1),
  40. PIN_FIELDS(12, 15, 0x410, 0x10, 4, 1),
  41. PIN_FIELDS(16, 19, 0x410, 0x10, 5, 1),
  42. PIN_FIELD(20, 20, 0x410, 0x10, 6, 1),
  43. PIN_FIELDS(21, 25, 0x410, 0x10, 7, 1),
  44. PIN_FIELDS(26, 27, 0x410, 0x10, 8, 1),
  45. PIN_FIELDS(28, 31, 0x410, 0x10, 9, 1),
  46. PIN_FIELD(32, 32, 0x410, 0x10, 10, 1),
  47. PIN_FIELDS(33, 39, 0x410, 0x10, 11, 1),
  48. PIN_FIELD(40, 40, 0x410, 0x10, 12, 1),
  49. PIN_FIELDS(41, 43, 0x410, 0x10, 13, 1),
  50. PIN_FIELDS(44, 47, 0x410, 0x10, 14, 1),
  51. PIN_FIELDS(48, 51, 0x410, 0x10, 15, 1),
  52. PIN_FIELDS(52, 53, 0x410, 0x10, 16, 1),
  53. PIN_FIELDS(54, 57, 0x410, 0x10, 17, 1),
  54. PIN_FIELDS(58, 63, 0x410, 0x10, 18, 1),
  55. PIN_FIELDS(64, 65, 0x410, 0x10, 19, 1),
  56. PIN_FIELDS(66, 67, 0x410, 0x10, 20, 1),
  57. PIN_FIELDS(68, 69, 0x410, 0x10, 21, 1),
  58. PIN_FIELD(70, 70, 0x410, 0x10, 22, 1),
  59. PIN_FIELD(71, 71, 0x410, 0x10, 23, 1),
  60. PIN_FIELD(72, 72, 0x410, 0x10, 24, 1),
  61. PIN_FIELD(73, 73, 0x410, 0x10, 25, 1),
  62. PIN_FIELD(74, 74, 0x410, 0x10, 26, 1),
  63. PIN_FIELD(75, 75, 0x410, 0x10, 27, 1),
  64. PIN_FIELD(76, 76, 0x410, 0x10, 28, 1),
  65. PIN_FIELD(77, 77, 0x410, 0x10, 29, 1),
  66. PIN_FIELD(78, 78, 0x410, 0x10, 30, 1),
  67. PIN_FIELD(79, 79, 0x410, 0x10, 31, 1),
  68. PIN_FIELD(80, 80, 0x420, 0x10, 0, 1),
  69. PIN_FIELD(81, 81, 0x420, 0x10, 1, 1),
  70. PIN_FIELD(82, 82, 0x420, 0x10, 2, 1),
  71. PIN_FIELD(83, 83, 0x420, 0x10, 3, 1),
  72. PIN_FIELD(84, 84, 0x420, 0x10, 4, 1),
  73. PIN_FIELDS(85, 86, 0x420, 0x10, 5, 1),
  74. PIN_FIELD(87, 87, 0x420, 0x10, 6, 1),
  75. PIN_FIELDS(88, 91, 0x420, 0x10, 7, 1),
  76. PIN_FIELDS(92, 98, 0x420, 0x10, 8, 1),
  77. PIN_FIELDS(99, 101, 0x420, 0x10, 9, 1),
  78. PIN_FIELDS(102, 104, 0x420, 0x10, 10, 1),
  79. PIN_FIELDS(105, 111, 0x420, 0x10, 11, 1),
  80. PIN_FIELDS(112, 115, 0x420, 0x10, 12, 1),
  81. };
  82. static const struct mtk_pin_field_calc mt8512_pin_smt_range[] = {
  83. PIN_FIELDS(0, 2, 0x470, 0x10, 0, 1),
  84. PIN_FIELDS(3, 5, 0x470, 0x10, 1, 1),
  85. PIN_FIELDS(6, 7, 0x470, 0x10, 2, 1),
  86. PIN_FIELDS(8, 11, 0x470, 0x10, 3, 1),
  87. PIN_FIELDS(12, 15, 0x470, 0x10, 4, 1),
  88. PIN_FIELDS(16, 19, 0x470, 0x10, 5, 1),
  89. PIN_FIELD(20, 20, 0x470, 0x10, 6, 1),
  90. PIN_FIELDS(21, 25, 0x470, 0x10, 7, 1),
  91. PIN_FIELDS(26, 27, 0x470, 0x10, 8, 1),
  92. PIN_FIELDS(28, 31, 0x470, 0x10, 9, 1),
  93. PIN_FIELD(32, 32, 0x470, 0x10, 10, 1),
  94. PIN_FIELDS(33, 39, 0x470, 0x10, 11, 1),
  95. PIN_FIELD(40, 40, 0x470, 0x10, 12, 1),
  96. PIN_FIELDS(41, 43, 0x470, 0x10, 13, 1),
  97. PIN_FIELDS(44, 47, 0x470, 0x10, 14, 1),
  98. PIN_FIELDS(48, 51, 0x470, 0x10, 15, 1),
  99. PIN_FIELDS(52, 53, 0x470, 0x10, 16, 1),
  100. PIN_FIELDS(54, 57, 0x470, 0x10, 17, 1),
  101. PIN_FIELDS(58, 63, 0x470, 0x10, 18, 1),
  102. PIN_FIELDS(64, 65, 0x470, 0x10, 19, 1),
  103. PIN_FIELDS(66, 67, 0x470, 0x10, 20, 1),
  104. PIN_FIELDS(68, 69, 0x470, 0x10, 21, 1),
  105. PIN_FIELD(70, 70, 0x470, 0x10, 22, 1),
  106. PIN_FIELD(71, 71, 0x470, 0x10, 23, 1),
  107. PIN_FIELD(72, 72, 0x470, 0x10, 24, 1),
  108. PIN_FIELD(73, 73, 0x470, 0x10, 25, 1),
  109. PIN_FIELD(74, 74, 0x470, 0x10, 26, 1),
  110. PIN_FIELD(75, 75, 0x470, 0x10, 27, 1),
  111. PIN_FIELD(76, 76, 0x470, 0x10, 28, 1),
  112. PIN_FIELD(77, 77, 0x470, 0x10, 29, 1),
  113. PIN_FIELD(78, 78, 0x470, 0x10, 30, 1),
  114. PIN_FIELD(79, 79, 0x470, 0x10, 31, 1),
  115. PIN_FIELD(80, 80, 0x480, 0x10, 0, 1),
  116. PIN_FIELD(81, 81, 0x480, 0x10, 1, 1),
  117. PIN_FIELD(82, 82, 0x480, 0x10, 2, 1),
  118. PIN_FIELD(83, 83, 0x480, 0x10, 3, 1),
  119. PIN_FIELD(84, 84, 0x480, 0x10, 4, 1),
  120. PIN_FIELDS(85, 86, 0x480, 0x10, 5, 1),
  121. PIN_FIELD(87, 87, 0x480, 0x10, 6, 1),
  122. PIN_FIELDS(88, 91, 0x480, 0x10, 7, 1),
  123. PIN_FIELDS(92, 98, 0x480, 0x10, 8, 1),
  124. PIN_FIELDS(99, 101, 0x480, 0x10, 9, 1),
  125. PIN_FIELDS(102, 104, 0x480, 0x10, 10, 1),
  126. PIN_FIELDS(105, 111, 0x480, 0x10, 11, 1),
  127. PIN_FIELDS(112, 115, 0x480, 0x10, 12, 1),
  128. };
  129. static const struct mtk_pin_field_calc mt8512_pin_drv_range[] = {
  130. PIN_FIELDS(0, 2, 0x710, 0x10, 0, 4),
  131. PIN_FIELDS(3, 5, 0x710, 0x10, 4, 4),
  132. PIN_FIELDS(6, 7, 0x710, 0x10, 8, 4),
  133. PIN_FIELDS(8, 11, 0x710, 0x10, 12, 4),
  134. PIN_FIELDS(12, 15, 0x710, 0x10, 16, 4),
  135. PIN_FIELDS(16, 19, 0x710, 0x10, 20, 4),
  136. PIN_FIELD(20, 20, 0x710, 0x10, 24, 4),
  137. PIN_FIELDS(21, 25, 0x710, 0x10, 28, 4),
  138. PIN_FIELDS(26, 27, 0x720, 0x10, 0, 4),
  139. PIN_FIELDS(28, 31, 0x720, 0x10, 4, 4),
  140. PIN_FIELD(32, 32, 0x720, 0x10, 8, 4),
  141. PIN_FIELDS(33, 39, 0x720, 0x10, 12, 4),
  142. PIN_FIELD(40, 40, 0x720, 0x10, 16, 4),
  143. PIN_FIELDS(41, 43, 0x720, 0x10, 20, 4),
  144. PIN_FIELDS(44, 47, 0x720, 0x10, 24, 4),
  145. PIN_FIELDS(48, 51, 0x720, 0x10, 28, 4),
  146. PIN_FIELDS(52, 53, 0x730, 0x10, 0, 4),
  147. PIN_FIELDS(54, 57, 0x730, 0x10, 4, 4),
  148. PIN_FIELDS(58, 63, 0x730, 0x10, 8, 4),
  149. PIN_FIELDS(64, 65, 0x730, 0x10, 12, 4),
  150. PIN_FIELDS(66, 67, 0x730, 0x10, 16, 4),
  151. PIN_FIELDS(68, 69, 0x730, 0x10, 20, 4),
  152. PIN_FIELD(70, 70, 0x730, 0x10, 24, 4),
  153. PIN_FIELD(71, 71, 0x730, 0x10, 28, 4),
  154. PIN_FIELDS(72, 75, 0x740, 0x10, 0, 4),
  155. PIN_FIELDS(76, 79, 0x740, 0x10, 16, 4),
  156. PIN_FIELD(80, 80, 0x750, 0x10, 0, 4),
  157. PIN_FIELD(81, 81, 0x750, 0x10, 4, 4),
  158. PIN_FIELD(82, 82, 0x750, 0x10, 8, 4),
  159. PIN_FIELDS(83, 86, 0x740, 0x10, 16, 4),
  160. PIN_FIELD(87, 87, 0x750, 0x10, 24, 4),
  161. PIN_FIELDS(88, 91, 0x750, 0x10, 28, 4),
  162. PIN_FIELDS(92, 98, 0x760, 0x10, 0, 4),
  163. PIN_FIELDS(99, 101, 0x760, 0x10, 4, 4),
  164. PIN_FIELDS(102, 104, 0x760, 0x10, 8, 4),
  165. PIN_FIELDS(105, 111, 0x760, 0x10, 12, 4),
  166. PIN_FIELDS(112, 115, 0x760, 0x10, 16, 4),
  167. };
  168. static const struct mtk_pin_reg_calc mt8512_reg_cals[] = {
  169. [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8512_pin_mode_range),
  170. [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8512_pin_dir_range),
  171. [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8512_pin_di_range),
  172. [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8512_pin_do_range),
  173. [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8512_pin_ies_range),
  174. [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8512_pin_smt_range),
  175. [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8512_pin_pullsel_range),
  176. [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8512_pin_pullen_range),
  177. [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8512_pin_drv_range),
  178. };
  179. static const struct mtk_pin_desc mt8512_pins[] = {
  180. MTK_PIN(0, "GPIO0", DRV_GRP4),
  181. MTK_PIN(1, "GPIO1", DRV_GRP4),
  182. MTK_PIN(2, "GPIO2", DRV_GRP4),
  183. MTK_PIN(3, "GPIO3", DRV_GRP4),
  184. MTK_PIN(4, "GPIO4", DRV_GRP4),
  185. MTK_PIN(5, "GPIO5", DRV_GRP4),
  186. MTK_PIN(6, "GPIO6", DRV_GRP4),
  187. MTK_PIN(7, "GPIO7", DRV_GRP4),
  188. MTK_PIN(8, "GPIO8", DRV_GRP4),
  189. MTK_PIN(9, "GPIO9", DRV_GRP4),
  190. MTK_PIN(10, "GPIO10", DRV_GRP4),
  191. MTK_PIN(11, "GPIO11", DRV_GRP4),
  192. MTK_PIN(12, "GPIO12", DRV_GRP4),
  193. MTK_PIN(13, "GPIO13", DRV_GRP4),
  194. MTK_PIN(14, "GPIO14", DRV_GRP4),
  195. MTK_PIN(15, "GPIO15", DRV_GRP4),
  196. MTK_PIN(16, "GPIO16", DRV_GRP4),
  197. MTK_PIN(17, "GPIO17", DRV_GRP4),
  198. MTK_PIN(18, "GPIO18", DRV_GRP4),
  199. MTK_PIN(19, "GPIO19", DRV_GRP4),
  200. MTK_PIN(20, "GPIO20", DRV_GRP4),
  201. MTK_PIN(21, "AUDIO_SYNC", DRV_GRP4),
  202. MTK_PIN(22, "WIFI_INTB", DRV_GRP4),
  203. MTK_PIN(23, "BT_INTB", DRV_GRP4),
  204. MTK_PIN(24, "BT_STEREO", DRV_GRP4),
  205. MTK_PIN(25, "RSTNB", DRV_GRP4),
  206. MTK_PIN(26, "USB_ID", DRV_GRP4),
  207. MTK_PIN(27, "USB_DRV", DRV_GRP4),
  208. MTK_PIN(28, "EINT_GAUGEING", DRV_GRP4),
  209. MTK_PIN(29, "CHG_IRQ", DRV_GRP4),
  210. MTK_PIN(30, "CHG_OTG", DRV_GRP4),
  211. MTK_PIN(31, "CHG_CEB", DRV_GRP4),
  212. MTK_PIN(32, "FL_EN", DRV_GRP4),
  213. MTK_PIN(33, "WAN_SMS_RDY", DRV_GRP4),
  214. MTK_PIN(34, "SOC2WAN_RESET", DRV_GRP4),
  215. MTK_PIN(35, "WAN_FM_RDY", DRV_GRP4),
  216. MTK_PIN(36, "WAN_DIS", DRV_GRP4),
  217. MTK_PIN(37, "WAN_VBUS_EN", DRV_GRP4),
  218. MTK_PIN(38, "WAN_VBAT_EN", DRV_GRP4),
  219. MTK_PIN(39, "WAN_PWR_EN", DRV_GRP4),
  220. MTK_PIN(40, "KPROW0", DRV_GRP4),
  221. MTK_PIN(41, "KPROW1", DRV_GRP4),
  222. MTK_PIN(42, "KPCOL0", DRV_GRP4),
  223. MTK_PIN(43, "KPCOL1", DRV_GRP4),
  224. MTK_PIN(44, "PWM0", DRV_GRP4),
  225. MTK_PIN(45, "PWM1", DRV_GRP4),
  226. MTK_PIN(46, "PWM2", DRV_GRP4),
  227. MTK_PIN(47, "PWM3", DRV_GRP4),
  228. MTK_PIN(48, "JTMS", DRV_GRP4),
  229. MTK_PIN(49, "JTCK", DRV_GRP4),
  230. MTK_PIN(50, "JTDI", DRV_GRP4),
  231. MTK_PIN(51, "JTDO", DRV_GRP4),
  232. MTK_PIN(52, "URXD0", DRV_GRP4),
  233. MTK_PIN(53, "UTXD0", DRV_GRP4),
  234. MTK_PIN(54, "URXD1", DRV_GRP4),
  235. MTK_PIN(55, "UTXD1", DRV_GRP4),
  236. MTK_PIN(56, "URTS1", DRV_GRP4),
  237. MTK_PIN(57, "UCTS1", DRV_GRP4),
  238. MTK_PIN(58, "RTC32K_CK", DRV_GRP4),
  239. MTK_PIN(59, "PMIC_DVS_REQ0", DRV_GRP4),
  240. MTK_PIN(60, "PMIC_DVS_REQ1", DRV_GRP4),
  241. MTK_PIN(61, "WATCHDOG", DRV_GRP4),
  242. MTK_PIN(62, "PMIC_INT", DRV_GRP4),
  243. MTK_PIN(63, "SUSPEND", DRV_GRP4),
  244. MTK_PIN(64, "SDA0", DRV_GRP4),
  245. MTK_PIN(65, "SCL0", DRV_GRP4),
  246. MTK_PIN(66, "SDA1", DRV_GRP4),
  247. MTK_PIN(67, "SCL1", DRV_GRP4),
  248. MTK_PIN(68, "SDA2", DRV_GRP4),
  249. MTK_PIN(69, "SCL2", DRV_GRP4),
  250. MTK_PIN(70, "MSDC1_CMD", DRV_GRP4),
  251. MTK_PIN(71, "MSDC1_CLK", DRV_GRP4),
  252. MTK_PIN(72, "MSDC1_DAT0", DRV_GRP4),
  253. MTK_PIN(73, "MSDC1_DAT1", DRV_GRP4),
  254. MTK_PIN(74, "MSDC1_DAT2", DRV_GRP4),
  255. MTK_PIN(75, "MSDC1_DAT3", DRV_GRP4),
  256. MTK_PIN(76, "MSDC0_DAT7", DRV_GRP4),
  257. MTK_PIN(77, "MSDC0_DAT6", DRV_GRP4),
  258. MTK_PIN(78, "MSDC0_DAT5", DRV_GRP4),
  259. MTK_PIN(79, "MSDC0_DAT4", DRV_GRP4),
  260. MTK_PIN(80, "MSDC0_RSTB", DRV_GRP4),
  261. MTK_PIN(81, "MSDC0_CMD", DRV_GRP4),
  262. MTK_PIN(82, "MSDC0_CLK", DRV_GRP4),
  263. MTK_PIN(83, "MSDC0_DAT3", DRV_GRP4),
  264. MTK_PIN(84, "MSDC0_DAT2", DRV_GRP4),
  265. MTK_PIN(85, "MSDC0_DAT1", DRV_GRP4),
  266. MTK_PIN(86, "MSDC0_DAT0", DRV_GRP4),
  267. MTK_PIN(87, "SPDIF", DRV_GRP4),
  268. MTK_PIN(88, "PCM_CLK", DRV_GRP4),
  269. MTK_PIN(89, "PCM_SYNC", DRV_GRP4),
  270. MTK_PIN(90, "PCM_RX", DRV_GRP4),
  271. MTK_PIN(91, "PCM_TX", DRV_GRP4),
  272. MTK_PIN(92, "I2SIN_MCLK", DRV_GRP4),
  273. MTK_PIN(93, "I2SIN_LRCK", DRV_GRP4),
  274. MTK_PIN(94, "I2SIN_BCK", DRV_GRP4),
  275. MTK_PIN(95, "I2SIN_DAT0", DRV_GRP4),
  276. MTK_PIN(96, "I2SIN_DAT1", DRV_GRP4),
  277. MTK_PIN(97, "I2SIN_DAT2", DRV_GRP4),
  278. MTK_PIN(98, "I2SIN_DAT3", DRV_GRP4),
  279. MTK_PIN(99, "DMIC0_CLK", DRV_GRP4),
  280. MTK_PIN(100, "DMIC0_DAT0", DRV_GRP4),
  281. MTK_PIN(101, "DMIC0_DAT1", DRV_GRP4),
  282. MTK_PIN(102, "DMIC1_CLK", DRV_GRP4),
  283. MTK_PIN(103, "DMIC1_DAT0", DRV_GRP4),
  284. MTK_PIN(104, "DMIC1_DAT1", DRV_GRP4),
  285. MTK_PIN(105, "I2SO_BCK", DRV_GRP4),
  286. MTK_PIN(106, "I2SO_LRCK", DRV_GRP4),
  287. MTK_PIN(107, "I2SO_MCLK", DRV_GRP4),
  288. MTK_PIN(108, "I2SO_DAT0", DRV_GRP4),
  289. MTK_PIN(109, "I2SO_DAT1", DRV_GRP4),
  290. MTK_PIN(110, "I2SO_DAT2", DRV_GRP4),
  291. MTK_PIN(111, "I2SO_DAT3", DRV_GRP4),
  292. MTK_PIN(112, "SPI_CSB", DRV_GRP4),
  293. MTK_PIN(113, "SPI_CLK", DRV_GRP4),
  294. MTK_PIN(114, "SPI_MISO", DRV_GRP4),
  295. MTK_PIN(115, "SPI_MOSI", DRV_GRP4),
  296. };
  297. /* List all groups consisting of these pins dedicated to the enablement of
  298. * certain hardware block and the corresponding mode for all of the pins.
  299. * The hardware probably has multiple combinations of these pinouts.
  300. */
  301. /* UART */
  302. static int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, };
  303. static int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, };
  304. static int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, };
  305. static int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, };
  306. static int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, };
  307. static int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, };
  308. /* Joint those groups owning the same capability in user point of view which
  309. * allows that people tend to use through the device tree.
  310. */
  311. static const char *const mt8512_uart_groups[] = { "uart0_0_rxd_txd",
  312. "uart1_0_rxd_txd",
  313. "uart2_0_rxd_txd", };
  314. /* SNAND */
  315. static int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, };
  316. static int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
  317. /* MMC0 */
  318. static int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84,
  319. 85, 86, };
  320. static int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
  321. static const struct mtk_group_desc mt8512_groups[] = {
  322. PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8512_uart0_0_rxd_txd),
  323. PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8512_uart1_0_rxd_txd),
  324. PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8512_uart2_0_rxd_txd),
  325. PINCTRL_PIN_GROUP("msdc0", mt8512_msdc0),
  326. PINCTRL_PIN_GROUP("snfi", mt8512_snfi),
  327. };
  328. static const char *const mt8512_msdc_groups[] = { "msdc0" };
  329. static const struct mtk_function_desc mt8512_functions[] = {
  330. {"uart", mt8512_uart_groups, ARRAY_SIZE(mt8512_uart_groups)},
  331. {"msdc", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)},
  332. {"snand", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)},
  333. };
  334. static struct mtk_pinctrl_soc mt8512_data = {
  335. .name = "mt8512_pinctrl",
  336. .reg_cal = mt8512_reg_cals,
  337. .pins = mt8512_pins,
  338. .npins = ARRAY_SIZE(mt8512_pins),
  339. .grps = mt8512_groups,
  340. .ngrps = ARRAY_SIZE(mt8512_groups),
  341. .funcs = mt8512_functions,
  342. .nfuncs = ARRAY_SIZE(mt8512_functions),
  343. };
  344. static int mtk_pinctrl_mt8512_probe(struct udevice *dev)
  345. {
  346. return mtk_pinctrl_common_probe(dev, &mt8512_data);
  347. }
  348. static const struct udevice_id mt8512_pctrl_match[] = {
  349. { .compatible = "mediatek,mt8512-pinctrl" },
  350. { /* sentinel */ }
  351. };
  352. U_BOOT_DRIVER(mt8512_pinctrl) = {
  353. .name = "mt8512_pinctrl",
  354. .id = UCLASS_PINCTRL,
  355. .of_match = mt8512_pctrl_match,
  356. .ops = &mtk_pinctrl_ops,
  357. .probe = mtk_pinctrl_mt8512_probe,
  358. .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
  359. };