pinctrl-mt7622.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 MediaTek Inc.
  4. * Author: Sam Shih <sam.shih@mediatek.com>
  5. */
  6. #include <dm.h>
  7. #include "pinctrl-mtk-common.h"
  8. #define MT7622_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1)
  9. #define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
  10. PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
  11. _x_bits, 32, 0)
  12. #define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
  13. PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
  14. _x_bits, 32, 1)
  15. static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
  16. PIN_FIELD(0, 0, 0x320, 0x10, 16, 4),
  17. PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4),
  18. PIN_FIELD(5, 5, 0x320, 0x10, 0, 4),
  19. PINS_FIELD(6, 7, 0x300, 0x10, 4, 4),
  20. PIN_FIELD(8, 9, 0x350, 0x10, 20, 4),
  21. PINS_FIELD(10, 13, 0x300, 0x10, 8, 4),
  22. PIN_FIELD(14, 15, 0x320, 0x10, 4, 4),
  23. PIN_FIELD(16, 17, 0x320, 0x10, 20, 4),
  24. PIN_FIELD(18, 21, 0x310, 0x10, 16, 4),
  25. PIN_FIELD(22, 22, 0x380, 0x10, 16, 4),
  26. PINS_FIELD(23, 24, 0x300, 0x10, 24, 4),
  27. PINS_FIELD(25, 36, 0x300, 0x10, 12, 4),
  28. PINS_FIELD(37, 50, 0x300, 0x10, 20, 4),
  29. PIN_FIELD(51, 70, 0x330, 0x10, 4, 4),
  30. PINS_FIELD(71, 72, 0x300, 0x10, 16, 4),
  31. PIN_FIELD(73, 76, 0x310, 0x10, 0, 4),
  32. PIN_FIELD(77, 77, 0x320, 0x10, 28, 4),
  33. PIN_FIELD(78, 78, 0x320, 0x10, 12, 4),
  34. PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4),
  35. PIN_FIELD(83, 83, 0x350, 0x10, 28, 4),
  36. PIN_FIELD(84, 84, 0x330, 0x10, 0, 4),
  37. PIN_FIELD(85, 90, 0x360, 0x10, 4, 4),
  38. PIN_FIELD(91, 94, 0x390, 0x10, 16, 4),
  39. PIN_FIELD(95, 97, 0x380, 0x10, 20, 4),
  40. PIN_FIELD(98, 101, 0x390, 0x10, 0, 4),
  41. PIN_FIELD(102, 102, 0x360, 0x10, 0, 4),
  42. };
  43. static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
  44. PIN_FIELD(0, 102, 0x0, 0x10, 0, 1),
  45. };
  46. static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
  47. PIN_FIELD(0, 102, 0x200, 0x10, 0, 1),
  48. };
  49. static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
  50. PIN_FIELD(0, 102, 0x100, 0x10, 0, 1),
  51. };
  52. static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
  53. PIN_FIELD(0, 31, 0x920, 0x10, 0, 1),
  54. PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1),
  55. PIN_FIELD(51, 70, 0x820, 0x10, 0, 1),
  56. PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1),
  57. PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1),
  58. PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1),
  59. PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1),
  60. };
  61. static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
  62. PIN_FIELD(0, 31, 0x930, 0x10, 0, 1),
  63. PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1),
  64. PIN_FIELD(51, 70, 0x830, 0x10, 0, 1),
  65. PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1),
  66. PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1),
  67. PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1),
  68. PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1),
  69. };
  70. static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
  71. PIN_FIELD(0, 31, 0x940, 0x10, 0, 1),
  72. PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1),
  73. PIN_FIELD(51, 70, 0x840, 0x10, 0, 1),
  74. PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1),
  75. PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1),
  76. PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1),
  77. PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1),
  78. };
  79. static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
  80. PIN_FIELD(0, 31, 0x960, 0x10, 0, 1),
  81. PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1),
  82. PIN_FIELD(51, 70, 0x860, 0x10, 0, 1),
  83. PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1),
  84. PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1),
  85. PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1),
  86. PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1),
  87. };
  88. static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
  89. PIN_FIELD(0, 31, 0x970, 0x10, 0, 1),
  90. PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1),
  91. PIN_FIELD(51, 70, 0x870, 0x10, 0, 1),
  92. PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1),
  93. PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1),
  94. PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1),
  95. PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1),
  96. };
  97. static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
  98. [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range),
  99. [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range),
  100. [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range),
  101. [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range),
  102. [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range),
  103. [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range),
  104. [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range),
  105. [PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range),
  106. [PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range),
  107. };
  108. static const struct mtk_pin_desc mt7622_pins[] = {
  109. MT7622_PIN(0, "GPIO_A"),
  110. MT7622_PIN(1, "I2S1_IN"),
  111. MT7622_PIN(2, "I2S1_OUT"),
  112. MT7622_PIN(3, "I2S_BCLK"),
  113. MT7622_PIN(4, "I2S_WS"),
  114. MT7622_PIN(5, "I2S_MCLK"),
  115. MT7622_PIN(6, "TXD0"),
  116. MT7622_PIN(7, "RXD0"),
  117. MT7622_PIN(8, "SPI_WP"),
  118. MT7622_PIN(9, "SPI_HOLD"),
  119. MT7622_PIN(10, "SPI_CLK"),
  120. MT7622_PIN(11, "SPI_MOSI"),
  121. MT7622_PIN(12, "SPI_MISO"),
  122. MT7622_PIN(13, "SPI_CS"),
  123. MT7622_PIN(14, "I2C_SDA"),
  124. MT7622_PIN(15, "I2C_SCL"),
  125. MT7622_PIN(16, "I2S2_IN"),
  126. MT7622_PIN(17, "I2S3_IN"),
  127. MT7622_PIN(18, "I2S4_IN"),
  128. MT7622_PIN(19, "I2S2_OUT"),
  129. MT7622_PIN(20, "I2S3_OUT"),
  130. MT7622_PIN(21, "I2S4_OUT"),
  131. MT7622_PIN(22, "GPIO_B"),
  132. MT7622_PIN(23, "MDC"),
  133. MT7622_PIN(24, "MDIO"),
  134. MT7622_PIN(25, "G2_TXD0"),
  135. MT7622_PIN(26, "G2_TXD1"),
  136. MT7622_PIN(27, "G2_TXD2"),
  137. MT7622_PIN(28, "G2_TXD3"),
  138. MT7622_PIN(29, "G2_TXEN"),
  139. MT7622_PIN(30, "G2_TXC"),
  140. MT7622_PIN(31, "G2_RXD0"),
  141. MT7622_PIN(32, "G2_RXD1"),
  142. MT7622_PIN(33, "G2_RXD2"),
  143. MT7622_PIN(34, "G2_RXD3"),
  144. MT7622_PIN(35, "G2_RXDV"),
  145. MT7622_PIN(36, "G2_RXC"),
  146. MT7622_PIN(37, "NCEB"),
  147. MT7622_PIN(38, "NWEB"),
  148. MT7622_PIN(39, "NREB"),
  149. MT7622_PIN(40, "NDL4"),
  150. MT7622_PIN(41, "NDL5"),
  151. MT7622_PIN(42, "NDL6"),
  152. MT7622_PIN(43, "NDL7"),
  153. MT7622_PIN(44, "NRB"),
  154. MT7622_PIN(45, "NCLE"),
  155. MT7622_PIN(46, "NALE"),
  156. MT7622_PIN(47, "NDL0"),
  157. MT7622_PIN(48, "NDL1"),
  158. MT7622_PIN(49, "NDL2"),
  159. MT7622_PIN(50, "NDL3"),
  160. MT7622_PIN(51, "MDI_TP_P0"),
  161. MT7622_PIN(52, "MDI_TN_P0"),
  162. MT7622_PIN(53, "MDI_RP_P0"),
  163. MT7622_PIN(54, "MDI_RN_P0"),
  164. MT7622_PIN(55, "MDI_TP_P1"),
  165. MT7622_PIN(56, "MDI_TN_P1"),
  166. MT7622_PIN(57, "MDI_RP_P1"),
  167. MT7622_PIN(58, "MDI_RN_P1"),
  168. MT7622_PIN(59, "MDI_RP_P2"),
  169. MT7622_PIN(60, "MDI_RN_P2"),
  170. MT7622_PIN(61, "MDI_TP_P2"),
  171. MT7622_PIN(62, "MDI_TN_P2"),
  172. MT7622_PIN(63, "MDI_TP_P3"),
  173. MT7622_PIN(64, "MDI_TN_P3"),
  174. MT7622_PIN(65, "MDI_RP_P3"),
  175. MT7622_PIN(66, "MDI_RN_P3"),
  176. MT7622_PIN(67, "MDI_RP_P4"),
  177. MT7622_PIN(68, "MDI_RN_P4"),
  178. MT7622_PIN(69, "MDI_TP_P4"),
  179. MT7622_PIN(70, "MDI_TN_P4"),
  180. MT7622_PIN(71, "PMIC_SCL"),
  181. MT7622_PIN(72, "PMIC_SDA"),
  182. MT7622_PIN(73, "SPIC1_CLK"),
  183. MT7622_PIN(74, "SPIC1_MOSI"),
  184. MT7622_PIN(75, "SPIC1_MISO"),
  185. MT7622_PIN(76, "SPIC1_CS"),
  186. MT7622_PIN(77, "GPIO_D"),
  187. MT7622_PIN(78, "WATCHDOG"),
  188. MT7622_PIN(79, "RTS3_N"),
  189. MT7622_PIN(80, "CTS3_N"),
  190. MT7622_PIN(81, "TXD3"),
  191. MT7622_PIN(82, "RXD3"),
  192. MT7622_PIN(83, "PERST0_N"),
  193. MT7622_PIN(84, "PERST1_N"),
  194. MT7622_PIN(85, "WLED_N"),
  195. MT7622_PIN(86, "EPHY_LED0_N"),
  196. MT7622_PIN(87, "AUXIN0"),
  197. MT7622_PIN(88, "AUXIN1"),
  198. MT7622_PIN(89, "AUXIN2"),
  199. MT7622_PIN(90, "AUXIN3"),
  200. MT7622_PIN(91, "TXD4"),
  201. MT7622_PIN(92, "RXD4"),
  202. MT7622_PIN(93, "RTS4_N"),
  203. MT7622_PIN(94, "CTS4_N"),
  204. MT7622_PIN(95, "PWM1"),
  205. MT7622_PIN(96, "PWM2"),
  206. MT7622_PIN(97, "PWM3"),
  207. MT7622_PIN(98, "PWM4"),
  208. MT7622_PIN(99, "PWM5"),
  209. MT7622_PIN(100, "PWM6"),
  210. MT7622_PIN(101, "PWM7"),
  211. MT7622_PIN(102, "GPIO_E"),
  212. };
  213. /* List all groups consisting of these pins dedicated to the enablement of
  214. * certain hardware block and the corresponding mode for all of the pins. The
  215. * hardware probably has multiple combinations of these pinouts.
  216. */
  217. /* EMMC */
  218. static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
  219. static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
  220. static int mt7622_emmc_rst_pins[] = { 37, };
  221. static int mt7622_emmc_rst_funcs[] = { 1, };
  222. /* LED for EPHY */
  223. static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
  224. static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
  225. static int mt7622_ephy0_led_pins[] = { 86, };
  226. static int mt7622_ephy0_led_funcs[] = { 0, };
  227. static int mt7622_ephy1_led_pins[] = { 91, };
  228. static int mt7622_ephy1_led_funcs[] = { 2, };
  229. static int mt7622_ephy2_led_pins[] = { 92, };
  230. static int mt7622_ephy2_led_funcs[] = { 2, };
  231. static int mt7622_ephy3_led_pins[] = { 93, };
  232. static int mt7622_ephy3_led_funcs[] = { 2, };
  233. static int mt7622_ephy4_led_pins[] = { 94, };
  234. static int mt7622_ephy4_led_funcs[] = { 2, };
  235. /* Embedded Switch */
  236. static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
  237. 62, 63, 64, 65, 66, 67, 68, 69, 70, };
  238. static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  239. 0, 0, 0, 0, 0, 0, 0, 0, 0, };
  240. static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
  241. static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
  242. static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
  243. 68, 69, 70, };
  244. static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
  245. 0, 0, 0, };
  246. /* RGMII via ESW */
  247. static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
  248. 67, 68, 69, 70, };
  249. static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  250. 0, };
  251. /* RGMII via GMAC1 */
  252. static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
  253. 67, 68, 69, 70, };
  254. static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
  255. 2, };
  256. /* RGMII via GMAC2 */
  257. static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
  258. 33, 34, 35, 36, };
  259. static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  260. 0, };
  261. /* I2C */
  262. static int mt7622_i2c0_pins[] = { 14, 15, };
  263. static int mt7622_i2c0_funcs[] = { 0, 0, };
  264. static int mt7622_i2c1_0_pins[] = { 55, 56, };
  265. static int mt7622_i2c1_0_funcs[] = { 0, 0, };
  266. static int mt7622_i2c1_1_pins[] = { 73, 74, };
  267. static int mt7622_i2c1_1_funcs[] = { 3, 3, };
  268. static int mt7622_i2c1_2_pins[] = { 87, 88, };
  269. static int mt7622_i2c1_2_funcs[] = { 0, 0, };
  270. static int mt7622_i2c2_0_pins[] = { 57, 58, };
  271. static int mt7622_i2c2_0_funcs[] = { 0, 0, };
  272. static int mt7622_i2c2_1_pins[] = { 75, 76, };
  273. static int mt7622_i2c2_1_funcs[] = { 3, 3, };
  274. static int mt7622_i2c2_2_pins[] = { 89, 90, };
  275. static int mt7622_i2c2_2_funcs[] = { 0, 0, };
  276. /* I2S */
  277. static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
  278. static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
  279. static int mt7622_i2s1_in_data_pins[] = { 1, };
  280. static int mt7622_i2s1_in_data_funcs[] = { 0, };
  281. static int mt7622_i2s2_in_data_pins[] = { 16, };
  282. static int mt7622_i2s2_in_data_funcs[] = { 0, };
  283. static int mt7622_i2s3_in_data_pins[] = { 17, };
  284. static int mt7622_i2s3_in_data_funcs[] = { 0, };
  285. static int mt7622_i2s4_in_data_pins[] = { 18, };
  286. static int mt7622_i2s4_in_data_funcs[] = { 0, };
  287. static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
  288. static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
  289. static int mt7622_i2s1_out_data_pins[] = { 2, };
  290. static int mt7622_i2s1_out_data_funcs[] = { 0, };
  291. static int mt7622_i2s2_out_data_pins[] = { 19, };
  292. static int mt7622_i2s2_out_data_funcs[] = { 0, };
  293. static int mt7622_i2s3_out_data_pins[] = { 20, };
  294. static int mt7622_i2s3_out_data_funcs[] = { 0, };
  295. static int mt7622_i2s4_out_data_pins[] = { 21, };
  296. static int mt7622_i2s4_out_data_funcs[] = { 0, };
  297. /* IR */
  298. static int mt7622_ir_0_tx_pins[] = { 16, };
  299. static int mt7622_ir_0_tx_funcs[] = { 4, };
  300. static int mt7622_ir_1_tx_pins[] = { 59, };
  301. static int mt7622_ir_1_tx_funcs[] = { 5, };
  302. static int mt7622_ir_2_tx_pins[] = { 99, };
  303. static int mt7622_ir_2_tx_funcs[] = { 3, };
  304. static int mt7622_ir_0_rx_pins[] = { 17, };
  305. static int mt7622_ir_0_rx_funcs[] = { 4, };
  306. static int mt7622_ir_1_rx_pins[] = { 60, };
  307. static int mt7622_ir_1_rx_funcs[] = { 5, };
  308. static int mt7622_ir_2_rx_pins[] = { 100, };
  309. static int mt7622_ir_2_rx_funcs[] = { 3, };
  310. /* MDIO */
  311. static int mt7622_mdc_mdio_pins[] = { 23, 24, };
  312. static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
  313. /* PCIE */
  314. static int mt7622_pcie0_0_waken_pins[] = { 14, };
  315. static int mt7622_pcie0_0_waken_funcs[] = { 2, };
  316. static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
  317. static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
  318. static int mt7622_pcie0_1_waken_pins[] = { 79, };
  319. static int mt7622_pcie0_1_waken_funcs[] = { 4, };
  320. static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
  321. static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
  322. static int mt7622_pcie1_0_waken_pins[] = { 14, };
  323. static int mt7622_pcie1_0_waken_funcs[] = { 3, };
  324. static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
  325. static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
  326. static int mt7622_pcie0_pad_perst_pins[] = { 83, };
  327. static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
  328. static int mt7622_pcie1_pad_perst_pins[] = { 84, };
  329. static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
  330. /* PMIC bus */
  331. static int mt7622_pmic_bus_pins[] = { 71, 72, };
  332. static int mt7622_pmic_bus_funcs[] = { 0, 0, };
  333. /* Parallel NAND */
  334. static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
  335. 48, 49, 50, };
  336. static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  337. 0, };
  338. /* PWM */
  339. static int mt7622_pwm_ch1_0_pins[] = { 51, };
  340. static int mt7622_pwm_ch1_0_funcs[] = { 3, };
  341. static int mt7622_pwm_ch1_1_pins[] = { 73, };
  342. static int mt7622_pwm_ch1_1_funcs[] = { 4, };
  343. static int mt7622_pwm_ch1_2_pins[] = { 95, };
  344. static int mt7622_pwm_ch1_2_funcs[] = { 0, };
  345. static int mt7622_pwm_ch2_0_pins[] = { 52, };
  346. static int mt7622_pwm_ch2_0_funcs[] = { 3, };
  347. static int mt7622_pwm_ch2_1_pins[] = { 74, };
  348. static int mt7622_pwm_ch2_1_funcs[] = { 4, };
  349. static int mt7622_pwm_ch2_2_pins[] = { 96, };
  350. static int mt7622_pwm_ch2_2_funcs[] = { 0, };
  351. static int mt7622_pwm_ch3_0_pins[] = { 53, };
  352. static int mt7622_pwm_ch3_0_funcs[] = { 3, };
  353. static int mt7622_pwm_ch3_1_pins[] = { 75, };
  354. static int mt7622_pwm_ch3_1_funcs[] = { 4, };
  355. static int mt7622_pwm_ch3_2_pins[] = { 97, };
  356. static int mt7622_pwm_ch3_2_funcs[] = { 0, };
  357. static int mt7622_pwm_ch4_0_pins[] = { 54, };
  358. static int mt7622_pwm_ch4_0_funcs[] = { 3, };
  359. static int mt7622_pwm_ch4_1_pins[] = { 67, };
  360. static int mt7622_pwm_ch4_1_funcs[] = { 3, };
  361. static int mt7622_pwm_ch4_2_pins[] = { 76, };
  362. static int mt7622_pwm_ch4_2_funcs[] = { 4, };
  363. static int mt7622_pwm_ch4_3_pins[] = { 98, };
  364. static int mt7622_pwm_ch4_3_funcs[] = { 0, };
  365. static int mt7622_pwm_ch5_0_pins[] = { 68, };
  366. static int mt7622_pwm_ch5_0_funcs[] = { 3, };
  367. static int mt7622_pwm_ch5_1_pins[] = { 77, };
  368. static int mt7622_pwm_ch5_1_funcs[] = { 4, };
  369. static int mt7622_pwm_ch5_2_pins[] = { 99, };
  370. static int mt7622_pwm_ch5_2_funcs[] = { 0, };
  371. static int mt7622_pwm_ch6_0_pins[] = { 69, };
  372. static int mt7622_pwm_ch6_0_funcs[] = { 3, };
  373. static int mt7622_pwm_ch6_1_pins[] = { 78, };
  374. static int mt7622_pwm_ch6_1_funcs[] = { 4, };
  375. static int mt7622_pwm_ch6_2_pins[] = { 81, };
  376. static int mt7622_pwm_ch6_2_funcs[] = { 4, };
  377. static int mt7622_pwm_ch6_3_pins[] = { 100, };
  378. static int mt7622_pwm_ch6_3_funcs[] = { 0, };
  379. static int mt7622_pwm_ch7_0_pins[] = { 70, };
  380. static int mt7622_pwm_ch7_0_funcs[] = { 3, };
  381. static int mt7622_pwm_ch7_1_pins[] = { 82, };
  382. static int mt7622_pwm_ch7_1_funcs[] = { 4, };
  383. static int mt7622_pwm_ch7_2_pins[] = { 101, };
  384. static int mt7622_pwm_ch7_2_funcs[] = { 0, };
  385. /* SD */
  386. static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
  387. static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
  388. static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
  389. static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
  390. /* Serial NAND */
  391. static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
  392. static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
  393. /* SPI NOR */
  394. static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
  395. static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
  396. /* SPIC */
  397. static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
  398. static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
  399. static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
  400. static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
  401. static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
  402. static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
  403. static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
  404. static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
  405. static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
  406. static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
  407. static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
  408. static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
  409. /* TDM */
  410. static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
  411. static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
  412. static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
  413. static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
  414. static int mt7622_tdm_0_out_data_pins[] = { 20, };
  415. static int mt7622_tdm_0_out_data_funcs[] = { 3, };
  416. static int mt7622_tdm_0_in_data_pins[] = { 21, };
  417. static int mt7622_tdm_0_in_data_funcs[] = { 3, };
  418. static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
  419. static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
  420. static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
  421. static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
  422. static int mt7622_tdm_1_out_data_pins[] = { 55, };
  423. static int mt7622_tdm_1_out_data_funcs[] = { 3, };
  424. static int mt7622_tdm_1_in_data_pins[] = { 56, };
  425. static int mt7622_tdm_1_in_data_funcs[] = { 3, };
  426. /* UART */
  427. static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
  428. static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
  429. static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
  430. static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
  431. static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
  432. static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
  433. static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
  434. static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
  435. static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
  436. static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
  437. static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
  438. static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
  439. static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
  440. static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
  441. static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
  442. static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
  443. static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
  444. static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
  445. static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
  446. static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
  447. static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
  448. static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
  449. static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
  450. static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
  451. static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
  452. static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
  453. static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
  454. static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
  455. static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
  456. static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
  457. static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
  458. static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
  459. static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
  460. static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
  461. static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
  462. static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
  463. static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
  464. static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
  465. static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
  466. static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
  467. /* Watchdog */
  468. static int mt7622_watchdog_pins[] = { 78, };
  469. static int mt7622_watchdog_funcs[] = { 0, };
  470. /* WLAN LED */
  471. static int mt7622_wled_pins[] = { 85, };
  472. static int mt7622_wled_funcs[] = { 0, };
  473. static const struct mtk_group_desc mt7622_groups[] = {
  474. PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
  475. PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
  476. PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
  477. PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led),
  478. PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led),
  479. PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led),
  480. PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led),
  481. PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led),
  482. PINCTRL_PIN_GROUP("esw", mt7622_esw),
  483. PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1),
  484. PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4),
  485. PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw),
  486. PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1),
  487. PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2),
  488. PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0),
  489. PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0),
  490. PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1),
  491. PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2),
  492. PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0),
  493. PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1),
  494. PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2),
  495. PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws),
  496. PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws),
  497. PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data),
  498. PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data),
  499. PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data),
  500. PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data),
  501. PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data),
  502. PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data),
  503. PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data),
  504. PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data),
  505. PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx),
  506. PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx),
  507. PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx),
  508. PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx),
  509. PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx),
  510. PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx),
  511. PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio),
  512. PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken),
  513. PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq),
  514. PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken),
  515. PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq),
  516. PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken),
  517. PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq),
  518. PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst),
  519. PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst),
  520. PINCTRL_PIN_GROUP("par_nand", mt7622_pnand),
  521. PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus),
  522. PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0),
  523. PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1),
  524. PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2),
  525. PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0),
  526. PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1),
  527. PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2),
  528. PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0),
  529. PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1),
  530. PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2),
  531. PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0),
  532. PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1),
  533. PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2),
  534. PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3),
  535. PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0),
  536. PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1),
  537. PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2),
  538. PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0),
  539. PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1),
  540. PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2),
  541. PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3),
  542. PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0),
  543. PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1),
  544. PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2),
  545. PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0),
  546. PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1),
  547. PINCTRL_PIN_GROUP("snfi", mt7622_snfi),
  548. PINCTRL_PIN_GROUP("spi_nor", mt7622_spi),
  549. PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0),
  550. PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1),
  551. PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0),
  552. PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1),
  553. PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0),
  554. PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold),
  555. PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws",
  556. mt7622_tdm_0_out_mclk_bclk_ws),
  557. PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws",
  558. mt7622_tdm_0_in_mclk_bclk_ws),
  559. PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data),
  560. PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data),
  561. PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws",
  562. mt7622_tdm_1_out_mclk_bclk_ws),
  563. PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws",
  564. mt7622_tdm_1_in_mclk_bclk_ws),
  565. PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data),
  566. PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data),
  567. PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx),
  568. PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx),
  569. PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts),
  570. PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx),
  571. PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts),
  572. PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx),
  573. PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts),
  574. PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx),
  575. PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts),
  576. PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx),
  577. PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts),
  578. PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx),
  579. PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx),
  580. PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx),
  581. PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts),
  582. PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx),
  583. PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx),
  584. PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts),
  585. PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx),
  586. PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts),
  587. PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog),
  588. PINCTRL_PIN_GROUP("wled", mt7622_wled),
  589. };
  590. /* Joint those groups owning the same capability in user point of view which
  591. * allows that people tend to use through the device tree.
  592. */
  593. static const char *const mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
  594. static const char *const mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
  595. "esw_p2_p3_p4", "mdc_mdio",
  596. "rgmii_via_gmac1",
  597. "rgmii_via_gmac2",
  598. "rgmii_via_esw", };
  599. static const char *const mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
  600. "i2c1_2", "i2c2_0", "i2c2_1",
  601. "i2c2_2", };
  602. static const char *const mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws",
  603. "i2s_in_mclk_bclk_ws",
  604. "i2s1_in_data", "i2s2_in_data",
  605. "i2s3_in_data", "i2s4_in_data",
  606. "i2s1_out_data", "i2s2_out_data",
  607. "i2s3_out_data", "i2s4_out_data", };
  608. static const char *const mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx",
  609. "ir_0_rx", "ir_1_rx", "ir_2_rx"};
  610. static const char *const mt7622_led_groups[] = { "ephy_leds", "ephy0_led",
  611. "ephy1_led", "ephy2_led",
  612. "ephy3_led", "ephy4_led",
  613. "wled", };
  614. static const char *const mt7622_flash_groups[] = { "par_nand", "snfi",
  615. "spi_nor"};
  616. static const char *const mt7622_pcie_groups[] = { "pcie0_0_waken",
  617. "pcie0_0_clkreq", "pcie0_1_waken",
  618. "pcie0_1_clkreq", "pcie1_0_waken",
  619. "pcie1_0_clkreq", "pcie0_pad_perst",
  620. "pcie1_pad_perst", };
  621. static const char *const mt7622_pmic_bus_groups[] = { "pmic_bus", };
  622. static const char *const mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
  623. "pwm_ch1_2", "pwm_ch2_0",
  624. "pwm_ch2_1", "pwm_ch2_2",
  625. "pwm_ch3_0", "pwm_ch3_1",
  626. "pwm_ch3_2", "pwm_ch4_0",
  627. "pwm_ch4_1", "pwm_ch4_2",
  628. "pwm_ch4_3", "pwm_ch5_0",
  629. "pwm_ch5_1", "pwm_ch5_2",
  630. "pwm_ch6_0", "pwm_ch6_1",
  631. "pwm_ch6_2", "pwm_ch6_3",
  632. "pwm_ch7_0", "pwm_ch7_1",
  633. "pwm_ch7_2", };
  634. static const char *const mt7622_sd_groups[] = { "sd_0", "sd_1", };
  635. static const char *const mt7622_spic_groups[] = { "spic0_0", "spic0_1",
  636. "spic1_0", "spic1_1", "spic2_0",
  637. "spic2_0_wp_hold", };
  638. static const char *const mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws",
  639. "tdm_0_in_mclk_bclk_ws",
  640. "tdm_0_out_data",
  641. "tdm_0_in_data",
  642. "tdm_1_out_mclk_bclk_ws",
  643. "tdm_1_in_mclk_bclk_ws",
  644. "tdm_1_out_data",
  645. "tdm_1_in_data", };
  646. static const char *const mt7622_uart_groups[] = { "uart0_0_tx_rx",
  647. "uart1_0_tx_rx", "uart1_0_rts_cts",
  648. "uart1_1_tx_rx", "uart1_1_rts_cts",
  649. "uart2_0_tx_rx", "uart2_0_rts_cts",
  650. "uart2_1_tx_rx", "uart2_1_rts_cts",
  651. "uart2_2_tx_rx", "uart2_2_rts_cts",
  652. "uart2_3_tx_rx",
  653. "uart3_0_tx_rx",
  654. "uart3_1_tx_rx", "uart3_1_rts_cts",
  655. "uart4_0_tx_rx",
  656. "uart4_1_tx_rx", "uart4_1_rts_cts",
  657. "uart4_2_tx_rx",
  658. "uart4_2_rts_cts",};
  659. static const char *const mt7622_wdt_groups[] = { "watchdog", };
  660. static const struct mtk_function_desc mt7622_functions[] = {
  661. {"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
  662. {"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
  663. {"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
  664. {"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)},
  665. {"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)},
  666. {"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)},
  667. {"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)},
  668. {"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)},
  669. {"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)},
  670. {"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)},
  671. {"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)},
  672. {"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)},
  673. {"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)},
  674. {"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)},
  675. {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
  676. };
  677. static struct mtk_pinctrl_soc mt7622_data = {
  678. .name = "mt7622_pinctrl",
  679. .reg_cal = mt7622_reg_cals,
  680. .pins = mt7622_pins,
  681. .npins = ARRAY_SIZE(mt7622_pins),
  682. .grps = mt7622_groups,
  683. .ngrps = ARRAY_SIZE(mt7622_groups),
  684. .funcs = mt7622_functions,
  685. .nfuncs = ARRAY_SIZE(mt7622_functions),
  686. .gpio_mode = 1,
  687. .rev = MTK_PINCTRL_V0,
  688. };
  689. static int mtk_pinctrl_mt7622_probe(struct udevice *dev)
  690. {
  691. return mtk_pinctrl_common_probe(dev, &mt7622_data);
  692. }
  693. static const struct udevice_id mt7622_pctrl_match[] = {
  694. { .compatible = "mediatek,mt7622-pinctrl" },
  695. { /* sentinel */ }
  696. };
  697. U_BOOT_DRIVER(mt7622_pinctrl) = {
  698. .name = "mt7622_pinctrl",
  699. .id = UCLASS_PINCTRL,
  700. .of_match = mt7622_pctrl_match,
  701. .ops = &mtk_pinctrl_ops,
  702. .probe = mtk_pinctrl_mt7622_probe,
  703. .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
  704. };