ti-pipe3-phy.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
  4. * Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <dm/device.h>
  9. #include <generic-phy.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <syscon.h>
  13. #include <regmap.h>
  14. #include <linux/bitops.h>
  15. #include <linux/delay.h>
  16. #include <linux/err.h>
  17. /* PLLCTRL Registers */
  18. #define PLL_STATUS 0x00000004
  19. #define PLL_GO 0x00000008
  20. #define PLL_CONFIGURATION1 0x0000000C
  21. #define PLL_CONFIGURATION2 0x00000010
  22. #define PLL_CONFIGURATION3 0x00000014
  23. #define PLL_CONFIGURATION4 0x00000020
  24. #define PLL_REGM_MASK 0x001FFE00
  25. #define PLL_REGM_SHIFT 9
  26. #define PLL_REGM_F_MASK 0x0003FFFF
  27. #define PLL_REGM_F_SHIFT 0
  28. #define PLL_REGN_MASK 0x000001FE
  29. #define PLL_REGN_SHIFT 1
  30. #define PLL_SELFREQDCO_MASK 0x0000000E
  31. #define PLL_SELFREQDCO_SHIFT 1
  32. #define PLL_SD_MASK 0x0003FC00
  33. #define PLL_SD_SHIFT 10
  34. #define SET_PLL_GO 0x1
  35. #define PLL_TICOPWDN BIT(16)
  36. #define PLL_LDOPWDN BIT(15)
  37. #define PLL_LOCK 0x2
  38. #define PLL_IDLE 0x1
  39. /* Software rest for the SATA PLL (in CTRL_CORE_SMA_SW_0 register)*/
  40. #define SATA_PLL_SOFT_RESET (1<<18)
  41. /* PHY POWER CONTROL Register */
  42. #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14)
  43. #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
  44. #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22)
  45. #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
  46. #define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
  47. #define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
  48. /* PHY RX Registers */
  49. #define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C
  50. #define INTERFACE_MASK GENMASK(31, 27)
  51. #define INTERFACE_SHIFT 27
  52. #define INTERFACE_MODE_USBSS BIT(4)
  53. #define INTERFACE_MODE_SATA_1P5 BIT(3)
  54. #define INTERFACE_MODE_SATA_3P0 BIT(2)
  55. #define INTERFACE_MODE_PCIE BIT(0)
  56. #define LOSD_MASK GENMASK(17, 14)
  57. #define LOSD_SHIFT 14
  58. #define MEM_PLLDIV GENMASK(6, 5)
  59. #define PIPE3_PHY_RX_TRIM 0x0000001C
  60. #define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)
  61. #define MEM_DLL_TRIM_SHIFT 30
  62. #define PIPE3_PHY_RX_DLL 0x00000024
  63. #define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)
  64. #define MEM_DLL_PHINT_RATE_SHIFT 30
  65. #define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028
  66. #define MEM_HS_RATE_MASK GENMASK(28, 27)
  67. #define MEM_HS_RATE_SHIFT 27
  68. #define MEM_OVRD_HS_RATE BIT(26)
  69. #define MEM_OVRD_HS_RATE_SHIFT 26
  70. #define MEM_CDR_FASTLOCK BIT(23)
  71. #define MEM_CDR_FASTLOCK_SHIFT 23
  72. #define MEM_CDR_LBW_MASK GENMASK(22, 21)
  73. #define MEM_CDR_LBW_SHIFT 21
  74. #define MEM_CDR_STEPCNT_MASK GENMASK(20, 19)
  75. #define MEM_CDR_STEPCNT_SHIFT 19
  76. #define MEM_CDR_STL_MASK GENMASK(18, 16)
  77. #define MEM_CDR_STL_SHIFT 16
  78. #define MEM_CDR_THR_MASK GENMASK(15, 13)
  79. #define MEM_CDR_THR_SHIFT 13
  80. #define MEM_CDR_THR_MODE BIT(12)
  81. #define MEM_CDR_THR_MODE_SHIFT 12
  82. #define MEM_CDR_2NDO_SDM_MODE BIT(11)
  83. #define MEM_CDR_2NDO_SDM_MODE_SHIFT 11
  84. #define PIPE3_PHY_RX_EQUALIZER 0x00000038
  85. #define MEM_EQLEV_MASK GENMASK(31, 16)
  86. #define MEM_EQLEV_SHIFT 16
  87. #define MEM_EQFTC_MASK GENMASK(15, 11)
  88. #define MEM_EQFTC_SHIFT 11
  89. #define MEM_EQCTL_MASK GENMASK(10, 7)
  90. #define MEM_EQCTL_SHIFT 7
  91. #define MEM_OVRD_EQLEV BIT(2)
  92. #define MEM_OVRD_EQLEV_SHIFT 2
  93. #define MEM_OVRD_EQFTC BIT(1)
  94. #define MEM_OVRD_EQFTC_SHIFT 1
  95. #define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44
  96. #define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9)
  97. #define MEM_CDR_LOS_SOURCE_SHIFT 9
  98. #define PLL_IDLE_TIME 100 /* in milliseconds */
  99. #define PLL_LOCK_TIME 100 /* in milliseconds */
  100. enum pipe3_mode { PIPE3_MODE_PCIE = 1,
  101. PIPE3_MODE_SATA,
  102. PIPE3_MODE_USBSS };
  103. struct pipe3_settings {
  104. u8 ana_interface;
  105. u8 ana_losd;
  106. u8 dig_fastlock;
  107. u8 dig_lbw;
  108. u8 dig_stepcnt;
  109. u8 dig_stl;
  110. u8 dig_thr;
  111. u8 dig_thr_mode;
  112. u8 dig_2ndo_sdm_mode;
  113. u8 dig_hs_rate;
  114. u8 dig_ovrd_hs_rate;
  115. u8 dll_trim_sel;
  116. u8 dll_phint_rate;
  117. u8 eq_lev;
  118. u8 eq_ftc;
  119. u8 eq_ctl;
  120. u8 eq_ovrd_lev;
  121. u8 eq_ovrd_ftc;
  122. };
  123. struct omap_pipe3 {
  124. void __iomem *pll_ctrl_base;
  125. void __iomem *phy_rx;
  126. void __iomem *power_reg;
  127. void __iomem *pll_reset_reg;
  128. struct pipe3_dpll_map *dpll_map;
  129. enum pipe3_mode mode;
  130. struct pipe3_settings settings;
  131. };
  132. struct pipe3_dpll_params {
  133. u16 m;
  134. u8 n;
  135. u8 freq:3;
  136. u8 sd;
  137. u32 mf;
  138. };
  139. struct pipe3_dpll_map {
  140. unsigned long rate;
  141. struct pipe3_dpll_params params;
  142. };
  143. struct pipe3_data {
  144. enum pipe3_mode mode;
  145. struct pipe3_dpll_map *dpll_map;
  146. struct pipe3_settings settings;
  147. };
  148. static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
  149. {
  150. return readl(addr + offset);
  151. }
  152. static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
  153. u32 data)
  154. {
  155. writel(data, addr + offset);
  156. }
  157. static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
  158. *pipe3)
  159. {
  160. u32 rate;
  161. struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
  162. rate = get_sys_clk_freq();
  163. for (; dpll_map->rate; dpll_map++) {
  164. if (rate == dpll_map->rate)
  165. return &dpll_map->params;
  166. }
  167. printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
  168. __func__, rate);
  169. return NULL;
  170. }
  171. static int omap_pipe3_wait_lock(struct omap_pipe3 *pipe3)
  172. {
  173. u32 val;
  174. int timeout = PLL_LOCK_TIME;
  175. do {
  176. mdelay(1);
  177. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
  178. if (val & PLL_LOCK)
  179. break;
  180. } while (--timeout);
  181. if (!(val & PLL_LOCK)) {
  182. printf("%s: DPLL failed to lock\n", __func__);
  183. return -EBUSY;
  184. }
  185. return 0;
  186. }
  187. static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3)
  188. {
  189. u32 val;
  190. struct pipe3_dpll_params *dpll_params;
  191. dpll_params = omap_pipe3_get_dpll_params(pipe3);
  192. if (!dpll_params) {
  193. printf("%s: Invalid DPLL parameters\n", __func__);
  194. return -EINVAL;
  195. }
  196. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
  197. val &= ~PLL_REGN_MASK;
  198. val |= dpll_params->n << PLL_REGN_SHIFT;
  199. omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
  200. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
  201. val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);
  202. val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
  203. omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
  204. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
  205. val &= ~PLL_REGM_MASK;
  206. val |= dpll_params->m << PLL_REGM_SHIFT;
  207. omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
  208. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4);
  209. val &= ~PLL_REGM_F_MASK;
  210. val |= dpll_params->mf << PLL_REGM_F_SHIFT;
  211. omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION4, val);
  212. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION3);
  213. val &= ~PLL_SD_MASK;
  214. val |= dpll_params->sd << PLL_SD_SHIFT;
  215. omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION3, val);
  216. omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_GO, SET_PLL_GO);
  217. return omap_pipe3_wait_lock(pipe3);
  218. }
  219. static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on)
  220. {
  221. u32 val, rate;
  222. val = readl(pipe3->power_reg);
  223. rate = get_sys_clk_freq();
  224. rate = rate/1000000;
  225. if (on) {
  226. val &= ~(PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
  227. PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
  228. val |= rate << PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
  229. writel(val, pipe3->power_reg);
  230. /* Power up TX before RX for SATA & USB */
  231. val |= PIPE3_PHY_TX_POWERON;
  232. writel(val, pipe3->power_reg);
  233. val |= PIPE3_PHY_RX_POWERON;
  234. writel(val, pipe3->power_reg);
  235. } else {
  236. val &= ~PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
  237. writel(val, pipe3->power_reg);
  238. }
  239. }
  240. static void ti_pipe3_calibrate(struct omap_pipe3 *phy)
  241. {
  242. u32 val;
  243. struct pipe3_settings *s = &phy->settings;
  244. val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
  245. val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
  246. val = (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
  247. omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
  248. val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
  249. val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
  250. MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
  251. MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
  252. val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
  253. s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
  254. s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
  255. s->dig_lbw << MEM_CDR_LBW_SHIFT |
  256. s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
  257. s->dig_stl << MEM_CDR_STL_SHIFT |
  258. s->dig_thr << MEM_CDR_THR_SHIFT |
  259. s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
  260. s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
  261. omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
  262. val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
  263. val &= ~MEM_DLL_TRIM_SEL_MASK;
  264. val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
  265. omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
  266. val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
  267. val &= ~MEM_DLL_PHINT_RATE_MASK;
  268. val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
  269. omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
  270. val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
  271. val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
  272. MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
  273. val |= s->eq_lev << MEM_EQLEV_SHIFT |
  274. s->eq_ftc << MEM_EQFTC_SHIFT |
  275. s->eq_ctl << MEM_EQCTL_SHIFT |
  276. s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
  277. s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
  278. omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
  279. if (phy->mode == PIPE3_MODE_SATA) {
  280. val = omap_pipe3_readl(phy->phy_rx,
  281. SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
  282. val &= ~MEM_CDR_LOS_SOURCE_MASK;
  283. omap_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
  284. val);
  285. }
  286. }
  287. static int pipe3_init(struct phy *phy)
  288. {
  289. int ret;
  290. u32 val;
  291. struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
  292. /* Program the DPLL only if not locked */
  293. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
  294. if (!(val & PLL_LOCK)) {
  295. ret = omap_pipe3_dpll_program(pipe3);
  296. if (ret)
  297. return ret;
  298. ti_pipe3_calibrate(pipe3);
  299. } else {
  300. /* else just bring it out of IDLE mode */
  301. val = omap_pipe3_readl(pipe3->pll_ctrl_base,
  302. PLL_CONFIGURATION2);
  303. if (val & PLL_IDLE) {
  304. val &= ~PLL_IDLE;
  305. omap_pipe3_writel(pipe3->pll_ctrl_base,
  306. PLL_CONFIGURATION2, val);
  307. ret = omap_pipe3_wait_lock(pipe3);
  308. if (ret)
  309. return ret;
  310. }
  311. }
  312. return 0;
  313. }
  314. static int pipe3_power_on(struct phy *phy)
  315. {
  316. struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
  317. /* Power up the PHY */
  318. omap_control_pipe3_power(pipe3, 1);
  319. return 0;
  320. }
  321. static int pipe3_power_off(struct phy *phy)
  322. {
  323. struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
  324. /* Power down the PHY */
  325. omap_control_pipe3_power(pipe3, 0);
  326. return 0;
  327. }
  328. static int pipe3_exit(struct phy *phy)
  329. {
  330. u32 val;
  331. int timeout = PLL_IDLE_TIME;
  332. struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
  333. pipe3_power_off(phy);
  334. /* Put DPLL in IDLE mode */
  335. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
  336. val |= PLL_IDLE;
  337. omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
  338. /* wait for LDO and Oscillator to power down */
  339. do {
  340. mdelay(1);
  341. val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
  342. if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
  343. break;
  344. } while (--timeout);
  345. if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
  346. pr_err("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
  347. __func__, val);
  348. return -EBUSY;
  349. }
  350. if (pipe3->pll_reset_reg) {
  351. val = readl(pipe3->pll_reset_reg);
  352. writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
  353. mdelay(1);
  354. writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
  355. }
  356. return 0;
  357. }
  358. static void *get_reg(struct udevice *dev, const char *name)
  359. {
  360. struct udevice *syscon;
  361. struct regmap *regmap;
  362. const fdt32_t *cell;
  363. int len, err;
  364. void *base;
  365. err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
  366. name, &syscon);
  367. if (err) {
  368. pr_err("unable to find syscon device for %s (%d)\n",
  369. name, err);
  370. return NULL;
  371. }
  372. regmap = syscon_get_regmap(syscon);
  373. if (IS_ERR(regmap)) {
  374. pr_err("unable to find regmap for %s (%ld)\n",
  375. name, PTR_ERR(regmap));
  376. return NULL;
  377. }
  378. cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), name,
  379. &len);
  380. if (len < 2*sizeof(fdt32_t)) {
  381. pr_err("offset not available for %s\n", name);
  382. return NULL;
  383. }
  384. base = regmap_get_range(regmap, 0);
  385. if (!base)
  386. return NULL;
  387. return fdtdec_get_number(cell + 1, 1) + base;
  388. }
  389. static int pipe3_phy_probe(struct udevice *dev)
  390. {
  391. fdt_addr_t addr;
  392. fdt_size_t sz;
  393. struct omap_pipe3 *pipe3 = dev_get_priv(dev);
  394. struct pipe3_data *data;
  395. /* PHY_RX */
  396. addr = devfdt_get_addr_size_index(dev, 0, &sz);
  397. if (addr == FDT_ADDR_T_NONE) {
  398. pr_err("missing phy_rx address\n");
  399. return -EINVAL;
  400. }
  401. pipe3->phy_rx = map_physmem(addr, sz, MAP_NOCACHE);
  402. if (!pipe3->phy_rx) {
  403. pr_err("unable to remap phy_rx\n");
  404. return -EINVAL;
  405. }
  406. /* PLLCTRL */
  407. addr = devfdt_get_addr_size_index(dev, 2, &sz);
  408. if (addr == FDT_ADDR_T_NONE) {
  409. pr_err("missing pll ctrl address\n");
  410. return -EINVAL;
  411. }
  412. pipe3->pll_ctrl_base = map_physmem(addr, sz, MAP_NOCACHE);
  413. if (!pipe3->pll_ctrl_base) {
  414. pr_err("unable to remap pll ctrl\n");
  415. return -EINVAL;
  416. }
  417. pipe3->power_reg = get_reg(dev, "syscon-phy-power");
  418. if (!pipe3->power_reg)
  419. return -EINVAL;
  420. data = (struct pipe3_data *)dev_get_driver_data(dev);
  421. pipe3->mode = data->mode;
  422. pipe3->dpll_map = data->dpll_map;
  423. pipe3->settings = data->settings;
  424. if (pipe3->mode == PIPE3_MODE_SATA) {
  425. pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
  426. if (!pipe3->pll_reset_reg)
  427. return -EINVAL;
  428. }
  429. return 0;
  430. }
  431. static struct pipe3_dpll_map dpll_map_sata[] = {
  432. {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
  433. {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
  434. {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
  435. {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
  436. {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
  437. {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
  438. { }, /* Terminator */
  439. };
  440. static struct pipe3_dpll_map dpll_map_usb[] = {
  441. {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
  442. {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
  443. {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
  444. {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
  445. {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
  446. {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
  447. { }, /* Terminator */
  448. };
  449. static struct pipe3_data data_usb = {
  450. .mode = PIPE3_MODE_USBSS,
  451. .dpll_map = dpll_map_usb,
  452. .settings = {
  453. /* DRA75x TRM Table 26-17. Preferred USB3_PHY_RX SCP Register Settings */
  454. .ana_interface = INTERFACE_MODE_USBSS,
  455. .ana_losd = 0xa,
  456. .dig_fastlock = 1,
  457. .dig_lbw = 3,
  458. .dig_stepcnt = 0,
  459. .dig_stl = 0x3,
  460. .dig_thr = 1,
  461. .dig_thr_mode = 1,
  462. .dig_2ndo_sdm_mode = 0,
  463. .dig_hs_rate = 0,
  464. .dig_ovrd_hs_rate = 1,
  465. .dll_trim_sel = 0x2,
  466. .dll_phint_rate = 0x3,
  467. .eq_lev = 0,
  468. .eq_ftc = 0,
  469. .eq_ctl = 0x9,
  470. .eq_ovrd_lev = 0,
  471. .eq_ovrd_ftc = 0,
  472. },
  473. };
  474. static struct pipe3_data data_sata = {
  475. .mode = PIPE3_MODE_SATA,
  476. .dpll_map = dpll_map_sata,
  477. .settings = {
  478. /* DRA75x TRM Table 26-9. Preferred SATA_PHY_RX SCP Register Settings */
  479. .ana_interface = INTERFACE_MODE_SATA_3P0,
  480. .ana_losd = 0x5,
  481. .dig_fastlock = 1,
  482. .dig_lbw = 3,
  483. .dig_stepcnt = 0,
  484. .dig_stl = 0x3,
  485. .dig_thr = 1,
  486. .dig_thr_mode = 1,
  487. .dig_2ndo_sdm_mode = 0,
  488. .dig_hs_rate = 0, /* Not in TRM preferred settings */
  489. .dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */
  490. .dll_trim_sel = 0x1,
  491. .dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */
  492. .eq_lev = 0,
  493. .eq_ftc = 0x1f,
  494. .eq_ctl = 0,
  495. .eq_ovrd_lev = 1,
  496. .eq_ovrd_ftc = 1,
  497. },
  498. };
  499. static const struct udevice_id pipe3_phy_ids[] = {
  500. { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&data_sata },
  501. { .compatible = "ti,omap-usb3", .data = (ulong)&data_usb},
  502. { }
  503. };
  504. static struct phy_ops pipe3_phy_ops = {
  505. .init = pipe3_init,
  506. .power_on = pipe3_power_on,
  507. .power_off = pipe3_power_off,
  508. .exit = pipe3_exit,
  509. };
  510. U_BOOT_DRIVER(pipe3_phy) = {
  511. .name = "pipe3_phy",
  512. .id = UCLASS_PHY,
  513. .of_match = pipe3_phy_ids,
  514. .ops = &pipe3_phy_ops,
  515. .probe = pipe3_phy_probe,
  516. .priv_auto_alloc_size = sizeof(struct omap_pipe3),
  517. };