meson-g12a-usb3-pcie.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Meson G12A USB3+PCIE Combo PHY driver
  4. *
  5. * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  6. * Copyright (C) 2019 BayLibre, SAS
  7. * Author: Neil Armstrong <narmstron@baylibre.com>
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <malloc.h>
  13. #include <regmap.h>
  14. #include <errno.h>
  15. #include <asm/io.h>
  16. #include <reset.h>
  17. #include <bitfield.h>
  18. #include <generic-phy.h>
  19. #include <linux/delay.h>
  20. #include <linux/bitops.h>
  21. #include <linux/compat.h>
  22. #include <linux/bitfield.h>
  23. #define PHY_R0 0x00
  24. #define PHY_R0_PCIE_POWER_STATE GENMASK(4, 0)
  25. #define PHY_R0_PCIE_USB3_SWITCH GENMASK(6, 5)
  26. #define PHY_R1 0x04
  27. #define PHY_R1_PHY_TX1_TERM_OFFSET GENMASK(4, 0)
  28. #define PHY_R1_PHY_TX0_TERM_OFFSET GENMASK(9, 5)
  29. #define PHY_R1_PHY_RX1_EQ GENMASK(12, 10)
  30. #define PHY_R1_PHY_RX0_EQ GENMASK(15, 13)
  31. #define PHY_R1_PHY_LOS_LEVEL GENMASK(20, 16)
  32. #define PHY_R1_PHY_LOS_BIAS GENMASK(23, 21)
  33. #define PHY_R1_PHY_REF_CLKDIV2 BIT(24)
  34. #define PHY_R1_PHY_MPLL_MULTIPLIER GENMASK(31, 25)
  35. #define PHY_R2 0x08
  36. #define PHY_R2_PCS_TX_DEEMPH_GEN2_6DB GENMASK(5, 0)
  37. #define PHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB GENMASK(11, 6)
  38. #define PHY_R2_PCS_TX_DEEMPH_GEN1 GENMASK(17, 12)
  39. #define PHY_R2_PHY_TX_VBOOST_LVL GENMASK(20, 18)
  40. #define PHY_R4 0x10
  41. #define PHY_R4_PHY_CR_WRITE BIT(0)
  42. #define PHY_R4_PHY_CR_READ BIT(1)
  43. #define PHY_R4_PHY_CR_DATA_IN GENMASK(17, 2)
  44. #define PHY_R4_PHY_CR_CAP_DATA BIT(18)
  45. #define PHY_R4_PHY_CR_CAP_ADDR BIT(19)
  46. #define PHY_R5 0x14
  47. #define PHY_R5_PHY_CR_DATA_OUT GENMASK(15, 0)
  48. #define PHY_R5_PHY_CR_ACK BIT(16)
  49. #define PHY_R5_PHY_BS_OUT BIT(17)
  50. struct phy_g12a_usb3_pcie_priv {
  51. struct regmap *regmap;
  52. #if CONFIG_IS_ENABLED(CLK)
  53. struct clk clk;
  54. #endif
  55. struct reset_ctl_bulk resets;
  56. };
  57. static int phy_g12a_usb3_pcie_cr_bus_addr(struct phy_g12a_usb3_pcie_priv *priv,
  58. unsigned int addr)
  59. {
  60. unsigned int val, reg;
  61. int ret;
  62. reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, addr);
  63. regmap_write(priv->regmap, PHY_R4, reg);
  64. regmap_write(priv->regmap, PHY_R4, reg);
  65. regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR);
  66. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  67. (val & PHY_R5_PHY_CR_ACK),
  68. 5, 1000);
  69. if (ret)
  70. return ret;
  71. regmap_write(priv->regmap, PHY_R4, reg);
  72. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  73. !(val & PHY_R5_PHY_CR_ACK),
  74. 5, 1000);
  75. if (ret)
  76. return ret;
  77. return 0;
  78. }
  79. static int
  80. phy_g12a_usb3_pcie_cr_bus_read(struct phy_g12a_usb3_pcie_priv *priv,
  81. unsigned int addr, unsigned int *data)
  82. {
  83. unsigned int val;
  84. int ret;
  85. ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
  86. if (ret)
  87. return ret;
  88. regmap_write(priv->regmap, PHY_R4, 0);
  89. regmap_write(priv->regmap, PHY_R4, PHY_R4_PHY_CR_READ);
  90. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  91. (val & PHY_R5_PHY_CR_ACK),
  92. 5, 1000);
  93. if (ret)
  94. return ret;
  95. *data = FIELD_GET(PHY_R5_PHY_CR_DATA_OUT, val);
  96. regmap_write(priv->regmap, PHY_R4, 0);
  97. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  98. !(val & PHY_R5_PHY_CR_ACK),
  99. 5, 1000);
  100. if (ret)
  101. return ret;
  102. return 0;
  103. }
  104. static int
  105. phy_g12a_usb3_pcie_cr_bus_write(struct phy_g12a_usb3_pcie_priv *priv,
  106. unsigned int addr, unsigned int data)
  107. {
  108. unsigned int val, reg;
  109. int ret;
  110. ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
  111. if (ret)
  112. return ret;
  113. reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, data);
  114. regmap_write(priv->regmap, PHY_R4, reg);
  115. regmap_write(priv->regmap, PHY_R4, reg);
  116. regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_DATA);
  117. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  118. (val & PHY_R5_PHY_CR_ACK),
  119. 5, 1000);
  120. if (ret)
  121. return ret;
  122. regmap_write(priv->regmap, PHY_R4, reg);
  123. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  124. (val & PHY_R5_PHY_CR_ACK) == 0,
  125. 5, 1000);
  126. if (ret)
  127. return ret;
  128. regmap_write(priv->regmap, PHY_R4, reg);
  129. regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_WRITE);
  130. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  131. (val & PHY_R5_PHY_CR_ACK),
  132. 5, 1000);
  133. if (ret)
  134. return ret;
  135. regmap_write(priv->regmap, PHY_R4, reg);
  136. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  137. (val & PHY_R5_PHY_CR_ACK) == 0,
  138. 5, 1000);
  139. if (ret)
  140. return ret;
  141. return 0;
  142. }
  143. static int
  144. phy_g12a_usb3_pcie_cr_bus_update_bits(struct phy_g12a_usb3_pcie_priv *priv,
  145. uint offset, uint mask, uint val)
  146. {
  147. uint reg;
  148. int ret;
  149. ret = phy_g12a_usb3_pcie_cr_bus_read(priv, offset, &reg);
  150. if (ret)
  151. return ret;
  152. reg &= ~mask;
  153. return phy_g12a_usb3_pcie_cr_bus_write(priv, offset, reg | val);
  154. }
  155. static int phy_meson_g12a_usb3_init(struct phy *phy)
  156. {
  157. struct udevice *dev = phy->dev;
  158. struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(dev);
  159. unsigned int data;
  160. int ret;
  161. /* TOFIX Handle PCIE mode */
  162. ret = reset_assert_bulk(&priv->resets);
  163. udelay(1);
  164. ret |= reset_deassert_bulk(&priv->resets);
  165. if (ret)
  166. return ret;
  167. /* Switch PHY to USB3 */
  168. regmap_update_bits(priv->regmap, PHY_R0,
  169. PHY_R0_PCIE_USB3_SWITCH,
  170. PHY_R0_PCIE_USB3_SWITCH);
  171. /*
  172. * WORKAROUND: There is SSPHY suspend bug due to
  173. * which USB enumerates
  174. * in HS mode instead of SS mode. Workaround it by asserting
  175. * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus
  176. * mode
  177. */
  178. ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x102d,
  179. BIT(7), BIT(7));
  180. if (ret)
  181. return ret;
  182. ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x1010, 0xff0, 20);
  183. if (ret)
  184. return ret;
  185. /*
  186. * Fix RX Equalization setting as follows
  187. * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
  188. * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
  189. * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
  190. * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
  191. */
  192. ret = phy_g12a_usb3_pcie_cr_bus_read(priv, 0x1006, &data);
  193. if (ret)
  194. return ret;
  195. data &= ~BIT(6);
  196. data |= BIT(7);
  197. data &= ~(0x7 << 8);
  198. data |= (0x3 << 8);
  199. data |= (1 << 11);
  200. ret = phy_g12a_usb3_pcie_cr_bus_write(priv, 0x1006, data);
  201. if (ret)
  202. return ret;
  203. /*
  204. * Set EQ and TX launch amplitudes as follows
  205. * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
  206. * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
  207. * LANE0.TX_OVRD_DRV_LO.EN set to 1.
  208. */
  209. ret = phy_g12a_usb3_pcie_cr_bus_read(priv, 0x1002, &data);
  210. if (ret)
  211. return ret;
  212. data &= ~0x3f80;
  213. data |= (0x16 << 7);
  214. data &= ~0x7f;
  215. data |= (0x7f | BIT(14));
  216. ret = phy_g12a_usb3_pcie_cr_bus_write(priv, 0x1002, data);
  217. if (ret)
  218. return ret;
  219. /*
  220. * MPLL_LOOP_CTL.PROP_CNTRL = 8
  221. */
  222. ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x30,
  223. 0xf << 4, 8 << 4);
  224. if (ret)
  225. return ret;
  226. regmap_update_bits(priv->regmap, PHY_R2,
  227. PHY_R2_PHY_TX_VBOOST_LVL,
  228. FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4));
  229. regmap_update_bits(priv->regmap, PHY_R1,
  230. PHY_R1_PHY_LOS_BIAS | PHY_R1_PHY_LOS_LEVEL,
  231. FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) |
  232. FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9));
  233. return ret;
  234. }
  235. static int phy_meson_g12a_usb3_exit(struct phy *phy)
  236. {
  237. struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
  238. return reset_assert_bulk(&priv->resets);
  239. }
  240. struct phy_ops meson_g12a_usb3_pcie_phy_ops = {
  241. .init = phy_meson_g12a_usb3_init,
  242. .exit = phy_meson_g12a_usb3_exit,
  243. };
  244. int meson_g12a_usb3_pcie_phy_probe(struct udevice *dev)
  245. {
  246. struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(dev);
  247. int ret;
  248. ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
  249. if (ret)
  250. return ret;
  251. ret = reset_get_bulk(dev, &priv->resets);
  252. if (ret == -ENOTSUPP)
  253. return 0;
  254. else if (ret)
  255. return ret;
  256. #if CONFIG_IS_ENABLED(CLK)
  257. ret = clk_get_by_index(dev, 0, &priv->clk);
  258. if (ret < 0)
  259. return ret;
  260. ret = clk_enable(&priv->clk);
  261. if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
  262. pr_err("failed to enable PHY clock\n");
  263. clk_free(&priv->clk);
  264. return ret;
  265. }
  266. #endif
  267. return 0;
  268. }
  269. static const struct udevice_id meson_g12a_usb3_pcie_phy_ids[] = {
  270. { .compatible = "amlogic,g12a-usb3-pcie-phy" },
  271. { }
  272. };
  273. U_BOOT_DRIVER(meson_g12a_usb3_pcie_phy) = {
  274. .name = "meson_g12a_usb3_pcie_phy",
  275. .id = UCLASS_PHY,
  276. .of_match = meson_g12a_usb3_pcie_phy_ids,
  277. .probe = meson_g12a_usb3_pcie_phy_probe,
  278. .ops = &meson_g12a_usb3_pcie_phy_ops,
  279. .priv_auto_alloc_size = sizeof(struct phy_g12a_usb3_pcie_priv),
  280. };