bcm6318-usbh-phy.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
  4. *
  5. * Derived from linux/arch/mips/bcm63xx/usb-common.c:
  6. * Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
  7. * Copyright 2013 Florian Fainelli <florian@openwrt.org>
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <generic-phy.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <power-domain.h>
  16. #include <reset.h>
  17. #include <asm/io.h>
  18. #include <dm/device.h>
  19. #include <linux/bitops.h>
  20. #include <linux/delay.h>
  21. /* USBH Setup register */
  22. #define USBH_SETUP_REG 0x00
  23. #define USBH_SETUP_IOC BIT(4)
  24. /* USBH PLL Control register */
  25. #define USBH_PLL_REG 0x04
  26. #define USBH_PLL_SUSP_EN BIT(27)
  27. #define USBH_PLL_IDDQ_PWRDN BIT(31)
  28. /* USBH Swap Control register */
  29. #define USBH_SWAP_REG 0x0c
  30. #define USBH_SWAP_OHCI_DATA BIT(0)
  31. #define USBH_SWAP_OHCI_ENDIAN BIT(1)
  32. #define USBH_SWAP_EHCI_DATA BIT(3)
  33. #define USBH_SWAP_EHCI_ENDIAN BIT(4)
  34. /* USBH Sim Control register */
  35. #define USBH_SIM_REG 0x20
  36. #define USBH_SIM_LADDR BIT(5)
  37. struct bcm6318_usbh_priv {
  38. void __iomem *regs;
  39. };
  40. static int bcm6318_usbh_init(struct phy *phy)
  41. {
  42. struct bcm6318_usbh_priv *priv = dev_get_priv(phy->dev);
  43. /* enable pll control susp */
  44. setbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_SUSP_EN);
  45. /* configure to work in native cpu endian */
  46. clrsetbits_be32(priv->regs + USBH_SWAP_REG,
  47. USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
  48. USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
  49. /* setup config */
  50. setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC);
  51. /* disable pll control pwrdn */
  52. clrbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_IDDQ_PWRDN);
  53. /* sim control config */
  54. setbits_be32(priv->regs + USBH_SIM_REG, USBH_SIM_LADDR);
  55. return 0;
  56. }
  57. static struct phy_ops bcm6318_usbh_ops = {
  58. .init = bcm6318_usbh_init,
  59. };
  60. static const struct udevice_id bcm6318_usbh_ids[] = {
  61. { .compatible = "brcm,bcm6318-usbh" },
  62. { /* sentinel */ }
  63. };
  64. static int bcm6318_usbh_probe(struct udevice *dev)
  65. {
  66. struct bcm6318_usbh_priv *priv = dev_get_priv(dev);
  67. struct power_domain pwr_dom;
  68. struct reset_ctl rst_ctl;
  69. struct clk clk;
  70. int ret;
  71. priv->regs = dev_remap_addr(dev);
  72. if (!priv->regs)
  73. return -EINVAL;
  74. /* enable usbh clock */
  75. ret = clk_get_by_name(dev, "usbh", &clk);
  76. if (ret < 0)
  77. return ret;
  78. ret = clk_enable(&clk);
  79. if (ret < 0)
  80. return ret;
  81. ret = clk_free(&clk);
  82. if (ret < 0)
  83. return ret;
  84. /* enable power domain */
  85. ret = power_domain_get(dev, &pwr_dom);
  86. if (ret < 0)
  87. return ret;
  88. ret = power_domain_on(&pwr_dom);
  89. if (ret < 0)
  90. return ret;
  91. ret = power_domain_free(&pwr_dom);
  92. if (ret < 0)
  93. return ret;
  94. /* perform reset */
  95. ret = reset_get_by_index(dev, 0, &rst_ctl);
  96. if (ret < 0)
  97. return ret;
  98. ret = reset_deassert(&rst_ctl);
  99. if (ret < 0)
  100. return ret;
  101. ret = reset_free(&rst_ctl);
  102. if (ret < 0)
  103. return ret;
  104. mdelay(100);
  105. return 0;
  106. }
  107. U_BOOT_DRIVER(bcm6318_usbh) = {
  108. .name = "bcm6318-usbh",
  109. .id = UCLASS_PHY,
  110. .of_match = bcm6318_usbh_ids,
  111. .ops = &bcm6318_usbh_ops,
  112. .priv_auto_alloc_size = sizeof(struct bcm6318_usbh_priv),
  113. .probe = bcm6318_usbh_probe,
  114. };