pcie_phytium.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Phytium PCIE host driver
  4. *
  5. * Heavily based on drivers/pci/pcie_xilinx.c
  6. *
  7. * Copyright (C) 2019
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <pci.h>
  12. #include <asm/io.h>
  13. /**
  14. * struct phytium_pcie - phytium PCIe controller state
  15. * @cfg_base: The base address of memory mapped configuration space
  16. */
  17. struct phytium_pcie {
  18. void *cfg_base;
  19. };
  20. /*
  21. * phytium_pci_skip_dev()
  22. * @parent: Identifies the PCIe device to access
  23. *
  24. * Checks whether the parent of the PCIe device is bridge
  25. *
  26. * Return: true if it is bridge, else false.
  27. */
  28. static int phytium_pci_skip_dev(pci_dev_t parent)
  29. {
  30. unsigned char pos, id;
  31. unsigned long addr = 0x40000000;
  32. unsigned short capreg;
  33. unsigned char port_type;
  34. addr += PCI_BUS(parent) << 20;
  35. addr += PCI_DEV(parent) << 15;
  36. addr += PCI_FUNC(parent) << 12;
  37. pos = 0x34;
  38. while (1) {
  39. pos = readb(addr + pos);
  40. if (pos < 0x40)
  41. break;
  42. pos &= ~3;
  43. id = readb(addr + pos);
  44. if (id == 0xff)
  45. break;
  46. if (id == 0x10) {
  47. capreg = readw(addr + pos + 2);
  48. port_type = (capreg >> 4) & 0xf;
  49. if (port_type == 0x6 || port_type == 0x4)
  50. return 1;
  51. else
  52. return 0;
  53. }
  54. pos += 1;
  55. }
  56. return 0;
  57. }
  58. /**
  59. * pci_phytium_conf_address() - Calculate the address of a config access
  60. * @bus: Pointer to the PCI bus
  61. * @bdf: Identifies the PCIe device to access
  62. * @offset: The offset into the device's configuration space
  63. * @paddress: Pointer to the pointer to write the calculates address to
  64. *
  65. * Calculates the address that should be accessed to perform a PCIe
  66. * configuration space access for a given device identified by the PCIe
  67. * controller device @pcie and the bus, device & function numbers in @bdf. If
  68. * access to the device is not valid then the function will return an error
  69. * code. Otherwise the address to access will be written to the pointer pointed
  70. * to by @paddress.
  71. */
  72. static int pci_phytium_conf_address(const struct udevice *bus, pci_dev_t bdf,
  73. uint offset, void **paddress)
  74. {
  75. struct phytium_pcie *pcie = dev_get_priv(bus);
  76. void *addr;
  77. pci_dev_t bdf_parent;
  78. unsigned int bus_no = PCI_BUS(bdf);
  79. unsigned int dev_no = PCI_DEV(bdf);
  80. bdf_parent = PCI_BDF((bus_no - 1), 0, 0);
  81. addr = pcie->cfg_base;
  82. addr += PCI_BUS(bdf) << 20;
  83. addr += PCI_DEV(bdf) << 15;
  84. addr += PCI_FUNC(bdf) << 12;
  85. if (bus_no > 0 && dev_no > 0) {
  86. if ((readb(addr + PCI_HEADER_TYPE) & 0x7f) !=
  87. PCI_HEADER_TYPE_BRIDGE)
  88. return -ENODEV;
  89. if (phytium_pci_skip_dev(bdf_parent))
  90. return -ENODEV;
  91. }
  92. addr += offset;
  93. *paddress = addr;
  94. return 0;
  95. }
  96. /**
  97. * pci_phytium_read_config() - Read from configuration space
  98. * @bus: Pointer to the PCI bus
  99. * @bdf: Identifies the PCIe device to access
  100. * @offset: The offset into the device's configuration space
  101. * @valuep: A pointer at which to store the read value
  102. * @size: Indicates the size of access to perform
  103. *
  104. * Read a value of size @size from offset @offset within the configuration
  105. * space of the device identified by the bus, device & function numbers in @bdf
  106. * on the PCI bus @bus.
  107. */
  108. static int pci_phytium_read_config(const struct udevice *bus, pci_dev_t bdf,
  109. uint offset, ulong *valuep,
  110. enum pci_size_t size)
  111. {
  112. return pci_generic_mmap_read_config(bus, pci_phytium_conf_address,
  113. bdf, offset, valuep, size);
  114. }
  115. /**
  116. * pci_phytium_write_config() - Write to configuration space
  117. * @bus: Pointer to the PCI bus
  118. * @bdf: Identifies the PCIe device to access
  119. * @offset: The offset into the device's configuration space
  120. * @value: The value to write
  121. * @size: Indicates the size of access to perform
  122. *
  123. * Write the value @value of size @size from offset @offset within the
  124. * configuration space of the device identified by the bus, device & function
  125. * numbers in @bdf on the PCI bus @bus.
  126. */
  127. static int pci_phytium_write_config(struct udevice *bus, pci_dev_t bdf,
  128. uint offset, ulong value,
  129. enum pci_size_t size)
  130. {
  131. return pci_generic_mmap_write_config(bus, pci_phytium_conf_address,
  132. bdf, offset, value, size);
  133. }
  134. /**
  135. * pci_phytium_ofdata_to_platdata() - Translate from DT to device state
  136. * @dev: A pointer to the device being operated on
  137. *
  138. * Translate relevant data from the device tree pertaining to device @dev into
  139. * state that the driver will later make use of. This state is stored in the
  140. * device's private data structure.
  141. *
  142. * Return: 0 on success, else -EINVAL
  143. */
  144. static int pci_phytium_ofdata_to_platdata(struct udevice *dev)
  145. {
  146. struct phytium_pcie *pcie = dev_get_priv(dev);
  147. struct fdt_resource reg_res;
  148. DECLARE_GLOBAL_DATA_PTR;
  149. int err;
  150. err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
  151. 0, &reg_res);
  152. if (err < 0) {
  153. pr_err("\"reg\" resource not found\n");
  154. return err;
  155. }
  156. pcie->cfg_base = map_physmem(reg_res.start,
  157. fdt_resource_size(&reg_res),
  158. MAP_NOCACHE);
  159. return 0;
  160. }
  161. static const struct dm_pci_ops pci_phytium_ops = {
  162. .read_config = pci_phytium_read_config,
  163. .write_config = pci_phytium_write_config,
  164. };
  165. static const struct udevice_id pci_phytium_ids[] = {
  166. { .compatible = "phytium,pcie-host-1.0" },
  167. { }
  168. };
  169. U_BOOT_DRIVER(pci_phytium) = {
  170. .name = "pci_phytium",
  171. .id = UCLASS_PCI,
  172. .of_match = pci_phytium_ids,
  173. .ops = &pci_phytium_ops,
  174. .ofdata_to_platdata = pci_phytium_ofdata_to_platdata,
  175. .priv_auto_alloc_size = sizeof(struct phytium_pcie),
  176. };