pcie_layerscape_gen4_fixup.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright 2018-2020 NXP
  4. *
  5. * PCIe Gen4 driver for NXP Layerscape SoCs
  6. * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
  7. *
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <pci.h>
  13. #include <asm/arch/fsl_serdes.h>
  14. #include <asm/io.h>
  15. #include <errno.h>
  16. #ifdef CONFIG_OF_BOARD_SETUP
  17. #include <linux/libfdt.h>
  18. #include <fdt_support.h>
  19. #ifdef CONFIG_ARM
  20. #include <asm/arch/clock.h>
  21. #endif
  22. #include "pcie_layerscape_gen4.h"
  23. #include "pcie_layerscape_fixup_common.h"
  24. #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  25. /*
  26. * Return next available LUT index.
  27. */
  28. static int ls_pcie_g4_next_lut_index(struct ls_pcie_g4 *pcie)
  29. {
  30. if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
  31. return pcie->next_lut_index++;
  32. return -ENOSPC; /* LUT is full */
  33. }
  34. /*
  35. * Program a single LUT entry
  36. */
  37. static void ls_pcie_g4_lut_set_mapping(struct ls_pcie_g4 *pcie, int index,
  38. u32 devid, u32 streamid)
  39. {
  40. /* leave mask as all zeroes, want to match all bits */
  41. lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
  42. lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
  43. }
  44. /*
  45. * An msi-map is a property to be added to the pci controller
  46. * node. It is a table, where each entry consists of 4 fields
  47. * e.g.:
  48. *
  49. * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
  50. * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
  51. */
  52. static void fdt_pcie_set_msi_map_entry_ls_gen4(void *blob,
  53. struct ls_pcie_g4 *pcie,
  54. u32 devid, u32 streamid)
  55. {
  56. u32 *prop;
  57. u32 phandle;
  58. int nodeoff;
  59. #ifdef CONFIG_FSL_PCIE_COMPAT
  60. nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
  61. pcie->ccsr_res.start);
  62. #else
  63. #error "No CONFIG_FSL_PCIE_COMPAT defined"
  64. #endif
  65. if (nodeoff < 0) {
  66. debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
  67. return;
  68. }
  69. /* get phandle to MSI controller */
  70. prop = (u32 *)fdt_getprop(blob, nodeoff, "msi-parent", 0);
  71. if (!prop) {
  72. debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
  73. __func__, pcie->idx);
  74. return;
  75. }
  76. phandle = fdt32_to_cpu(*prop);
  77. /* set one msi-map row */
  78. fdt_appendprop_u32(blob, nodeoff, "msi-map", devid);
  79. fdt_appendprop_u32(blob, nodeoff, "msi-map", phandle);
  80. fdt_appendprop_u32(blob, nodeoff, "msi-map", streamid);
  81. fdt_appendprop_u32(blob, nodeoff, "msi-map", 1);
  82. }
  83. /*
  84. * An iommu-map is a property to be added to the pci controller
  85. * node. It is a table, where each entry consists of 4 fields
  86. * e.g.:
  87. *
  88. * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
  89. * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
  90. */
  91. static void fdt_pcie_set_iommu_map_entry_ls_gen4(void *blob,
  92. struct ls_pcie_g4 *pcie,
  93. u32 devid, u32 streamid)
  94. {
  95. u32 *prop;
  96. u32 iommu_map[4];
  97. int nodeoff;
  98. int lenp;
  99. #ifdef CONFIG_FSL_PCIE_COMPAT
  100. nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
  101. pcie->ccsr_res.start);
  102. #else
  103. #error "No CONFIG_FSL_PCIE_COMPAT defined"
  104. #endif
  105. if (nodeoff < 0) {
  106. debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
  107. return;
  108. }
  109. /* get phandle to iommu controller */
  110. prop = fdt_getprop_w(blob, nodeoff, "iommu-map", &lenp);
  111. if (!prop) {
  112. debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
  113. __func__, pcie->idx);
  114. return;
  115. }
  116. /* set iommu-map row */
  117. iommu_map[0] = cpu_to_fdt32(devid);
  118. iommu_map[1] = *++prop;
  119. iommu_map[2] = cpu_to_fdt32(streamid);
  120. iommu_map[3] = cpu_to_fdt32(1);
  121. if (devid == 0)
  122. fdt_setprop_inplace(blob, nodeoff, "iommu-map", iommu_map, 16);
  123. else
  124. fdt_appendprop(blob, nodeoff, "iommu-map", iommu_map, 16);
  125. }
  126. static void fdt_fixup_pcie_ls_gen4(void *blob)
  127. {
  128. struct udevice *dev, *bus;
  129. struct ls_pcie_g4 *pcie;
  130. int streamid;
  131. int index;
  132. pci_dev_t bdf;
  133. /* Scan all known buses */
  134. for (pci_find_first_device(&dev); dev; pci_find_next_device(&dev)) {
  135. for (bus = dev; device_is_on_pci_bus(bus);)
  136. bus = bus->parent;
  137. pcie = dev_get_priv(bus);
  138. streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
  139. if (streamid < 0) {
  140. debug("ERROR: no stream ids free\n");
  141. continue;
  142. } else {
  143. pcie->stream_id_cur++;
  144. }
  145. index = ls_pcie_g4_next_lut_index(pcie);
  146. if (index < 0) {
  147. debug("ERROR: no LUT indexes free\n");
  148. continue;
  149. }
  150. /* the DT fixup must be relative to the hose first_busno */
  151. bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
  152. /* map PCI b.d.f to streamID in LUT */
  153. ls_pcie_g4_lut_set_mapping(pcie, index, bdf >> 8, streamid);
  154. /* update msi-map in device tree */
  155. fdt_pcie_set_msi_map_entry_ls_gen4(blob, pcie, bdf >> 8,
  156. streamid);
  157. /* update iommu-map in device tree */
  158. fdt_pcie_set_iommu_map_entry_ls_gen4(blob, pcie, bdf >> 8,
  159. streamid);
  160. }
  161. }
  162. #endif
  163. static void ft_pcie_ep_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
  164. {
  165. int off;
  166. off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
  167. pcie->ccsr_res.start);
  168. if (off < 0) {
  169. debug("%s: ERROR: failed to find pcie compatiable\n",
  170. __func__);
  171. return;
  172. }
  173. if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
  174. fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
  175. else
  176. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  177. }
  178. static void ft_pcie_rc_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
  179. {
  180. int off;
  181. #ifdef CONFIG_FSL_PCIE_COMPAT
  182. off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
  183. pcie->ccsr_res.start);
  184. #else
  185. #error "No CONFIG_FSL_PCIE_COMPAT defined"
  186. #endif
  187. if (off < 0) {
  188. debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
  189. return;
  190. }
  191. if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
  192. fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
  193. else
  194. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  195. }
  196. static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
  197. {
  198. ft_pcie_rc_layerscape_gen4_fix(blob, pcie);
  199. ft_pcie_ep_layerscape_gen4_fix(blob, pcie);
  200. }
  201. /* Fixup Kernel DT for PCIe */
  202. void ft_pci_setup_ls_gen4(void *blob, struct bd_info *bd)
  203. {
  204. struct ls_pcie_g4 *pcie;
  205. list_for_each_entry(pcie, &ls_pcie_g4_list, list)
  206. ft_pcie_layerscape_gen4_setup(blob, pcie);
  207. #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  208. fdt_fixup_pcie_ls_gen4(blob);
  209. #endif
  210. }
  211. #else /* !CONFIG_OF_BOARD_SETUP */
  212. void ft_pci_setup_ls_gen4(void *blob, struct bd_info *bd)
  213. {
  214. }
  215. #endif