pcie_intel_fpga.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel FPGA PCIe host controller driver
  4. *
  5. * Copyright (C) 2013-2018 Intel Corporation. All rights reserved
  6. *
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <pci.h>
  11. #include <asm/io.h>
  12. #include <dm/device_compat.h>
  13. #include <linux/bitops.h>
  14. #include <linux/delay.h>
  15. #define RP_TX_REG0 0x2000
  16. #define RP_TX_CNTRL 0x2004
  17. #define RP_TX_SOP BIT(0)
  18. #define RP_TX_EOP BIT(1)
  19. #define RP_RXCPL_STATUS 0x200C
  20. #define RP_RXCPL_SOP BIT(0)
  21. #define RP_RXCPL_EOP BIT(1)
  22. #define RP_RXCPL_REG 0x2008
  23. #define P2A_INT_STATUS 0x3060
  24. #define P2A_INT_STS_ALL 0xf
  25. #define P2A_INT_ENABLE 0x3070
  26. #define RP_CAP_OFFSET 0x70
  27. /* TLP configuration type 0 and 1 */
  28. #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
  29. #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
  30. #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
  31. #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
  32. #define TLP_PAYLOAD_SIZE 0x01
  33. #define TLP_READ_TAG 0x1d
  34. #define TLP_WRITE_TAG 0x10
  35. #define RP_DEVFN 0
  36. #define RP_CFG_ADDR(pcie, reg) \
  37. ((pcie->hip_base) + (reg) + (1 << 20))
  38. #define RP_SECONDARY(pcie) \
  39. readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
  40. #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
  41. #define TLP_CFGRD_DW0(pcie, bus) \
  42. ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGRD1 \
  43. : TLP_FMTTYPE_CFGRD0) << 24) | \
  44. TLP_PAYLOAD_SIZE)
  45. #define TLP_CFGWR_DW0(pcie, bus) \
  46. ((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGWR1 \
  47. : TLP_FMTTYPE_CFGWR0) << 24) | \
  48. TLP_PAYLOAD_SIZE)
  49. #define TLP_CFG_DW1(pcie, tag, be) \
  50. (((TLP_REQ_ID(pcie->first_busno, RP_DEVFN)) << 16) | (tag << 8) | (be))
  51. #define TLP_CFG_DW2(bus, dev, fn, offset) \
  52. (((bus) << 24) | ((dev) << 19) | ((fn) << 16) | (offset))
  53. #define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
  54. #define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
  55. #define TLP_HDR_SIZE 3
  56. #define TLP_LOOP 20000
  57. #define DWORD_MASK 3
  58. #define IS_ROOT_PORT(pcie, bdf) \
  59. ((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
  60. /**
  61. * struct intel_fpga_pcie - Intel FPGA PCIe controller state
  62. * @bus: Pointer to the PCI bus
  63. * @cra_base: The base address of CRA register space
  64. * @hip_base: The base address of Rootport configuration space
  65. * @first_busno: This driver supports multiple PCIe controllers.
  66. * first_busno stores the bus number of the PCIe root-port
  67. * number which may vary depending on the PCIe setup.
  68. */
  69. struct intel_fpga_pcie {
  70. struct udevice *bus;
  71. void __iomem *cra_base;
  72. void __iomem *hip_base;
  73. int first_busno;
  74. };
  75. /**
  76. * Intel FPGA PCIe port uses BAR0 of RC's configuration space as the
  77. * translation from PCI bus to native BUS. Entire DDR region is mapped
  78. * into PCIe space using these registers, so it can be reached by DMA from
  79. * EP devices.
  80. * The BAR0 of bridge should be hidden during enumeration to avoid the
  81. * sizing and resource allocation by PCIe core.
  82. */
  83. static bool intel_fpga_pcie_hide_rc_bar(struct intel_fpga_pcie *pcie,
  84. pci_dev_t bdf, int offset)
  85. {
  86. if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) == 0 &&
  87. PCI_FUNC(bdf) == 0 && offset == PCI_BASE_ADDRESS_0)
  88. return true;
  89. return false;
  90. }
  91. static inline void cra_writel(struct intel_fpga_pcie *pcie, const u32 value,
  92. const u32 reg)
  93. {
  94. writel(value, pcie->cra_base + reg);
  95. }
  96. static inline u32 cra_readl(struct intel_fpga_pcie *pcie, const u32 reg)
  97. {
  98. return readl(pcie->cra_base + reg);
  99. }
  100. static bool intel_fpga_pcie_link_up(struct intel_fpga_pcie *pcie)
  101. {
  102. return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA))
  103. & PCI_EXP_LNKSTA_DLLLA);
  104. }
  105. static bool intel_fpga_pcie_addr_valid(struct intel_fpga_pcie *pcie,
  106. pci_dev_t bdf)
  107. {
  108. /* If there is no link, then there is no device */
  109. if (!IS_ROOT_PORT(pcie, bdf) && !intel_fpga_pcie_link_up(pcie))
  110. return false;
  111. /* access only one slot on each root port */
  112. if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) > 0)
  113. return false;
  114. if ((PCI_BUS(bdf) == pcie->first_busno + 1) && PCI_DEV(bdf) > 0)
  115. return false;
  116. return true;
  117. }
  118. static void tlp_write_tx(struct intel_fpga_pcie *pcie, u32 reg0, u32 ctrl)
  119. {
  120. cra_writel(pcie, reg0, RP_TX_REG0);
  121. cra_writel(pcie, ctrl, RP_TX_CNTRL);
  122. }
  123. static int tlp_read_packet(struct intel_fpga_pcie *pcie, u32 *value)
  124. {
  125. int i;
  126. u32 ctrl;
  127. u32 comp_status;
  128. u32 dw[4];
  129. u32 count = 0;
  130. for (i = 0; i < TLP_LOOP; i++) {
  131. ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
  132. if (!(ctrl & RP_RXCPL_SOP))
  133. continue;
  134. /* read first DW */
  135. dw[count++] = cra_readl(pcie, RP_RXCPL_REG);
  136. /* Poll for EOP */
  137. for (i = 0; i < TLP_LOOP; i++) {
  138. ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
  139. dw[count++] = cra_readl(pcie, RP_RXCPL_REG);
  140. if (ctrl & RP_RXCPL_EOP) {
  141. comp_status = TLP_COMP_STATUS(dw[1]);
  142. if (comp_status) {
  143. *value = pci_get_ff(PCI_SIZE_32);
  144. return 0;
  145. }
  146. if (value &&
  147. TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&
  148. count >= 3)
  149. *value = dw[3];
  150. return 0;
  151. }
  152. }
  153. udelay(5);
  154. }
  155. dev_err(pcie->dev, "read TLP packet timed out\n");
  156. return -ENODEV;
  157. }
  158. static void tlp_write_packet(struct intel_fpga_pcie *pcie, u32 *headers,
  159. u32 data)
  160. {
  161. tlp_write_tx(pcie, headers[0], RP_TX_SOP);
  162. tlp_write_tx(pcie, headers[1], 0);
  163. tlp_write_tx(pcie, headers[2], 0);
  164. tlp_write_tx(pcie, data, RP_TX_EOP);
  165. }
  166. static int tlp_cfg_dword_read(struct intel_fpga_pcie *pcie, pci_dev_t bdf,
  167. int offset, u8 byte_en, u32 *value)
  168. {
  169. u32 headers[TLP_HDR_SIZE];
  170. u8 busno = PCI_BUS(bdf);
  171. headers[0] = TLP_CFGRD_DW0(pcie, busno);
  172. headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
  173. headers[2] = TLP_CFG_DW2(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
  174. tlp_write_packet(pcie, headers, 0);
  175. return tlp_read_packet(pcie, value);
  176. }
  177. static int tlp_cfg_dword_write(struct intel_fpga_pcie *pcie, pci_dev_t bdf,
  178. int offset, u8 byte_en, u32 value)
  179. {
  180. u32 headers[TLP_HDR_SIZE];
  181. u8 busno = PCI_BUS(bdf);
  182. headers[0] = TLP_CFGWR_DW0(pcie, busno);
  183. headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
  184. headers[2] = TLP_CFG_DW2(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
  185. tlp_write_packet(pcie, headers, value);
  186. return tlp_read_packet(pcie, NULL);
  187. }
  188. int intel_fpga_rp_conf_addr(const struct udevice *bus, pci_dev_t bdf,
  189. uint offset, void **paddress)
  190. {
  191. struct intel_fpga_pcie *pcie = dev_get_priv(bus);
  192. *paddress = RP_CFG_ADDR(pcie, offset);
  193. return 0;
  194. }
  195. static int intel_fpga_pcie_rp_rd_conf(struct udevice *bus, pci_dev_t bdf,
  196. uint offset, ulong *valuep,
  197. enum pci_size_t size)
  198. {
  199. return pci_generic_mmap_read_config(bus, intel_fpga_rp_conf_addr,
  200. bdf, offset, valuep, size);
  201. }
  202. static int intel_fpga_pcie_rp_wr_conf(struct udevice *bus, pci_dev_t bdf,
  203. uint offset, ulong value,
  204. enum pci_size_t size)
  205. {
  206. int ret;
  207. struct intel_fpga_pcie *pcie = dev_get_priv(bus);
  208. ret = pci_generic_mmap_write_config(bus, intel_fpga_rp_conf_addr,
  209. bdf, offset, value, size);
  210. if (!ret) {
  211. /* Monitor changes to PCI_PRIMARY_BUS register on root port
  212. * and update local copy of root bus number accordingly.
  213. */
  214. if (offset == PCI_PRIMARY_BUS)
  215. pcie->first_busno = (u8)(value);
  216. }
  217. return ret;
  218. }
  219. static u8 pcie_get_byte_en(uint offset, enum pci_size_t size)
  220. {
  221. switch (size) {
  222. case PCI_SIZE_8:
  223. return 1 << (offset & 3);
  224. case PCI_SIZE_16:
  225. return 3 << (offset & 3);
  226. default:
  227. return 0xf;
  228. }
  229. }
  230. static int _pcie_intel_fpga_read_config(struct intel_fpga_pcie *pcie,
  231. pci_dev_t bdf, uint offset,
  232. ulong *valuep, enum pci_size_t size)
  233. {
  234. int ret;
  235. u32 data;
  236. u8 byte_en;
  237. /* Uses memory mapped method to read rootport config registers */
  238. if (IS_ROOT_PORT(pcie, bdf))
  239. return intel_fpga_pcie_rp_rd_conf(pcie->bus, bdf,
  240. offset, valuep, size);
  241. byte_en = pcie_get_byte_en(offset, size);
  242. ret = tlp_cfg_dword_read(pcie, bdf, offset & ~DWORD_MASK,
  243. byte_en, &data);
  244. if (ret)
  245. return ret;
  246. dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
  247. offset, size, data);
  248. *valuep = pci_conv_32_to_size(data, offset, size);
  249. return 0;
  250. }
  251. static int _pcie_intel_fpga_write_config(struct intel_fpga_pcie *pcie,
  252. pci_dev_t bdf, uint offset,
  253. ulong value, enum pci_size_t size)
  254. {
  255. u32 data;
  256. u8 byte_en;
  257. dev_dbg(pcie->dev, "PCIE CFG write: (b.d.f)=(%02d.%02d.%02d)\n",
  258. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  259. dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
  260. offset, size, value);
  261. /* Uses memory mapped method to read rootport config registers */
  262. if (IS_ROOT_PORT(pcie, bdf))
  263. return intel_fpga_pcie_rp_wr_conf(pcie->bus, bdf, offset,
  264. value, size);
  265. byte_en = pcie_get_byte_en(offset, size);
  266. data = pci_conv_size_to_32(0, value, offset, size);
  267. return tlp_cfg_dword_write(pcie, bdf, offset & ~DWORD_MASK,
  268. byte_en, data);
  269. }
  270. static int pcie_intel_fpga_read_config(const struct udevice *bus, pci_dev_t bdf,
  271. uint offset, ulong *valuep,
  272. enum pci_size_t size)
  273. {
  274. struct intel_fpga_pcie *pcie = dev_get_priv(bus);
  275. dev_dbg(pcie->dev, "PCIE CFG read: (b.d.f)=(%02d.%02d.%02d)\n",
  276. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  277. if (intel_fpga_pcie_hide_rc_bar(pcie, bdf, offset)) {
  278. *valuep = (u32)pci_get_ff(size);
  279. return 0;
  280. }
  281. if (!intel_fpga_pcie_addr_valid(pcie, bdf)) {
  282. *valuep = (u32)pci_get_ff(size);
  283. return 0;
  284. }
  285. return _pcie_intel_fpga_read_config(pcie, bdf, offset, valuep, size);
  286. }
  287. static int pcie_intel_fpga_write_config(struct udevice *bus, pci_dev_t bdf,
  288. uint offset, ulong value,
  289. enum pci_size_t size)
  290. {
  291. struct intel_fpga_pcie *pcie = dev_get_priv(bus);
  292. if (intel_fpga_pcie_hide_rc_bar(pcie, bdf, offset))
  293. return 0;
  294. if (!intel_fpga_pcie_addr_valid(pcie, bdf))
  295. return 0;
  296. return _pcie_intel_fpga_write_config(pcie, bdf, offset, value,
  297. size);
  298. }
  299. static int pcie_intel_fpga_probe(struct udevice *dev)
  300. {
  301. struct intel_fpga_pcie *pcie = dev_get_priv(dev);
  302. pcie->bus = pci_get_controller(dev);
  303. pcie->first_busno = dev->seq;
  304. /* clear all interrupts */
  305. cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
  306. /* disable all interrupts */
  307. cra_writel(pcie, 0, P2A_INT_ENABLE);
  308. return 0;
  309. }
  310. static int pcie_intel_fpga_ofdata_to_platdata(struct udevice *dev)
  311. {
  312. struct intel_fpga_pcie *pcie = dev_get_priv(dev);
  313. struct fdt_resource reg_res;
  314. int node = dev_of_offset(dev);
  315. int ret;
  316. DECLARE_GLOBAL_DATA_PTR;
  317. ret = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names",
  318. "Cra", &reg_res);
  319. if (ret) {
  320. dev_err(dev, "resource \"Cra\" not found\n");
  321. return ret;
  322. }
  323. pcie->cra_base = map_physmem(reg_res.start,
  324. fdt_resource_size(&reg_res),
  325. MAP_NOCACHE);
  326. ret = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names",
  327. "Hip", &reg_res);
  328. if (ret) {
  329. dev_err(dev, "resource \"Hip\" not found\n");
  330. return ret;
  331. }
  332. pcie->hip_base = map_physmem(reg_res.start,
  333. fdt_resource_size(&reg_res),
  334. MAP_NOCACHE);
  335. return 0;
  336. }
  337. static const struct dm_pci_ops pcie_intel_fpga_ops = {
  338. .read_config = pcie_intel_fpga_read_config,
  339. .write_config = pcie_intel_fpga_write_config,
  340. };
  341. static const struct udevice_id pcie_intel_fpga_ids[] = {
  342. { .compatible = "altr,pcie-root-port-2.0" },
  343. {},
  344. };
  345. U_BOOT_DRIVER(pcie_intel_fpga) = {
  346. .name = "pcie_intel_fpga",
  347. .id = UCLASS_PCI,
  348. .of_match = pcie_intel_fpga_ids,
  349. .ops = &pcie_intel_fpga_ops,
  350. .ofdata_to_platdata = pcie_intel_fpga_ofdata_to_platdata,
  351. .probe = pcie_intel_fpga_probe,
  352. .priv_auto_alloc_size = sizeof(struct intel_fpga_pcie),
  353. };