pcie_imx.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Freescale i.MX6 PCI Express Root-Complex driver
  4. *
  5. * Copyright (C) 2013 Marek Vasut <marex@denx.de>
  6. *
  7. * Based on upstream Linux kernel driver:
  8. * pci-imx6.c: Sean Cross <xobs@kosagi.com>
  9. * pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
  10. */
  11. #include <common.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <pci.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/iomux.h>
  18. #include <asm/arch/crm_regs.h>
  19. #include <asm/gpio.h>
  20. #include <asm/io.h>
  21. #include <dm.h>
  22. #include <linux/delay.h>
  23. #include <linux/sizes.h>
  24. #include <errno.h>
  25. #include <asm/arch/sys_proto.h>
  26. #define PCI_ACCESS_READ 0
  27. #define PCI_ACCESS_WRITE 1
  28. #ifdef CONFIG_MX6SX
  29. #define MX6_DBI_ADDR 0x08ffc000
  30. #define MX6_IO_ADDR 0x08000000
  31. #define MX6_MEM_ADDR 0x08100000
  32. #define MX6_ROOT_ADDR 0x08f00000
  33. #else
  34. #define MX6_DBI_ADDR 0x01ffc000
  35. #define MX6_IO_ADDR 0x01000000
  36. #define MX6_MEM_ADDR 0x01100000
  37. #define MX6_ROOT_ADDR 0x01f00000
  38. #endif
  39. #define MX6_DBI_SIZE 0x4000
  40. #define MX6_IO_SIZE 0x100000
  41. #define MX6_MEM_SIZE 0xe00000
  42. #define MX6_ROOT_SIZE 0xfc000
  43. /* PCIe Port Logic registers (memory-mapped) */
  44. #define PL_OFFSET 0x700
  45. #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
  46. #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
  47. #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
  48. #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
  49. #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
  50. #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
  51. #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
  52. #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
  53. #define PCIE_PHY_CTRL_DATA_LOC 0
  54. #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
  55. #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
  56. #define PCIE_PHY_CTRL_WR_LOC 18
  57. #define PCIE_PHY_CTRL_RD_LOC 19
  58. #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
  59. #define PCIE_PHY_STAT_DATA_LOC 0
  60. #define PCIE_PHY_STAT_ACK_LOC 16
  61. /* PHY registers (not memory-mapped) */
  62. #define PCIE_PHY_RX_ASIC_OUT 0x100D
  63. #define PHY_RX_OVRD_IN_LO 0x1005
  64. #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
  65. #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
  66. #define PCIE_PHY_PUP_REQ (1 << 7)
  67. /* iATU registers */
  68. #define PCIE_ATU_VIEWPORT 0x900
  69. #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
  70. #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
  71. #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
  72. #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
  73. #define PCIE_ATU_CR1 0x904
  74. #define PCIE_ATU_TYPE_MEM (0x0 << 0)
  75. #define PCIE_ATU_TYPE_IO (0x2 << 0)
  76. #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
  77. #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
  78. #define PCIE_ATU_CR2 0x908
  79. #define PCIE_ATU_ENABLE (0x1 << 31)
  80. #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
  81. #define PCIE_ATU_LOWER_BASE 0x90C
  82. #define PCIE_ATU_UPPER_BASE 0x910
  83. #define PCIE_ATU_LIMIT 0x914
  84. #define PCIE_ATU_LOWER_TARGET 0x918
  85. #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
  86. #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
  87. #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
  88. #define PCIE_ATU_UPPER_TARGET 0x91C
  89. struct imx_pcie_priv {
  90. void __iomem *dbi_base;
  91. void __iomem *cfg_base;
  92. };
  93. /*
  94. * PHY access functions
  95. */
  96. static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
  97. {
  98. u32 val;
  99. u32 max_iterations = 10;
  100. u32 wait_counter = 0;
  101. do {
  102. val = readl(dbi_base + PCIE_PHY_STAT);
  103. val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
  104. wait_counter++;
  105. if (val == exp_val)
  106. return 0;
  107. udelay(1);
  108. } while (wait_counter < max_iterations);
  109. return -ETIMEDOUT;
  110. }
  111. static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
  112. {
  113. u32 val;
  114. int ret;
  115. val = addr << PCIE_PHY_CTRL_DATA_LOC;
  116. writel(val, dbi_base + PCIE_PHY_CTRL);
  117. val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
  118. writel(val, dbi_base + PCIE_PHY_CTRL);
  119. ret = pcie_phy_poll_ack(dbi_base, 1);
  120. if (ret)
  121. return ret;
  122. val = addr << PCIE_PHY_CTRL_DATA_LOC;
  123. writel(val, dbi_base + PCIE_PHY_CTRL);
  124. ret = pcie_phy_poll_ack(dbi_base, 0);
  125. if (ret)
  126. return ret;
  127. return 0;
  128. }
  129. /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
  130. static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
  131. {
  132. u32 val, phy_ctl;
  133. int ret;
  134. ret = pcie_phy_wait_ack(dbi_base, addr);
  135. if (ret)
  136. return ret;
  137. /* assert Read signal */
  138. phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
  139. writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
  140. ret = pcie_phy_poll_ack(dbi_base, 1);
  141. if (ret)
  142. return ret;
  143. val = readl(dbi_base + PCIE_PHY_STAT);
  144. *data = val & 0xffff;
  145. /* deassert Read signal */
  146. writel(0x00, dbi_base + PCIE_PHY_CTRL);
  147. ret = pcie_phy_poll_ack(dbi_base, 0);
  148. if (ret)
  149. return ret;
  150. return 0;
  151. }
  152. static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
  153. {
  154. u32 var;
  155. int ret;
  156. /* write addr */
  157. /* cap addr */
  158. ret = pcie_phy_wait_ack(dbi_base, addr);
  159. if (ret)
  160. return ret;
  161. var = data << PCIE_PHY_CTRL_DATA_LOC;
  162. writel(var, dbi_base + PCIE_PHY_CTRL);
  163. /* capture data */
  164. var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
  165. writel(var, dbi_base + PCIE_PHY_CTRL);
  166. ret = pcie_phy_poll_ack(dbi_base, 1);
  167. if (ret)
  168. return ret;
  169. /* deassert cap data */
  170. var = data << PCIE_PHY_CTRL_DATA_LOC;
  171. writel(var, dbi_base + PCIE_PHY_CTRL);
  172. /* wait for ack de-assertion */
  173. ret = pcie_phy_poll_ack(dbi_base, 0);
  174. if (ret)
  175. return ret;
  176. /* assert wr signal */
  177. var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
  178. writel(var, dbi_base + PCIE_PHY_CTRL);
  179. /* wait for ack */
  180. ret = pcie_phy_poll_ack(dbi_base, 1);
  181. if (ret)
  182. return ret;
  183. /* deassert wr signal */
  184. var = data << PCIE_PHY_CTRL_DATA_LOC;
  185. writel(var, dbi_base + PCIE_PHY_CTRL);
  186. /* wait for ack de-assertion */
  187. ret = pcie_phy_poll_ack(dbi_base, 0);
  188. if (ret)
  189. return ret;
  190. writel(0x0, dbi_base + PCIE_PHY_CTRL);
  191. return 0;
  192. }
  193. static int imx6_pcie_link_up(struct imx_pcie_priv *priv)
  194. {
  195. u32 rc, ltssm;
  196. int rx_valid, temp;
  197. /* link is debug bit 36, debug register 1 starts at bit 32 */
  198. rc = readl(priv->dbi_base + PCIE_PHY_DEBUG_R1);
  199. if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
  200. !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
  201. return -EAGAIN;
  202. /*
  203. * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
  204. * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
  205. * If (MAC/LTSSM.state == Recovery.RcvrLock)
  206. * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
  207. * to gen2 is stuck
  208. */
  209. pcie_phy_read(priv->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
  210. ltssm = readl(priv->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
  211. if (rx_valid & 0x01)
  212. return 0;
  213. if (ltssm != 0x0d)
  214. return 0;
  215. printf("transition to gen2 is stuck, reset PHY!\n");
  216. pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
  217. temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
  218. pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
  219. udelay(3000);
  220. pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
  221. temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
  222. pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
  223. return 0;
  224. }
  225. /*
  226. * iATU region setup
  227. */
  228. static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
  229. {
  230. /*
  231. * i.MX6 defines 16MB in the AXI address map for PCIe.
  232. *
  233. * That address space excepted the pcie registers is
  234. * split and defined into different regions by iATU,
  235. * with sizes and offsets as follows:
  236. *
  237. * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
  238. * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
  239. * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
  240. */
  241. /* CMD reg:I/O space, MEM space, and Bus Master Enable */
  242. setbits_le32(priv->dbi_base + PCI_COMMAND,
  243. PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  244. /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
  245. setbits_le32(priv->dbi_base + PCI_CLASS_REVISION,
  246. PCI_CLASS_BRIDGE_PCI << 16);
  247. /* Region #0 is used for Outbound CFG space access. */
  248. writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
  249. writel(lower_32_bits((uintptr_t)priv->cfg_base),
  250. priv->dbi_base + PCIE_ATU_LOWER_BASE);
  251. writel(upper_32_bits((uintptr_t)priv->cfg_base),
  252. priv->dbi_base + PCIE_ATU_UPPER_BASE);
  253. writel(lower_32_bits((uintptr_t)priv->cfg_base + MX6_ROOT_SIZE),
  254. priv->dbi_base + PCIE_ATU_LIMIT);
  255. writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
  256. writel(0, priv->dbi_base + PCIE_ATU_UPPER_TARGET);
  257. writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
  258. writel(PCIE_ATU_ENABLE, priv->dbi_base + PCIE_ATU_CR2);
  259. return 0;
  260. }
  261. /*
  262. * PCI Express accessors
  263. */
  264. static void __iomem *get_bus_address(struct imx_pcie_priv *priv,
  265. pci_dev_t d, int where)
  266. {
  267. void __iomem *va_address;
  268. /* Reconfigure Region #0 */
  269. writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
  270. if (PCI_BUS(d) < 2)
  271. writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
  272. else
  273. writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
  274. if (PCI_BUS(d) == 0) {
  275. va_address = priv->dbi_base;
  276. } else {
  277. writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
  278. va_address = priv->cfg_base;
  279. }
  280. va_address += (where & ~0x3);
  281. return va_address;
  282. }
  283. static int imx_pcie_addr_valid(pci_dev_t d)
  284. {
  285. if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
  286. return -EINVAL;
  287. if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
  288. return -EINVAL;
  289. return 0;
  290. }
  291. /*
  292. * Replace the original ARM DABT handler with a simple jump-back one.
  293. *
  294. * The problem here is that if we have a PCIe bridge attached to this PCIe
  295. * controller, but no PCIe device is connected to the bridges' downstream
  296. * port, the attempt to read/write from/to the config space will produce
  297. * a DABT. This is a behavior of the controller and can not be disabled
  298. * unfortuatelly.
  299. *
  300. * To work around the problem, we backup the current DABT handler address
  301. * and replace it with our own DABT handler, which only bounces right back
  302. * into the code.
  303. */
  304. static void imx_pcie_fix_dabt_handler(bool set)
  305. {
  306. extern uint32_t *_data_abort;
  307. uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
  308. static const uint32_t data_abort_bounce_handler = 0xe25ef004;
  309. uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;
  310. static uint32_t data_abort_backup;
  311. if (set) {
  312. data_abort_backup = *data_abort_addr;
  313. *data_abort_addr = data_abort_bounce_addr;
  314. } else {
  315. *data_abort_addr = data_abort_backup;
  316. }
  317. }
  318. static int imx_pcie_read_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
  319. int where, u32 *val)
  320. {
  321. void __iomem *va_address;
  322. int ret;
  323. ret = imx_pcie_addr_valid(d);
  324. if (ret) {
  325. *val = 0xffffffff;
  326. return 0;
  327. }
  328. va_address = get_bus_address(priv, d, where);
  329. /*
  330. * Read the PCIe config space. We must replace the DABT handler
  331. * here in case we got data abort from the PCIe controller, see
  332. * imx_pcie_fix_dabt_handler() description. Note that writing the
  333. * "val" with valid value is also imperative here as in case we
  334. * did got DABT, the val would contain random value.
  335. */
  336. imx_pcie_fix_dabt_handler(true);
  337. writel(0xffffffff, val);
  338. *val = readl(va_address);
  339. imx_pcie_fix_dabt_handler(false);
  340. return 0;
  341. }
  342. static int imx_pcie_write_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
  343. int where, u32 val)
  344. {
  345. void __iomem *va_address = NULL;
  346. int ret;
  347. ret = imx_pcie_addr_valid(d);
  348. if (ret)
  349. return ret;
  350. va_address = get_bus_address(priv, d, where);
  351. /*
  352. * Write the PCIe config space. We must replace the DABT handler
  353. * here in case we got data abort from the PCIe controller, see
  354. * imx_pcie_fix_dabt_handler() description.
  355. */
  356. imx_pcie_fix_dabt_handler(true);
  357. writel(val, va_address);
  358. imx_pcie_fix_dabt_handler(false);
  359. return 0;
  360. }
  361. /*
  362. * Initial bus setup
  363. */
  364. static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv,
  365. bool prepare_for_boot)
  366. {
  367. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  368. if (is_mx6dqp())
  369. setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
  370. #if defined(CONFIG_MX6SX)
  371. struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
  372. /* SSP_EN is not used on MX6SX anymore */
  373. setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
  374. /* Force PCIe PHY reset */
  375. setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
  376. /* Power up PCIe PHY */
  377. setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
  378. #else
  379. /*
  380. * If the bootloader already enabled the link we need some special
  381. * handling to get the core back into a state where it is safe to
  382. * touch it for configuration. As there is no dedicated reset signal
  383. * wired up for MX6QDL, we need to manually force LTSSM into "detect"
  384. * state before completely disabling LTSSM, which is a prerequisite
  385. * for core configuration.
  386. *
  387. * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
  388. * indication that the bootloader activated the link.
  389. */
  390. if (is_mx6dq() && prepare_for_boot) {
  391. u32 val, gpr1, gpr12;
  392. gpr1 = readl(&iomuxc_regs->gpr[1]);
  393. gpr12 = readl(&iomuxc_regs->gpr[12]);
  394. if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
  395. (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
  396. val = readl(priv->dbi_base + PCIE_PL_PFLR);
  397. val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
  398. val |= PCIE_PL_PFLR_FORCE_LINK;
  399. imx_pcie_fix_dabt_handler(true);
  400. writel(val, priv->dbi_base + PCIE_PL_PFLR);
  401. imx_pcie_fix_dabt_handler(false);
  402. gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
  403. writel(val, &iomuxc_regs->gpr[12]);
  404. }
  405. }
  406. setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
  407. clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
  408. #endif
  409. return 0;
  410. }
  411. static int imx6_pcie_init_phy(void)
  412. {
  413. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  414. clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
  415. clrsetbits_le32(&iomuxc_regs->gpr[12],
  416. IOMUXC_GPR12_DEVICE_TYPE_MASK,
  417. IOMUXC_GPR12_DEVICE_TYPE_RC);
  418. clrsetbits_le32(&iomuxc_regs->gpr[12],
  419. IOMUXC_GPR12_LOS_LEVEL_MASK,
  420. IOMUXC_GPR12_LOS_LEVEL_9);
  421. #ifdef CONFIG_MX6SX
  422. clrsetbits_le32(&iomuxc_regs->gpr[12],
  423. IOMUXC_GPR12_RX_EQ_MASK,
  424. IOMUXC_GPR12_RX_EQ_2);
  425. #endif
  426. writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
  427. (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
  428. (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
  429. (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
  430. (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
  431. &iomuxc_regs->gpr[8]);
  432. return 0;
  433. }
  434. __weak int imx6_pcie_toggle_power(void)
  435. {
  436. #ifdef CONFIG_PCIE_IMX_POWER_GPIO
  437. gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
  438. gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
  439. mdelay(20);
  440. gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
  441. mdelay(20);
  442. gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
  443. #endif
  444. return 0;
  445. }
  446. __weak int imx6_pcie_toggle_reset(void)
  447. {
  448. /*
  449. * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
  450. * for detailed understanding of the PCIe CR reset logic.
  451. *
  452. * The PCIe #PERST reset line _MUST_ be connected, otherwise your
  453. * design does not conform to the specification. You must wait at
  454. * least 20 ms after de-asserting the #PERST so the EP device can
  455. * do self-initialisation.
  456. *
  457. * In case your #PERST pin is connected to a plain GPIO pin of the
  458. * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
  459. * configuration file and the condition below will handle the rest
  460. * of the reset toggling.
  461. *
  462. * In case your #PERST toggling logic is more complex, for example
  463. * connected via CPLD or somesuch, you can override this function
  464. * in your board file and implement reset logic as needed. You must
  465. * not forget to wait at least 20 ms after de-asserting #PERST in
  466. * this case either though.
  467. *
  468. * In case your #PERST line of the PCIe EP device is not connected
  469. * at all, your design is broken and you should fix your design,
  470. * otherwise you will observe problems like for example the link
  471. * not coming up after rebooting the system back from running Linux
  472. * that uses the PCIe as well OR the PCIe link might not come up in
  473. * Linux at all in the first place since it's in some non-reset
  474. * state due to being previously used in U-Boot.
  475. */
  476. #ifdef CONFIG_PCIE_IMX_PERST_GPIO
  477. gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
  478. gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
  479. mdelay(20);
  480. gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
  481. mdelay(20);
  482. gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
  483. #else
  484. puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
  485. #endif
  486. return 0;
  487. }
  488. static int imx6_pcie_deassert_core_reset(void)
  489. {
  490. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  491. imx6_pcie_toggle_power();
  492. enable_pcie_clock();
  493. if (is_mx6dqp())
  494. clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
  495. /*
  496. * Wait for the clock to settle a bit, when the clock are sourced
  497. * from the CPU, we need about 30 ms to settle.
  498. */
  499. mdelay(50);
  500. #if defined(CONFIG_MX6SX)
  501. /* SSP_EN is not used on MX6SX anymore */
  502. clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
  503. /* Clear PCIe PHY reset bit */
  504. clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
  505. #else
  506. /* Enable PCIe */
  507. clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
  508. setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
  509. #endif
  510. imx6_pcie_toggle_reset();
  511. return 0;
  512. }
  513. static int imx_pcie_link_up(struct imx_pcie_priv *priv)
  514. {
  515. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  516. uint32_t tmp;
  517. int count = 0;
  518. imx6_pcie_assert_core_reset(priv, false);
  519. imx6_pcie_init_phy();
  520. imx6_pcie_deassert_core_reset();
  521. imx_pcie_regions_setup(priv);
  522. /*
  523. * By default, the subordinate is set equally to the secondary
  524. * bus (0x01) when the RC boots.
  525. * This means that theoretically, only bus 1 is reachable from the RC.
  526. * Force the PCIe RC subordinate to 0xff, otherwise no downstream
  527. * devices will be detected if the enumeration is applied strictly.
  528. */
  529. tmp = readl(priv->dbi_base + 0x18);
  530. tmp |= (0xff << 16);
  531. writel(tmp, priv->dbi_base + 0x18);
  532. /*
  533. * FIXME: Force the PCIe RC to Gen1 operation
  534. * The RC must be forced into Gen1 mode before bringing the link
  535. * up, otherwise no downstream devices are detected. After the
  536. * link is up, a managed Gen1->Gen2 transition can be initiated.
  537. */
  538. tmp = readl(priv->dbi_base + 0x7c);
  539. tmp &= ~0xf;
  540. tmp |= 0x1;
  541. writel(tmp, priv->dbi_base + 0x7c);
  542. /* LTSSM enable, starting link. */
  543. setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
  544. while (!imx6_pcie_link_up(priv)) {
  545. udelay(10);
  546. count++;
  547. if (count >= 4000) {
  548. #ifdef CONFIG_PCI_SCAN_SHOW
  549. puts("PCI: pcie phy link never came up\n");
  550. #endif
  551. debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
  552. readl(priv->dbi_base + PCIE_PHY_DEBUG_R0),
  553. readl(priv->dbi_base + PCIE_PHY_DEBUG_R1));
  554. return -EINVAL;
  555. }
  556. }
  557. return 0;
  558. }
  559. #if !CONFIG_IS_ENABLED(DM_PCI)
  560. static struct imx_pcie_priv imx_pcie_priv = {
  561. .dbi_base = (void __iomem *)MX6_DBI_ADDR,
  562. .cfg_base = (void __iomem *)MX6_ROOT_ADDR,
  563. };
  564. static struct imx_pcie_priv *priv = &imx_pcie_priv;
  565. static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
  566. int where, u32 *val)
  567. {
  568. struct imx_pcie_priv *priv = hose->priv_data;
  569. return imx_pcie_read_cfg(priv, d, where, val);
  570. }
  571. static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
  572. int where, u32 val)
  573. {
  574. struct imx_pcie_priv *priv = hose->priv_data;
  575. return imx_pcie_write_cfg(priv, d, where, val);
  576. }
  577. void imx_pcie_init(void)
  578. {
  579. /* Static instance of the controller. */
  580. static struct pci_controller pcc;
  581. struct pci_controller *hose = &pcc;
  582. int ret;
  583. memset(&pcc, 0, sizeof(pcc));
  584. hose->priv_data = priv;
  585. /* PCI I/O space */
  586. pci_set_region(&hose->regions[0],
  587. MX6_IO_ADDR, MX6_IO_ADDR,
  588. MX6_IO_SIZE, PCI_REGION_IO);
  589. /* PCI memory space */
  590. pci_set_region(&hose->regions[1],
  591. MX6_MEM_ADDR, MX6_MEM_ADDR,
  592. MX6_MEM_SIZE, PCI_REGION_MEM);
  593. /* System memory space */
  594. pci_set_region(&hose->regions[2],
  595. MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
  596. 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  597. hose->region_count = 3;
  598. pci_set_ops(hose,
  599. pci_hose_read_config_byte_via_dword,
  600. pci_hose_read_config_word_via_dword,
  601. imx_pcie_read_config,
  602. pci_hose_write_config_byte_via_dword,
  603. pci_hose_write_config_word_via_dword,
  604. imx_pcie_write_config);
  605. /* Start the controller. */
  606. ret = imx_pcie_link_up(priv);
  607. if (!ret) {
  608. pci_register_hose(hose);
  609. hose->last_busno = pci_hose_scan(hose);
  610. }
  611. }
  612. void imx_pcie_remove(void)
  613. {
  614. imx6_pcie_assert_core_reset(priv, true);
  615. }
  616. /* Probe function. */
  617. void pci_init_board(void)
  618. {
  619. imx_pcie_init();
  620. }
  621. #else
  622. static int imx_pcie_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
  623. uint offset, ulong *value,
  624. enum pci_size_t size)
  625. {
  626. struct imx_pcie_priv *priv = dev_get_priv(dev);
  627. u32 tmpval;
  628. int ret;
  629. ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
  630. if (ret)
  631. return ret;
  632. *value = pci_conv_32_to_size(tmpval, offset, size);
  633. return 0;
  634. }
  635. static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf,
  636. uint offset, ulong value,
  637. enum pci_size_t size)
  638. {
  639. struct imx_pcie_priv *priv = dev_get_priv(dev);
  640. u32 tmpval, newval;
  641. int ret;
  642. ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
  643. if (ret)
  644. return ret;
  645. newval = pci_conv_size_to_32(tmpval, value, offset, size);
  646. return imx_pcie_write_cfg(priv, bdf, offset, newval);
  647. }
  648. static int imx_pcie_dm_probe(struct udevice *dev)
  649. {
  650. struct imx_pcie_priv *priv = dev_get_priv(dev);
  651. return imx_pcie_link_up(priv);
  652. }
  653. static int imx_pcie_dm_remove(struct udevice *dev)
  654. {
  655. struct imx_pcie_priv *priv = dev_get_priv(dev);
  656. imx6_pcie_assert_core_reset(priv, true);
  657. return 0;
  658. }
  659. static int imx_pcie_ofdata_to_platdata(struct udevice *dev)
  660. {
  661. struct imx_pcie_priv *priv = dev_get_priv(dev);
  662. priv->dbi_base = (void __iomem *)devfdt_get_addr_index(dev, 0);
  663. priv->cfg_base = (void __iomem *)devfdt_get_addr_index(dev, 1);
  664. if (!priv->dbi_base || !priv->cfg_base)
  665. return -EINVAL;
  666. return 0;
  667. }
  668. static const struct dm_pci_ops imx_pcie_ops = {
  669. .read_config = imx_pcie_dm_read_config,
  670. .write_config = imx_pcie_dm_write_config,
  671. };
  672. static const struct udevice_id imx_pcie_ids[] = {
  673. { .compatible = "fsl,imx6q-pcie" },
  674. { .compatible = "fsl,imx6sx-pcie" },
  675. { }
  676. };
  677. U_BOOT_DRIVER(imx_pcie) = {
  678. .name = "imx_pcie",
  679. .id = UCLASS_PCI,
  680. .of_match = imx_pcie_ids,
  681. .ops = &imx_pcie_ops,
  682. .probe = imx_pcie_dm_probe,
  683. .remove = imx_pcie_dm_remove,
  684. .ofdata_to_platdata = imx_pcie_ofdata_to_platdata,
  685. .priv_auto_alloc_size = sizeof(struct imx_pcie_priv),
  686. .flags = DM_FLAG_OS_PREPARE,
  687. };
  688. #endif