pcie_ecam_generic.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Generic PCIE host provided by e.g. QEMU
  4. *
  5. * Heavily based on drivers/pci/pcie_xilinx.c
  6. *
  7. * Copyright (C) 2016 Imagination Technologies
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <pci.h>
  12. #include <asm/io.h>
  13. /**
  14. * struct generic_ecam_pcie - generic_ecam PCIe controller state
  15. * @cfg_base: The base address of memory mapped configuration space
  16. */
  17. struct generic_ecam_pcie {
  18. void *cfg_base;
  19. pci_size_t size;
  20. int first_busno;
  21. };
  22. /**
  23. * pci_generic_ecam_conf_address() - Calculate the address of a config access
  24. * @bus: Pointer to the PCI bus
  25. * @bdf: Identifies the PCIe device to access
  26. * @offset: The offset into the device's configuration space
  27. * @paddress: Pointer to the pointer to write the calculates address to
  28. *
  29. * Calculates the address that should be accessed to perform a PCIe
  30. * configuration space access for a given device identified by the PCIe
  31. * controller device @pcie and the bus, device & function numbers in @bdf. If
  32. * access to the device is not valid then the function will return an error
  33. * code. Otherwise the address to access will be written to the pointer pointed
  34. * to by @paddress.
  35. */
  36. static int pci_generic_ecam_conf_address(const struct udevice *bus,
  37. pci_dev_t bdf, uint offset,
  38. void **paddress)
  39. {
  40. struct generic_ecam_pcie *pcie = dev_get_priv(bus);
  41. void *addr;
  42. addr = pcie->cfg_base;
  43. addr += (PCI_BUS(bdf) - pcie->first_busno) << 20;
  44. addr += PCI_DEV(bdf) << 15;
  45. addr += PCI_FUNC(bdf) << 12;
  46. addr += offset;
  47. *paddress = addr;
  48. return 0;
  49. }
  50. static bool pci_generic_ecam_addr_valid(const struct udevice *bus,
  51. pci_dev_t bdf)
  52. {
  53. struct generic_ecam_pcie *pcie = dev_get_priv(bus);
  54. int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
  55. return (PCI_BUS(bdf) >= pcie->first_busno &&
  56. PCI_BUS(bdf) < pcie->first_busno + num_buses);
  57. }
  58. /**
  59. * pci_generic_ecam_read_config() - Read from configuration space
  60. * @bus: Pointer to the PCI bus
  61. * @bdf: Identifies the PCIe device to access
  62. * @offset: The offset into the device's configuration space
  63. * @valuep: A pointer at which to store the read value
  64. * @size: Indicates the size of access to perform
  65. *
  66. * Read a value of size @size from offset @offset within the configuration
  67. * space of the device identified by the bus, device & function numbers in @bdf
  68. * on the PCI bus @bus.
  69. */
  70. static int pci_generic_ecam_read_config(const struct udevice *bus,
  71. pci_dev_t bdf, uint offset,
  72. ulong *valuep, enum pci_size_t size)
  73. {
  74. if (!pci_generic_ecam_addr_valid(bus, bdf)) {
  75. *valuep = pci_get_ff(size);
  76. return 0;
  77. }
  78. return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address,
  79. bdf, offset, valuep, size);
  80. }
  81. /**
  82. * pci_generic_ecam_write_config() - Write to configuration space
  83. * @bus: Pointer to the PCI bus
  84. * @bdf: Identifies the PCIe device to access
  85. * @offset: The offset into the device's configuration space
  86. * @value: The value to write
  87. * @size: Indicates the size of access to perform
  88. *
  89. * Write the value @value of size @size from offset @offset within the
  90. * configuration space of the device identified by the bus, device & function
  91. * numbers in @bdf on the PCI bus @bus.
  92. */
  93. static int pci_generic_ecam_write_config(struct udevice *bus, pci_dev_t bdf,
  94. uint offset, ulong value,
  95. enum pci_size_t size)
  96. {
  97. if (!pci_generic_ecam_addr_valid(bus, bdf))
  98. return 0;
  99. return pci_generic_mmap_write_config(bus, pci_generic_ecam_conf_address,
  100. bdf, offset, value, size);
  101. }
  102. /**
  103. * pci_generic_ecam_ofdata_to_platdata() - Translate from DT to device state
  104. * @dev: A pointer to the device being operated on
  105. *
  106. * Translate relevant data from the device tree pertaining to device @dev into
  107. * state that the driver will later make use of. This state is stored in the
  108. * device's private data structure.
  109. *
  110. * Return: 0 on success, else -EINVAL
  111. */
  112. static int pci_generic_ecam_ofdata_to_platdata(struct udevice *dev)
  113. {
  114. struct generic_ecam_pcie *pcie = dev_get_priv(dev);
  115. struct fdt_resource reg_res;
  116. DECLARE_GLOBAL_DATA_PTR;
  117. int err;
  118. err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
  119. 0, &reg_res);
  120. if (err < 0) {
  121. pr_err("\"reg\" resource not found\n");
  122. return err;
  123. }
  124. pcie->size = fdt_resource_size(&reg_res);
  125. pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE);
  126. return 0;
  127. }
  128. static int pci_generic_ecam_probe(struct udevice *dev)
  129. {
  130. struct generic_ecam_pcie *pcie = dev_get_priv(dev);
  131. pcie->first_busno = dev->seq;
  132. return 0;
  133. }
  134. static const struct dm_pci_ops pci_generic_ecam_ops = {
  135. .read_config = pci_generic_ecam_read_config,
  136. .write_config = pci_generic_ecam_write_config,
  137. };
  138. static const struct udevice_id pci_generic_ecam_ids[] = {
  139. { .compatible = "pci-host-ecam-generic" },
  140. { }
  141. };
  142. U_BOOT_DRIVER(pci_generic_ecam) = {
  143. .name = "pci_generic_ecam",
  144. .id = UCLASS_PCI,
  145. .of_match = pci_generic_ecam_ids,
  146. .ops = &pci_generic_ecam_ops,
  147. .probe = pci_generic_ecam_probe,
  148. .ofdata_to_platdata = pci_generic_ecam_ofdata_to_platdata,
  149. .priv_auto_alloc_size = sizeof(struct generic_ecam_pcie),
  150. };