pci_tegra.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2010, CompuLab, Ltd.
  4. * Author: Mike Rapoport <mike@compulab.co.il>
  5. *
  6. * Based on NVIDIA PCIe driver
  7. * Copyright (c) 2008-2009, NVIDIA Corporation.
  8. *
  9. * Copyright (c) 2013-2014, NVIDIA Corporation.
  10. */
  11. #define pr_fmt(fmt) "tegra-pcie: " fmt
  12. #include <common.h>
  13. #include <clk.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <log.h>
  17. #include <malloc.h>
  18. #include <pci.h>
  19. #include <pci_tegra.h>
  20. #include <power-domain.h>
  21. #include <reset.h>
  22. #include <linux/delay.h>
  23. #include <asm/io.h>
  24. #include <asm/gpio.h>
  25. #include <linux/ioport.h>
  26. #include <linux/list.h>
  27. #ifndef CONFIG_TEGRA186
  28. #include <asm/arch/clock.h>
  29. #include <asm/arch/powergate.h>
  30. #include <asm/arch-tegra/xusb-padctl.h>
  31. #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
  32. #endif
  33. /*
  34. * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
  35. * should not be present. These are needed because newer Tegra SoCs support
  36. * only the standard clock/reset APIs, whereas older Tegra SoCs support only
  37. * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
  38. * fixed to implement the standard APIs, and all drivers converted to solely
  39. * use the new standard APIs, with no ifdefs.
  40. */
  41. #define AFI_AXI_BAR0_SZ 0x00
  42. #define AFI_AXI_BAR1_SZ 0x04
  43. #define AFI_AXI_BAR2_SZ 0x08
  44. #define AFI_AXI_BAR3_SZ 0x0c
  45. #define AFI_AXI_BAR4_SZ 0x10
  46. #define AFI_AXI_BAR5_SZ 0x14
  47. #define AFI_AXI_BAR0_START 0x18
  48. #define AFI_AXI_BAR1_START 0x1c
  49. #define AFI_AXI_BAR2_START 0x20
  50. #define AFI_AXI_BAR3_START 0x24
  51. #define AFI_AXI_BAR4_START 0x28
  52. #define AFI_AXI_BAR5_START 0x2c
  53. #define AFI_FPCI_BAR0 0x30
  54. #define AFI_FPCI_BAR1 0x34
  55. #define AFI_FPCI_BAR2 0x38
  56. #define AFI_FPCI_BAR3 0x3c
  57. #define AFI_FPCI_BAR4 0x40
  58. #define AFI_FPCI_BAR5 0x44
  59. #define AFI_CACHE_BAR0_SZ 0x48
  60. #define AFI_CACHE_BAR0_ST 0x4c
  61. #define AFI_CACHE_BAR1_SZ 0x50
  62. #define AFI_CACHE_BAR1_ST 0x54
  63. #define AFI_MSI_BAR_SZ 0x60
  64. #define AFI_MSI_FPCI_BAR_ST 0x64
  65. #define AFI_MSI_AXI_BAR_ST 0x68
  66. #define AFI_CONFIGURATION 0xac
  67. #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
  68. #define AFI_FPCI_ERROR_MASKS 0xb0
  69. #define AFI_INTR_MASK 0xb4
  70. #define AFI_INTR_MASK_INT_MASK (1 << 0)
  71. #define AFI_INTR_MASK_MSI_MASK (1 << 8)
  72. #define AFI_SM_INTR_ENABLE 0xc4
  73. #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
  74. #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
  75. #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
  76. #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
  77. #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
  78. #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
  79. #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
  80. #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
  81. #define AFI_AFI_INTR_ENABLE 0xc8
  82. #define AFI_INTR_EN_INI_SLVERR (1 << 0)
  83. #define AFI_INTR_EN_INI_DECERR (1 << 1)
  84. #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
  85. #define AFI_INTR_EN_TGT_DECERR (1 << 3)
  86. #define AFI_INTR_EN_TGT_WRERR (1 << 4)
  87. #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
  88. #define AFI_INTR_EN_AXI_DECERR (1 << 6)
  89. #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
  90. #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
  91. #define AFI_PCIE_CONFIG 0x0f8
  92. #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
  93. #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
  94. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
  95. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
  96. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
  97. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
  98. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
  99. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
  100. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
  101. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
  102. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20)
  103. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20)
  104. #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20)
  105. #define AFI_FUSE 0x104
  106. #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
  107. #define AFI_PEX0_CTRL 0x110
  108. #define AFI_PEX1_CTRL 0x118
  109. #define AFI_PEX2_CTRL 0x128
  110. #define AFI_PEX2_CTRL_T186 0x19c
  111. #define AFI_PEX_CTRL_RST (1 << 0)
  112. #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
  113. #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
  114. #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
  115. #define AFI_PLLE_CONTROL 0x160
  116. #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
  117. #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
  118. #define AFI_PEXBIAS_CTRL_0 0x168
  119. #define PADS_CTL_SEL 0x0000009C
  120. #define PADS_CTL 0x000000A0
  121. #define PADS_CTL_IDDQ_1L (1 << 0)
  122. #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
  123. #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
  124. #define PADS_PLL_CTL_TEGRA20 0x000000B8
  125. #define PADS_PLL_CTL_TEGRA30 0x000000B4
  126. #define PADS_PLL_CTL_RST_B4SM (0x1 << 1)
  127. #define PADS_PLL_CTL_LOCKDET (0x1 << 8)
  128. #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
  129. #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16)
  130. #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16)
  131. #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16)
  132. #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
  133. #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20)
  134. #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20)
  135. #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22)
  136. #define PADS_REFCLK_CFG0 0x000000C8
  137. #define PADS_REFCLK_CFG1 0x000000CC
  138. /*
  139. * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
  140. * entries, one entry per PCIe port. These field definitions and desired
  141. * values aren't in the TRM, but do come from NVIDIA.
  142. */
  143. #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
  144. #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
  145. #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
  146. #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
  147. #define RP_VEND_XP 0x00000F00
  148. #define RP_VEND_XP_DL_UP (1 << 30)
  149. #define RP_VEND_CTL2 0x00000FA8
  150. #define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
  151. #define RP_PRIV_MISC 0x00000FE0
  152. #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
  153. #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
  154. #define RP_LINK_CONTROL_STATUS 0x00000090
  155. #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
  156. #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
  157. enum tegra_pci_id {
  158. TEGRA20_PCIE,
  159. TEGRA30_PCIE,
  160. TEGRA124_PCIE,
  161. TEGRA210_PCIE,
  162. TEGRA186_PCIE,
  163. };
  164. struct tegra_pcie_port {
  165. struct tegra_pcie *pcie;
  166. struct fdt_resource regs;
  167. unsigned int num_lanes;
  168. unsigned int index;
  169. struct list_head list;
  170. };
  171. struct tegra_pcie_soc {
  172. unsigned int num_ports;
  173. unsigned long pads_pll_ctl;
  174. unsigned long tx_ref_sel;
  175. unsigned long afi_pex2_ctrl;
  176. u32 pads_refclk_cfg0;
  177. u32 pads_refclk_cfg1;
  178. bool has_pex_clkreq_en;
  179. bool has_pex_bias_ctrl;
  180. bool has_cml_clk;
  181. bool has_gen2;
  182. bool force_pca_enable;
  183. };
  184. struct tegra_pcie {
  185. struct resource pads;
  186. struct resource afi;
  187. struct resource cs;
  188. struct list_head ports;
  189. unsigned long xbar;
  190. const struct tegra_pcie_soc *soc;
  191. #ifdef CONFIG_TEGRA186
  192. struct clk clk_afi;
  193. struct clk clk_pex;
  194. struct reset_ctl reset_afi;
  195. struct reset_ctl reset_pex;
  196. struct reset_ctl reset_pcie_x;
  197. struct power_domain pwrdom;
  198. #else
  199. struct tegra_xusb_phy *phy;
  200. #endif
  201. };
  202. static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
  203. unsigned long offset)
  204. {
  205. writel(value, pcie->afi.start + offset);
  206. }
  207. static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset)
  208. {
  209. return readl(pcie->afi.start + offset);
  210. }
  211. static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
  212. unsigned long offset)
  213. {
  214. writel(value, pcie->pads.start + offset);
  215. }
  216. #ifndef CONFIG_TEGRA186
  217. static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)
  218. {
  219. return readl(pcie->pads.start + offset);
  220. }
  221. #endif
  222. static unsigned long rp_readl(struct tegra_pcie_port *port,
  223. unsigned long offset)
  224. {
  225. return readl(port->regs.start + offset);
  226. }
  227. static void rp_writel(struct tegra_pcie_port *port, unsigned long value,
  228. unsigned long offset)
  229. {
  230. writel(value, port->regs.start + offset);
  231. }
  232. static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where)
  233. {
  234. return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) |
  235. (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) |
  236. (where & 0xfc);
  237. }
  238. static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
  239. int where, unsigned long *address)
  240. {
  241. unsigned int bus = PCI_BUS(bdf);
  242. if (bus == 0) {
  243. unsigned int dev = PCI_DEV(bdf);
  244. struct tegra_pcie_port *port;
  245. list_for_each_entry(port, &pcie->ports, list) {
  246. if (port->index + 1 == dev) {
  247. *address = port->regs.start + (where & ~3);
  248. return 0;
  249. }
  250. }
  251. return -EFAULT;
  252. } else {
  253. #ifdef CONFIG_TEGRA20
  254. unsigned int dev = PCI_DEV(bdf);
  255. if (dev != 0)
  256. return -EFAULT;
  257. #endif
  258. *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);
  259. return 0;
  260. }
  261. }
  262. static int pci_tegra_read_config(const struct udevice *bus, pci_dev_t bdf,
  263. uint offset, ulong *valuep,
  264. enum pci_size_t size)
  265. {
  266. struct tegra_pcie *pcie = dev_get_priv(bus);
  267. unsigned long address, value;
  268. int err;
  269. err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
  270. if (err < 0) {
  271. value = 0xffffffff;
  272. goto done;
  273. }
  274. value = readl(address);
  275. #ifdef CONFIG_TEGRA20
  276. /* fixup root port class */
  277. if (PCI_BUS(bdf) == 0) {
  278. if ((offset & ~3) == PCI_CLASS_REVISION) {
  279. value &= ~0x00ff0000;
  280. value |= PCI_CLASS_BRIDGE_PCI << 16;
  281. }
  282. }
  283. #endif
  284. done:
  285. *valuep = pci_conv_32_to_size(value, offset, size);
  286. return 0;
  287. }
  288. static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf,
  289. uint offset, ulong value,
  290. enum pci_size_t size)
  291. {
  292. struct tegra_pcie *pcie = dev_get_priv(bus);
  293. unsigned long address;
  294. ulong old;
  295. int err;
  296. err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
  297. if (err < 0)
  298. return 0;
  299. old = readl(address);
  300. value = pci_conv_size_to_32(old, value, offset, size);
  301. writel(value, address);
  302. return 0;
  303. }
  304. static int tegra_pcie_port_parse_dt(ofnode node, struct tegra_pcie_port *port)
  305. {
  306. const u32 *addr;
  307. int len;
  308. addr = ofnode_get_property(node, "assigned-addresses", &len);
  309. if (!addr) {
  310. pr_err("property \"assigned-addresses\" not found");
  311. return -FDT_ERR_NOTFOUND;
  312. }
  313. port->regs.start = fdt32_to_cpu(addr[2]);
  314. port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]);
  315. return 0;
  316. }
  317. static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes,
  318. enum tegra_pci_id id, unsigned long *xbar)
  319. {
  320. switch (id) {
  321. case TEGRA20_PCIE:
  322. switch (lanes) {
  323. case 0x00000004:
  324. debug("single-mode configuration\n");
  325. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
  326. return 0;
  327. case 0x00000202:
  328. debug("dual-mode configuration\n");
  329. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
  330. return 0;
  331. }
  332. break;
  333. case TEGRA30_PCIE:
  334. switch (lanes) {
  335. case 0x00000204:
  336. debug("4x1, 2x1 configuration\n");
  337. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
  338. return 0;
  339. case 0x00020202:
  340. debug("2x3 configuration\n");
  341. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
  342. return 0;
  343. case 0x00010104:
  344. debug("4x1, 1x2 configuration\n");
  345. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
  346. return 0;
  347. }
  348. break;
  349. case TEGRA124_PCIE:
  350. case TEGRA210_PCIE:
  351. switch (lanes) {
  352. case 0x0000104:
  353. debug("4x1, 1x1 configuration\n");
  354. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
  355. return 0;
  356. case 0x0000102:
  357. debug("2x1, 1x1 configuration\n");
  358. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
  359. return 0;
  360. }
  361. break;
  362. case TEGRA186_PCIE:
  363. switch (lanes) {
  364. case 0x0010004:
  365. debug("x4 x1 configuration\n");
  366. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401;
  367. return 0;
  368. case 0x0010102:
  369. debug("x2 x1 x1 configuration\n");
  370. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211;
  371. return 0;
  372. case 0x0010101:
  373. debug("x1 x1 x1 configuration\n");
  374. *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111;
  375. return 0;
  376. }
  377. break;
  378. default:
  379. break;
  380. }
  381. return -FDT_ERR_NOTFOUND;
  382. }
  383. static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes)
  384. {
  385. struct fdt_pci_addr addr;
  386. int err;
  387. err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1);
  388. if (err < 0) {
  389. pr_err("failed to parse \"nvidia,num-lanes\" property");
  390. return err;
  391. }
  392. *lanes = err;
  393. err = ofnode_read_pci_addr(node, 0, "reg", &addr);
  394. if (err < 0) {
  395. pr_err("failed to parse \"reg\" property");
  396. return err;
  397. }
  398. *index = PCI_DEV(addr.phys_hi) - 1;
  399. return 0;
  400. }
  401. int __weak tegra_pcie_board_init(void)
  402. {
  403. return 0;
  404. }
  405. static int tegra_pcie_parse_dt(struct udevice *dev, enum tegra_pci_id id,
  406. struct tegra_pcie *pcie)
  407. {
  408. ofnode subnode;
  409. u32 lanes = 0;
  410. int err;
  411. err = dev_read_resource(dev, 0, &pcie->pads);
  412. if (err < 0) {
  413. pr_err("resource \"pads\" not found");
  414. return err;
  415. }
  416. err = dev_read_resource(dev, 1, &pcie->afi);
  417. if (err < 0) {
  418. pr_err("resource \"afi\" not found");
  419. return err;
  420. }
  421. err = dev_read_resource(dev, 2, &pcie->cs);
  422. if (err < 0) {
  423. pr_err("resource \"cs\" not found");
  424. return err;
  425. }
  426. err = tegra_pcie_board_init();
  427. if (err < 0) {
  428. pr_err("tegra_pcie_board_init() failed: err=%d", err);
  429. return err;
  430. }
  431. #ifndef CONFIG_TEGRA186
  432. pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
  433. if (pcie->phy) {
  434. err = tegra_xusb_phy_prepare(pcie->phy);
  435. if (err < 0) {
  436. pr_err("failed to prepare PHY: %d", err);
  437. return err;
  438. }
  439. }
  440. #endif
  441. dev_for_each_subnode(subnode, dev) {
  442. unsigned int index = 0, num_lanes = 0;
  443. struct tegra_pcie_port *port;
  444. err = tegra_pcie_parse_port_info(subnode, &index, &num_lanes);
  445. if (err < 0) {
  446. pr_err("failed to obtain root port info");
  447. continue;
  448. }
  449. lanes |= num_lanes << (index << 3);
  450. if (!ofnode_is_available(subnode))
  451. continue;
  452. port = malloc(sizeof(*port));
  453. if (!port)
  454. continue;
  455. memset(port, 0, sizeof(*port));
  456. port->num_lanes = num_lanes;
  457. port->index = index;
  458. err = tegra_pcie_port_parse_dt(subnode, port);
  459. if (err < 0) {
  460. free(port);
  461. continue;
  462. }
  463. list_add_tail(&port->list, &pcie->ports);
  464. port->pcie = pcie;
  465. }
  466. err = tegra_pcie_get_xbar_config(dev_ofnode(dev), lanes, id,
  467. &pcie->xbar);
  468. if (err < 0) {
  469. pr_err("invalid lane configuration");
  470. return err;
  471. }
  472. return 0;
  473. }
  474. #ifdef CONFIG_TEGRA186
  475. static int tegra_pcie_power_on(struct tegra_pcie *pcie)
  476. {
  477. int ret;
  478. ret = power_domain_on(&pcie->pwrdom);
  479. if (ret) {
  480. pr_err("power_domain_on() failed: %d\n", ret);
  481. return ret;
  482. }
  483. ret = clk_enable(&pcie->clk_afi);
  484. if (ret) {
  485. pr_err("clk_enable(afi) failed: %d\n", ret);
  486. return ret;
  487. }
  488. ret = clk_enable(&pcie->clk_pex);
  489. if (ret) {
  490. pr_err("clk_enable(pex) failed: %d\n", ret);
  491. return ret;
  492. }
  493. ret = reset_deassert(&pcie->reset_afi);
  494. if (ret) {
  495. pr_err("reset_deassert(afi) failed: %d\n", ret);
  496. return ret;
  497. }
  498. ret = reset_deassert(&pcie->reset_pex);
  499. if (ret) {
  500. pr_err("reset_deassert(pex) failed: %d\n", ret);
  501. return ret;
  502. }
  503. return 0;
  504. }
  505. #else
  506. static int tegra_pcie_power_on(struct tegra_pcie *pcie)
  507. {
  508. const struct tegra_pcie_soc *soc = pcie->soc;
  509. unsigned long value;
  510. int err;
  511. /* reset PCIEXCLK logic, AFI controller and PCIe controller */
  512. reset_set_enable(PERIPH_ID_PCIEXCLK, 1);
  513. reset_set_enable(PERIPH_ID_AFI, 1);
  514. reset_set_enable(PERIPH_ID_PCIE, 1);
  515. err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
  516. if (err < 0) {
  517. pr_err("failed to power off PCIe partition: %d", err);
  518. return err;
  519. }
  520. err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
  521. PERIPH_ID_PCIE);
  522. if (err < 0) {
  523. pr_err("failed to power up PCIe partition: %d", err);
  524. return err;
  525. }
  526. /* take AFI controller out of reset */
  527. reset_set_enable(PERIPH_ID_AFI, 0);
  528. /* enable AFI clock */
  529. clock_enable(PERIPH_ID_AFI);
  530. if (soc->has_cml_clk) {
  531. /* enable CML clock */
  532. value = readl(NV_PA_CLK_RST_BASE + 0x48c);
  533. value |= (1 << 0);
  534. value &= ~(1 << 1);
  535. writel(value, NV_PA_CLK_RST_BASE + 0x48c);
  536. }
  537. err = tegra_plle_enable();
  538. if (err < 0) {
  539. pr_err("failed to enable PLLE: %d\n", err);
  540. return err;
  541. }
  542. return 0;
  543. }
  544. static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
  545. {
  546. const struct tegra_pcie_soc *soc = pcie->soc;
  547. unsigned long start = get_timer(0);
  548. u32 value;
  549. while (get_timer(start) < timeout) {
  550. value = pads_readl(pcie, soc->pads_pll_ctl);
  551. if (value & PADS_PLL_CTL_LOCKDET)
  552. return 0;
  553. }
  554. return -ETIMEDOUT;
  555. }
  556. static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
  557. {
  558. const struct tegra_pcie_soc *soc = pcie->soc;
  559. u32 value;
  560. int err;
  561. /* initialize internal PHY, enable up to 16 PCIe lanes */
  562. pads_writel(pcie, 0, PADS_CTL_SEL);
  563. /* override IDDQ to 1 on all 4 lanes */
  564. value = pads_readl(pcie, PADS_CTL);
  565. value |= PADS_CTL_IDDQ_1L;
  566. pads_writel(pcie, value, PADS_CTL);
  567. /*
  568. * Set up PHY PLL inputs select PLLE output as refclock, set TX
  569. * ref sel to div10 (not div5).
  570. */
  571. value = pads_readl(pcie, soc->pads_pll_ctl);
  572. value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
  573. value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
  574. pads_writel(pcie, value, soc->pads_pll_ctl);
  575. /* reset PLL */
  576. value = pads_readl(pcie, soc->pads_pll_ctl);
  577. value &= ~PADS_PLL_CTL_RST_B4SM;
  578. pads_writel(pcie, value, soc->pads_pll_ctl);
  579. udelay(20);
  580. /* take PLL out of reset */
  581. value = pads_readl(pcie, soc->pads_pll_ctl);
  582. value |= PADS_PLL_CTL_RST_B4SM;
  583. pads_writel(pcie, value, soc->pads_pll_ctl);
  584. /* wait for the PLL to lock */
  585. err = tegra_pcie_pll_wait(pcie, 500);
  586. if (err < 0) {
  587. pr_err("PLL failed to lock: %d", err);
  588. return err;
  589. }
  590. /* turn off IDDQ override */
  591. value = pads_readl(pcie, PADS_CTL);
  592. value &= ~PADS_CTL_IDDQ_1L;
  593. pads_writel(pcie, value, PADS_CTL);
  594. /* enable TX/RX data */
  595. value = pads_readl(pcie, PADS_CTL);
  596. value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
  597. pads_writel(pcie, value, PADS_CTL);
  598. return 0;
  599. }
  600. #endif
  601. static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
  602. {
  603. const struct tegra_pcie_soc *soc = pcie->soc;
  604. struct tegra_pcie_port *port;
  605. u32 value;
  606. int err;
  607. #ifdef CONFIG_TEGRA186
  608. {
  609. #else
  610. if (pcie->phy) {
  611. #endif
  612. value = afi_readl(pcie, AFI_PLLE_CONTROL);
  613. value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
  614. value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
  615. afi_writel(pcie, value, AFI_PLLE_CONTROL);
  616. }
  617. if (soc->has_pex_bias_ctrl)
  618. afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
  619. value = afi_readl(pcie, AFI_PCIE_CONFIG);
  620. value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
  621. value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
  622. list_for_each_entry(port, &pcie->ports, list)
  623. value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
  624. afi_writel(pcie, value, AFI_PCIE_CONFIG);
  625. value = afi_readl(pcie, AFI_FUSE);
  626. if (soc->has_gen2)
  627. value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
  628. else
  629. value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
  630. afi_writel(pcie, value, AFI_FUSE);
  631. #ifndef CONFIG_TEGRA186
  632. if (pcie->phy)
  633. err = tegra_xusb_phy_enable(pcie->phy);
  634. else
  635. err = tegra_pcie_phy_enable(pcie);
  636. if (err < 0) {
  637. pr_err("failed to power on PHY: %d\n", err);
  638. return err;
  639. }
  640. #endif
  641. /* take the PCIEXCLK logic out of reset */
  642. #ifdef CONFIG_TEGRA186
  643. err = reset_deassert(&pcie->reset_pcie_x);
  644. if (err) {
  645. pr_err("reset_deassert(pcie_x) failed: %d\n", err);
  646. return err;
  647. }
  648. #else
  649. reset_set_enable(PERIPH_ID_PCIEXCLK, 0);
  650. #endif
  651. /* finally enable PCIe */
  652. value = afi_readl(pcie, AFI_CONFIGURATION);
  653. value |= AFI_CONFIGURATION_EN_FPCI;
  654. afi_writel(pcie, value, AFI_CONFIGURATION);
  655. /* disable all interrupts */
  656. afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE);
  657. afi_writel(pcie, 0, AFI_SM_INTR_ENABLE);
  658. afi_writel(pcie, 0, AFI_INTR_MASK);
  659. afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
  660. return 0;
  661. }
  662. static int tegra_pcie_setup_translations(struct udevice *bus)
  663. {
  664. struct tegra_pcie *pcie = dev_get_priv(bus);
  665. unsigned long fpci, axi, size;
  666. struct pci_region *io, *mem, *pref;
  667. int count;
  668. /* BAR 0: type 1 extended configuration space */
  669. fpci = 0xfe100000;
  670. size = resource_size(&pcie->cs);
  671. axi = pcie->cs.start;
  672. afi_writel(pcie, axi, AFI_AXI_BAR0_START);
  673. afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
  674. afi_writel(pcie, fpci, AFI_FPCI_BAR0);
  675. count = pci_get_regions(bus, &io, &mem, &pref);
  676. if (count != 3)
  677. return -EINVAL;
  678. /* BAR 1: downstream I/O */
  679. fpci = 0xfdfc0000;
  680. size = io->size;
  681. axi = io->phys_start;
  682. afi_writel(pcie, axi, AFI_AXI_BAR1_START);
  683. afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
  684. afi_writel(pcie, fpci, AFI_FPCI_BAR1);
  685. /* BAR 2: prefetchable memory */
  686. fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
  687. size = pref->size;
  688. axi = pref->phys_start;
  689. afi_writel(pcie, axi, AFI_AXI_BAR2_START);
  690. afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
  691. afi_writel(pcie, fpci, AFI_FPCI_BAR2);
  692. /* BAR 3: non-prefetchable memory */
  693. fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
  694. size = mem->size;
  695. axi = mem->phys_start;
  696. afi_writel(pcie, axi, AFI_AXI_BAR3_START);
  697. afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
  698. afi_writel(pcie, fpci, AFI_FPCI_BAR3);
  699. /* NULL out the remaining BARs as they are not used */
  700. afi_writel(pcie, 0, AFI_AXI_BAR4_START);
  701. afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
  702. afi_writel(pcie, 0, AFI_FPCI_BAR4);
  703. afi_writel(pcie, 0, AFI_AXI_BAR5_START);
  704. afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
  705. afi_writel(pcie, 0, AFI_FPCI_BAR5);
  706. /* map all upstream transactions as uncached */
  707. afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);
  708. afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
  709. afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
  710. afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
  711. /* MSI translations are setup only when needed */
  712. afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
  713. afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
  714. afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
  715. afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
  716. return 0;
  717. }
  718. static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
  719. {
  720. unsigned long ret = 0;
  721. switch (port->index) {
  722. case 0:
  723. ret = AFI_PEX0_CTRL;
  724. break;
  725. case 1:
  726. ret = AFI_PEX1_CTRL;
  727. break;
  728. case 2:
  729. ret = port->pcie->soc->afi_pex2_ctrl;
  730. break;
  731. }
  732. return ret;
  733. }
  734. void tegra_pcie_port_reset(struct tegra_pcie_port *port)
  735. {
  736. unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
  737. unsigned long value;
  738. /* pulse reset signel */
  739. value = afi_readl(port->pcie, ctrl);
  740. value &= ~AFI_PEX_CTRL_RST;
  741. afi_writel(port->pcie, value, ctrl);
  742. udelay(2000);
  743. value = afi_readl(port->pcie, ctrl);
  744. value |= AFI_PEX_CTRL_RST;
  745. afi_writel(port->pcie, value, ctrl);
  746. }
  747. int tegra_pcie_port_index_of_port(struct tegra_pcie_port *port)
  748. {
  749. return port->index;
  750. }
  751. void __weak tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
  752. {
  753. tegra_pcie_port_reset(port);
  754. }
  755. static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
  756. {
  757. struct tegra_pcie *pcie = port->pcie;
  758. const struct tegra_pcie_soc *soc = pcie->soc;
  759. unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
  760. unsigned long value;
  761. /* enable reference clock */
  762. value = afi_readl(pcie, ctrl);
  763. value |= AFI_PEX_CTRL_REFCLK_EN;
  764. if (pcie->soc->has_pex_clkreq_en)
  765. value |= AFI_PEX_CTRL_CLKREQ_EN;
  766. value |= AFI_PEX_CTRL_OVERRIDE_EN;
  767. afi_writel(pcie, value, ctrl);
  768. tegra_pcie_board_port_reset(port);
  769. if (soc->force_pca_enable) {
  770. value = rp_readl(port, RP_VEND_CTL2);
  771. value |= RP_VEND_CTL2_PCA_ENABLE;
  772. rp_writel(port, value, RP_VEND_CTL2);
  773. }
  774. /* configure the reference clock driver */
  775. pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
  776. if (soc->num_ports > 2)
  777. pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
  778. }
  779. static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
  780. {
  781. unsigned int retries = 3;
  782. unsigned long value;
  783. value = rp_readl(port, RP_PRIV_MISC);
  784. value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
  785. value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
  786. rp_writel(port, value, RP_PRIV_MISC);
  787. do {
  788. unsigned int timeout = 200;
  789. do {
  790. value = rp_readl(port, RP_VEND_XP);
  791. if (value & RP_VEND_XP_DL_UP)
  792. break;
  793. udelay(2000);
  794. } while (--timeout);
  795. if (!timeout) {
  796. debug("link %u down, retrying\n", port->index);
  797. goto retry;
  798. }
  799. timeout = 200;
  800. do {
  801. value = rp_readl(port, RP_LINK_CONTROL_STATUS);
  802. if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
  803. return true;
  804. udelay(2000);
  805. } while (--timeout);
  806. retry:
  807. tegra_pcie_board_port_reset(port);
  808. } while (--retries);
  809. return false;
  810. }
  811. static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
  812. {
  813. unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
  814. unsigned long value;
  815. /* assert port reset */
  816. value = afi_readl(port->pcie, ctrl);
  817. value &= ~AFI_PEX_CTRL_RST;
  818. afi_writel(port->pcie, value, ctrl);
  819. /* disable reference clock */
  820. value = afi_readl(port->pcie, ctrl);
  821. value &= ~AFI_PEX_CTRL_REFCLK_EN;
  822. afi_writel(port->pcie, value, ctrl);
  823. }
  824. static void tegra_pcie_port_free(struct tegra_pcie_port *port)
  825. {
  826. list_del(&port->list);
  827. free(port);
  828. }
  829. static int tegra_pcie_enable(struct tegra_pcie *pcie)
  830. {
  831. struct tegra_pcie_port *port, *tmp;
  832. list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
  833. debug("probing port %u, using %u lanes\n", port->index,
  834. port->num_lanes);
  835. tegra_pcie_port_enable(port);
  836. if (tegra_pcie_port_check_link(port))
  837. continue;
  838. debug("link %u down, ignoring\n", port->index);
  839. tegra_pcie_port_disable(port);
  840. tegra_pcie_port_free(port);
  841. }
  842. return 0;
  843. }
  844. static const struct tegra_pcie_soc pci_tegra_soc[] = {
  845. [TEGRA20_PCIE] = {
  846. .num_ports = 2,
  847. .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
  848. .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
  849. .pads_refclk_cfg0 = 0xfa5cfa5c,
  850. .has_pex_clkreq_en = false,
  851. .has_pex_bias_ctrl = false,
  852. .has_cml_clk = false,
  853. .has_gen2 = false,
  854. },
  855. [TEGRA30_PCIE] = {
  856. .num_ports = 3,
  857. .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
  858. .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
  859. .afi_pex2_ctrl = AFI_PEX2_CTRL,
  860. .pads_refclk_cfg0 = 0xfa5cfa5c,
  861. .pads_refclk_cfg1 = 0xfa5cfa5c,
  862. .has_pex_clkreq_en = true,
  863. .has_pex_bias_ctrl = true,
  864. .has_cml_clk = true,
  865. .has_gen2 = false,
  866. },
  867. [TEGRA124_PCIE] = {
  868. .num_ports = 2,
  869. .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
  870. .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
  871. .pads_refclk_cfg0 = 0x44ac44ac,
  872. .has_pex_clkreq_en = true,
  873. .has_pex_bias_ctrl = true,
  874. .has_cml_clk = true,
  875. .has_gen2 = true,
  876. },
  877. [TEGRA210_PCIE] = {
  878. .num_ports = 2,
  879. .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
  880. .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
  881. .pads_refclk_cfg0 = 0x90b890b8,
  882. .has_pex_clkreq_en = true,
  883. .has_pex_bias_ctrl = true,
  884. .has_cml_clk = true,
  885. .has_gen2 = true,
  886. .force_pca_enable = true,
  887. },
  888. [TEGRA186_PCIE] = {
  889. .num_ports = 3,
  890. .afi_pex2_ctrl = AFI_PEX2_CTRL_T186,
  891. .pads_refclk_cfg0 = 0x80b880b8,
  892. .pads_refclk_cfg1 = 0x000480b8,
  893. .has_pex_clkreq_en = true,
  894. .has_pex_bias_ctrl = true,
  895. .has_gen2 = true,
  896. },
  897. };
  898. static int pci_tegra_ofdata_to_platdata(struct udevice *dev)
  899. {
  900. struct tegra_pcie *pcie = dev_get_priv(dev);
  901. enum tegra_pci_id id;
  902. id = dev_get_driver_data(dev);
  903. pcie->soc = &pci_tegra_soc[id];
  904. INIT_LIST_HEAD(&pcie->ports);
  905. if (tegra_pcie_parse_dt(dev, id, pcie))
  906. return -EINVAL;
  907. return 0;
  908. }
  909. static int pci_tegra_probe(struct udevice *dev)
  910. {
  911. struct tegra_pcie *pcie = dev_get_priv(dev);
  912. int err;
  913. #ifdef CONFIG_TEGRA186
  914. err = clk_get_by_name(dev, "afi", &pcie->clk_afi);
  915. if (err) {
  916. debug("clk_get_by_name(afi) failed: %d\n", err);
  917. return err;
  918. }
  919. err = clk_get_by_name(dev, "pex", &pcie->clk_pex);
  920. if (err) {
  921. debug("clk_get_by_name(pex) failed: %d\n", err);
  922. return err;
  923. }
  924. err = reset_get_by_name(dev, "afi", &pcie->reset_afi);
  925. if (err) {
  926. debug("reset_get_by_name(afi) failed: %d\n", err);
  927. return err;
  928. }
  929. err = reset_get_by_name(dev, "pex", &pcie->reset_pex);
  930. if (err) {
  931. debug("reset_get_by_name(pex) failed: %d\n", err);
  932. return err;
  933. }
  934. err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x);
  935. if (err) {
  936. debug("reset_get_by_name(pcie_x) failed: %d\n", err);
  937. return err;
  938. }
  939. err = power_domain_get(dev, &pcie->pwrdom);
  940. if (err) {
  941. debug("power_domain_get() failed: %d\n", err);
  942. return err;
  943. }
  944. #endif
  945. err = tegra_pcie_power_on(pcie);
  946. if (err < 0) {
  947. pr_err("failed to power on");
  948. return err;
  949. }
  950. err = tegra_pcie_enable_controller(pcie);
  951. if (err < 0) {
  952. pr_err("failed to enable controller");
  953. return err;
  954. }
  955. err = tegra_pcie_setup_translations(dev);
  956. if (err < 0) {
  957. pr_err("failed to decode ranges");
  958. return err;
  959. }
  960. err = tegra_pcie_enable(pcie);
  961. if (err < 0) {
  962. pr_err("failed to enable PCIe");
  963. return err;
  964. }
  965. return 0;
  966. }
  967. static const struct dm_pci_ops pci_tegra_ops = {
  968. .read_config = pci_tegra_read_config,
  969. .write_config = pci_tegra_write_config,
  970. };
  971. static const struct udevice_id pci_tegra_ids[] = {
  972. { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE },
  973. { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
  974. { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
  975. { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
  976. { .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE },
  977. { }
  978. };
  979. U_BOOT_DRIVER(pci_tegra) = {
  980. .name = "pci_tegra",
  981. .id = UCLASS_PCI,
  982. .of_match = pci_tegra_ids,
  983. .ops = &pci_tegra_ops,
  984. .ofdata_to_platdata = pci_tegra_ofdata_to_platdata,
  985. .probe = pci_tegra_probe,
  986. .priv_auto_alloc_size = sizeof(struct tegra_pcie),
  987. };