pci_msc01.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Imagination Technologies
  4. * Author: Paul Burton <paul.burton@mips.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <msc01.h>
  9. #include <pci.h>
  10. #include <pci_msc01.h>
  11. #include <asm/io.h>
  12. #define PCI_ACCESS_READ 0
  13. #define PCI_ACCESS_WRITE 1
  14. struct msc01_pci_controller {
  15. struct pci_controller hose;
  16. void *base;
  17. };
  18. static inline struct msc01_pci_controller *
  19. hose_to_msc01(struct pci_controller *hose)
  20. {
  21. return container_of(hose, struct msc01_pci_controller, hose);
  22. }
  23. static int msc01_config_access(struct msc01_pci_controller *msc01,
  24. unsigned char access_type, pci_dev_t bdf,
  25. int where, u32 *data)
  26. {
  27. const u32 aborts = MSC01_PCI_INTSTAT_MA_MSK | MSC01_PCI_INTSTAT_TA_MSK;
  28. void *intstat = msc01->base + MSC01_PCI_INTSTAT_OFS;
  29. void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS;
  30. unsigned int bus = PCI_BUS(bdf);
  31. unsigned int dev = PCI_DEV(bdf);
  32. unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
  33. /* clear abort status */
  34. __raw_writel(aborts, intstat);
  35. /* setup address */
  36. __raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) |
  37. (dev << MSC01_PCI_CFGADDR_DNUM_SHF) |
  38. (devfn << MSC01_PCI_CFGADDR_FNUM_SHF) |
  39. ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF),
  40. msc01->base + MSC01_PCI_CFGADDR_OFS);
  41. /* perform access */
  42. if (access_type == PCI_ACCESS_WRITE)
  43. __raw_writel(*data, cfgdata);
  44. else
  45. *data = __raw_readl(cfgdata);
  46. /* check for aborts */
  47. if (__raw_readl(intstat) & aborts) {
  48. /* clear abort status */
  49. __raw_writel(aborts, intstat);
  50. return -1;
  51. }
  52. return 0;
  53. }
  54. static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
  55. int where, u32 *value)
  56. {
  57. struct msc01_pci_controller *msc01 = hose_to_msc01(hose);
  58. *value = 0xffffffff;
  59. return msc01_config_access(msc01, PCI_ACCESS_READ, dev, where, value);
  60. }
  61. static int msc01_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
  62. int where, u32 value)
  63. {
  64. struct msc01_pci_controller *gt = hose_to_msc01(hose);
  65. u32 data = value;
  66. return msc01_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
  67. }
  68. void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys,
  69. unsigned long sys_size, unsigned long mem_bus,
  70. unsigned long mem_phys, unsigned long mem_size,
  71. unsigned long io_bus, unsigned long io_phys,
  72. unsigned long io_size)
  73. {
  74. static struct msc01_pci_controller global_msc01;
  75. struct msc01_pci_controller *msc01;
  76. struct pci_controller *hose;
  77. msc01 = &global_msc01;
  78. msc01->base = base;
  79. hose = &msc01->hose;
  80. hose->first_busno = 0;
  81. hose->last_busno = 0;
  82. /* System memory space */
  83. pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
  84. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  85. /* PCI memory space */
  86. pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
  87. PCI_REGION_MEM);
  88. /* PCI I/O space */
  89. pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
  90. PCI_REGION_IO);
  91. hose->region_count = 3;
  92. pci_set_ops(hose,
  93. pci_hose_read_config_byte_via_dword,
  94. pci_hose_read_config_word_via_dword,
  95. msc01_read_config_dword,
  96. pci_hose_write_config_byte_via_dword,
  97. pci_hose_write_config_word_via_dword,
  98. msc01_write_config_dword);
  99. pci_register_hose(hose);
  100. hose->last_busno = pci_hose_scan(hose);
  101. }