pci_gt64120.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
  4. *
  5. * Based on the Linux implementation.
  6. * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
  7. * Authors: Carsten Langgaard <carstenl@mips.com>
  8. * Maciej W. Rozycki <macro@mips.com>
  9. */
  10. #include <common.h>
  11. #include <gt64120.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <pci.h>
  15. #include <pci_gt64120.h>
  16. #include <asm/io.h>
  17. #define PCI_ACCESS_READ 0
  18. #define PCI_ACCESS_WRITE 1
  19. struct gt64120_regs {
  20. u8 unused_000[0xc18];
  21. u32 intrcause;
  22. u8 unused_c1c[0x0dc];
  23. u32 pci0_cfgaddr;
  24. u32 pci0_cfgdata;
  25. };
  26. struct gt64120_pci_controller {
  27. struct pci_controller hose;
  28. struct gt64120_regs *regs;
  29. };
  30. static inline struct gt64120_pci_controller *
  31. hose_to_gt64120(struct pci_controller *hose)
  32. {
  33. return container_of(hose, struct gt64120_pci_controller, hose);
  34. }
  35. #define GT_INTRCAUSE_ABORT_BITS \
  36. (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)
  37. static int gt_config_access(struct gt64120_pci_controller *gt,
  38. unsigned char access_type, pci_dev_t bdf,
  39. int where, u32 *data)
  40. {
  41. unsigned int bus = PCI_BUS(bdf);
  42. unsigned int dev = PCI_DEV(bdf);
  43. unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
  44. u32 intr;
  45. u32 addr;
  46. u32 val;
  47. if (bus == 0 && dev >= 31) {
  48. /* Because of a bug in the galileo (for slot 31). */
  49. return -1;
  50. }
  51. if (access_type == PCI_ACCESS_WRITE)
  52. debug("PCI WR %02x:%02x.%x reg:%02d data:%08x\n",
  53. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
  54. /* Clear cause register bits */
  55. writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
  56. addr = GT_PCI0_CFGADDR_CONFIGEN_BIT;
  57. addr |= bus << GT_PCI0_CFGADDR_BUSNUM_SHF;
  58. addr |= devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF;
  59. addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF;
  60. /* Setup address */
  61. writel(addr, &gt->regs->pci0_cfgaddr);
  62. if (access_type == PCI_ACCESS_WRITE) {
  63. if (bus == 0 && dev == 0) {
  64. /*
  65. * The Galileo system controller is acting
  66. * differently than other devices.
  67. */
  68. val = *data;
  69. } else {
  70. val = cpu_to_le32(*data);
  71. }
  72. writel(val, &gt->regs->pci0_cfgdata);
  73. } else {
  74. val = readl(&gt->regs->pci0_cfgdata);
  75. if (bus == 0 && dev == 0) {
  76. /*
  77. * The Galileo system controller is acting
  78. * differently than other devices.
  79. */
  80. *data = val;
  81. } else {
  82. *data = le32_to_cpu(val);
  83. }
  84. }
  85. /* Check for master or target abort */
  86. intr = readl(&gt->regs->intrcause);
  87. if (intr & GT_INTRCAUSE_ABORT_BITS) {
  88. /* Error occurred, clear abort bits */
  89. writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
  90. return -1;
  91. }
  92. if (access_type == PCI_ACCESS_READ)
  93. debug("PCI RD %02x:%02x.%x reg:%02d data:%08x\n",
  94. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
  95. return 0;
  96. }
  97. static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
  98. int where, u32 *value)
  99. {
  100. struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
  101. *value = 0xffffffff;
  102. return gt_config_access(gt, PCI_ACCESS_READ, dev, where, value);
  103. }
  104. static int gt_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
  105. int where, u32 value)
  106. {
  107. struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
  108. u32 data = value;
  109. return gt_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
  110. }
  111. void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
  112. unsigned long sys_size, unsigned long mem_bus,
  113. unsigned long mem_phys, unsigned long mem_size,
  114. unsigned long io_bus, unsigned long io_phys,
  115. unsigned long io_size)
  116. {
  117. static struct gt64120_pci_controller global_gt;
  118. struct gt64120_pci_controller *gt;
  119. struct pci_controller *hose;
  120. gt = &global_gt;
  121. gt->regs = regs;
  122. hose = &gt->hose;
  123. hose->first_busno = 0;
  124. hose->last_busno = 0;
  125. /* System memory space */
  126. pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
  127. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  128. /* PCI memory space */
  129. pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
  130. PCI_REGION_MEM);
  131. /* PCI I/O space */
  132. pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
  133. PCI_REGION_IO);
  134. hose->region_count = 3;
  135. pci_set_ops(hose,
  136. pci_hose_read_config_byte_via_dword,
  137. pci_hose_read_config_word_via_dword,
  138. gt_read_config_dword,
  139. pci_hose_write_config_byte_via_dword,
  140. pci_hose_write_config_word_via_dword,
  141. gt_write_config_dword);
  142. pci_register_hose(hose);
  143. hose->last_busno = pci_hose_scan(hose);
  144. }