pci_auto_old.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * PCI autoconfiguration library (legacy version, do not change)
  4. *
  5. * Author: Matt Porter <mporter@mvista.com>
  6. *
  7. * Copyright 2000 MontaVista Software Inc.
  8. */
  9. #include <common.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <pci.h>
  13. /*
  14. * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
  15. * and change pci_auto.c.
  16. */
  17. /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  18. #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  19. #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
  20. #endif
  21. /*
  22. *
  23. */
  24. void pciauto_setup_device(struct pci_controller *hose,
  25. pci_dev_t dev, int bars_num,
  26. struct pci_region *mem,
  27. struct pci_region *prefetch,
  28. struct pci_region *io)
  29. {
  30. u32 bar_response;
  31. pci_size_t bar_size;
  32. u16 cmdstat = 0;
  33. int bar, bar_nr = 0;
  34. #ifndef CONFIG_PCI_ENUM_ONLY
  35. u8 header_type;
  36. int rom_addr;
  37. pci_addr_t bar_value;
  38. struct pci_region *bar_res;
  39. int found_mem64 = 0;
  40. #endif
  41. u16 class;
  42. pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
  43. cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
  44. for (bar = PCI_BASE_ADDRESS_0;
  45. bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
  46. /* Tickle the BAR and get the response */
  47. #ifndef CONFIG_PCI_ENUM_ONLY
  48. pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
  49. #endif
  50. pci_hose_read_config_dword(hose, dev, bar, &bar_response);
  51. /* If BAR is not implemented go to the next BAR */
  52. if (!bar_response)
  53. continue;
  54. #ifndef CONFIG_PCI_ENUM_ONLY
  55. found_mem64 = 0;
  56. #endif
  57. /* Check the BAR type and set our address mask */
  58. if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  59. bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
  60. & 0xffff) + 1;
  61. #ifndef CONFIG_PCI_ENUM_ONLY
  62. bar_res = io;
  63. #endif
  64. debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
  65. bar_nr, (unsigned long long)bar_size);
  66. } else {
  67. if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  68. PCI_BASE_ADDRESS_MEM_TYPE_64) {
  69. u32 bar_response_upper;
  70. u64 bar64;
  71. #ifndef CONFIG_PCI_ENUM_ONLY
  72. pci_hose_write_config_dword(hose, dev, bar + 4,
  73. 0xffffffff);
  74. #endif
  75. pci_hose_read_config_dword(hose, dev, bar + 4,
  76. &bar_response_upper);
  77. bar64 = ((u64)bar_response_upper << 32) | bar_response;
  78. bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
  79. #ifndef CONFIG_PCI_ENUM_ONLY
  80. found_mem64 = 1;
  81. #endif
  82. } else {
  83. bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
  84. }
  85. #ifndef CONFIG_PCI_ENUM_ONLY
  86. if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
  87. bar_res = prefetch;
  88. else
  89. bar_res = mem;
  90. debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
  91. bar_nr, bar_res == prefetch ? "Prf" : "Mem",
  92. (unsigned long long)bar_size);
  93. #endif
  94. }
  95. #ifndef CONFIG_PCI_ENUM_ONLY
  96. if (pciauto_region_allocate(bar_res, bar_size,
  97. &bar_value, found_mem64) == 0) {
  98. /* Write it out and update our limit */
  99. pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
  100. if (found_mem64) {
  101. bar += 4;
  102. #ifdef CONFIG_SYS_PCI_64BIT
  103. pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
  104. #else
  105. /*
  106. * If we are a 64-bit decoder then increment to the
  107. * upper 32 bits of the bar and force it to locate
  108. * in the lower 4GB of memory.
  109. */
  110. pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
  111. #endif
  112. }
  113. }
  114. #endif
  115. cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
  116. PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
  117. debug("\n");
  118. bar_nr++;
  119. }
  120. #ifndef CONFIG_PCI_ENUM_ONLY
  121. /* Configure the expansion ROM address */
  122. pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
  123. header_type &= 0x7f;
  124. if (header_type != PCI_HEADER_TYPE_CARDBUS) {
  125. rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
  126. PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
  127. pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
  128. pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
  129. if (bar_response) {
  130. bar_size = -(bar_response & ~1);
  131. debug("PCI Autoconfig: ROM, size=%#x, ",
  132. (unsigned int)bar_size);
  133. if (pciauto_region_allocate(mem, bar_size,
  134. &bar_value, false) == 0) {
  135. pci_hose_write_config_dword(hose, dev, rom_addr,
  136. bar_value);
  137. }
  138. cmdstat |= PCI_COMMAND_MEMORY;
  139. debug("\n");
  140. }
  141. }
  142. #endif
  143. /* PCI_COMMAND_IO must be set for VGA device */
  144. pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
  145. if (class == PCI_CLASS_DISPLAY_VGA)
  146. cmdstat |= PCI_COMMAND_IO;
  147. pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
  148. pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
  149. CONFIG_SYS_PCI_CACHE_LINE_SIZE);
  150. pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
  151. }
  152. void pciauto_prescan_setup_bridge(struct pci_controller *hose,
  153. pci_dev_t dev, int sub_bus)
  154. {
  155. struct pci_region *pci_mem;
  156. struct pci_region *pci_prefetch;
  157. struct pci_region *pci_io;
  158. u16 cmdstat, prefechable_64;
  159. pci_mem = hose->pci_mem;
  160. pci_prefetch = hose->pci_prefetch;
  161. pci_io = hose->pci_io;
  162. pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
  163. pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
  164. &prefechable_64);
  165. prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
  166. /* Configure bus number registers */
  167. pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
  168. PCI_BUS(dev) - hose->first_busno);
  169. pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
  170. sub_bus - hose->first_busno);
  171. pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
  172. if (pci_mem) {
  173. /* Round memory allocator to 1MB boundary */
  174. pciauto_region_align(pci_mem, 0x100000);
  175. /* Set up memory and I/O filter limits, assume 32-bit I/O space */
  176. pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
  177. (pci_mem->bus_lower & 0xfff00000) >> 16);
  178. cmdstat |= PCI_COMMAND_MEMORY;
  179. }
  180. if (pci_prefetch) {
  181. /* Round memory allocator to 1MB boundary */
  182. pciauto_region_align(pci_prefetch, 0x100000);
  183. /* Set up memory and I/O filter limits, assume 32-bit I/O space */
  184. pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
  185. (pci_prefetch->bus_lower & 0xfff00000) >> 16);
  186. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
  187. #ifdef CONFIG_SYS_PCI_64BIT
  188. pci_hose_write_config_dword(hose, dev,
  189. PCI_PREF_BASE_UPPER32,
  190. pci_prefetch->bus_lower >> 32);
  191. #else
  192. pci_hose_write_config_dword(hose, dev,
  193. PCI_PREF_BASE_UPPER32,
  194. 0x0);
  195. #endif
  196. cmdstat |= PCI_COMMAND_MEMORY;
  197. } else {
  198. /* We don't support prefetchable memory for now, so disable */
  199. pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
  200. pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
  201. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
  202. pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
  203. pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
  204. }
  205. }
  206. if (pci_io) {
  207. /* Round I/O allocator to 4KB boundary */
  208. pciauto_region_align(pci_io, 0x1000);
  209. pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
  210. (pci_io->bus_lower & 0x0000f000) >> 8);
  211. pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
  212. (pci_io->bus_lower & 0xffff0000) >> 16);
  213. cmdstat |= PCI_COMMAND_IO;
  214. }
  215. /* Enable memory and I/O accesses, enable bus master */
  216. pci_hose_write_config_word(hose, dev, PCI_COMMAND,
  217. cmdstat | PCI_COMMAND_MASTER);
  218. }
  219. void pciauto_postscan_setup_bridge(struct pci_controller *hose,
  220. pci_dev_t dev, int sub_bus)
  221. {
  222. struct pci_region *pci_mem;
  223. struct pci_region *pci_prefetch;
  224. struct pci_region *pci_io;
  225. pci_mem = hose->pci_mem;
  226. pci_prefetch = hose->pci_prefetch;
  227. pci_io = hose->pci_io;
  228. /* Configure bus number registers */
  229. pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
  230. sub_bus - hose->first_busno);
  231. if (pci_mem) {
  232. /* Round memory allocator to 1MB boundary */
  233. pciauto_region_align(pci_mem, 0x100000);
  234. pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
  235. (pci_mem->bus_lower - 1) >> 16);
  236. }
  237. if (pci_prefetch) {
  238. u16 prefechable_64;
  239. pci_hose_read_config_word(hose, dev,
  240. PCI_PREF_MEMORY_LIMIT,
  241. &prefechable_64);
  242. prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
  243. /* Round memory allocator to 1MB boundary */
  244. pciauto_region_align(pci_prefetch, 0x100000);
  245. pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
  246. (pci_prefetch->bus_lower - 1) >> 16);
  247. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
  248. #ifdef CONFIG_SYS_PCI_64BIT
  249. pci_hose_write_config_dword(hose, dev,
  250. PCI_PREF_LIMIT_UPPER32,
  251. (pci_prefetch->bus_lower - 1) >> 32);
  252. #else
  253. pci_hose_write_config_dword(hose, dev,
  254. PCI_PREF_LIMIT_UPPER32,
  255. 0x0);
  256. #endif
  257. }
  258. if (pci_io) {
  259. /* Round I/O allocator to 4KB boundary */
  260. pciauto_region_align(pci_io, 0x1000);
  261. pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
  262. ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
  263. pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
  264. ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
  265. }
  266. }
  267. /*
  268. * HJF: Changed this to return int. I think this is required
  269. * to get the correct result when scanning bridges
  270. */
  271. int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
  272. {
  273. struct pci_region *pci_mem;
  274. struct pci_region *pci_prefetch;
  275. struct pci_region *pci_io;
  276. unsigned int sub_bus = PCI_BUS(dev);
  277. unsigned short class;
  278. int n;
  279. pci_mem = hose->pci_mem;
  280. pci_prefetch = hose->pci_prefetch;
  281. pci_io = hose->pci_io;
  282. pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
  283. switch (class) {
  284. case PCI_CLASS_BRIDGE_PCI:
  285. debug("PCI Autoconfig: Found P2P bridge, device %d\n",
  286. PCI_DEV(dev));
  287. pciauto_setup_device(hose, dev, 2, pci_mem,
  288. pci_prefetch, pci_io);
  289. /* Passing in current_busno allows for sibling P2P bridges */
  290. hose->current_busno++;
  291. pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
  292. /*
  293. * need to figure out if this is a subordinate bridge on the bus
  294. * to be able to properly set the pri/sec/sub bridge registers.
  295. */
  296. n = pci_hose_scan_bus(hose, hose->current_busno);
  297. /* figure out the deepest we've gone for this leg */
  298. sub_bus = max((unsigned int)n, sub_bus);
  299. pciauto_postscan_setup_bridge(hose, dev, sub_bus);
  300. sub_bus = hose->current_busno;
  301. break;
  302. case PCI_CLASS_BRIDGE_CARDBUS:
  303. /*
  304. * just do a minimal setup of the bridge,
  305. * let the OS take care of the rest
  306. */
  307. pciauto_setup_device(hose, dev, 0, pci_mem,
  308. pci_prefetch, pci_io);
  309. debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
  310. PCI_DEV(dev));
  311. hose->current_busno++;
  312. break;
  313. #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
  314. case PCI_CLASS_BRIDGE_OTHER:
  315. debug("PCI Autoconfig: Skipping bridge device %d\n",
  316. PCI_DEV(dev));
  317. break;
  318. #endif
  319. #if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
  320. !defined(CONFIG_TARGET_CADDY2)
  321. case PCI_CLASS_BRIDGE_OTHER:
  322. /*
  323. * The host/PCI bridge 1 seems broken in 8349 - it presents
  324. * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
  325. * device claiming resources io/mem/irq.. we only allow for
  326. * the PIMMR window to be allocated (BAR0 - 1MB size)
  327. */
  328. debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
  329. pciauto_setup_device(hose, dev, 0, hose->pci_mem,
  330. hose->pci_prefetch, hose->pci_io);
  331. break;
  332. #endif
  333. case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
  334. debug("PCI AutoConfig: Found PowerPC device\n");
  335. default:
  336. pciauto_setup_device(hose, dev, 6, pci_mem,
  337. pci_prefetch, pci_io);
  338. break;
  339. }
  340. return sub_bus;
  341. }