pci.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Andreas Heppel <aheppel@sysgo.de>
  5. *
  6. * (C) Copyright 2002, 2003
  7. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8. */
  9. /*
  10. * Old PCI routines
  11. *
  12. * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
  13. * and change pci-uclass.c.
  14. */
  15. #include <common.h>
  16. #include <init.h>
  17. #include <log.h>
  18. #include <linux/delay.h>
  19. #include <command.h>
  20. #include <env.h>
  21. #include <errno.h>
  22. #include <asm/processor.h>
  23. #include <asm/io.h>
  24. #include <pci.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #define PCI_HOSE_OP(rw, size, type) \
  27. int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
  28. pci_dev_t dev, \
  29. int offset, type value) \
  30. { \
  31. return hose->rw##_##size(hose, dev, offset, value); \
  32. }
  33. PCI_HOSE_OP(read, byte, u8 *)
  34. PCI_HOSE_OP(read, word, u16 *)
  35. PCI_HOSE_OP(read, dword, u32 *)
  36. PCI_HOSE_OP(write, byte, u8)
  37. PCI_HOSE_OP(write, word, u16)
  38. PCI_HOSE_OP(write, dword, u32)
  39. #define PCI_OP(rw, size, type, error_code) \
  40. int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
  41. { \
  42. struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
  43. \
  44. if (!hose) \
  45. { \
  46. error_code; \
  47. return -1; \
  48. } \
  49. \
  50. return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  51. }
  52. PCI_OP(read, byte, u8 *, *value = 0xff)
  53. PCI_OP(read, word, u16 *, *value = 0xffff)
  54. PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  55. PCI_OP(write, byte, u8, )
  56. PCI_OP(write, word, u16, )
  57. PCI_OP(write, dword, u32, )
  58. #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
  59. int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  60. pci_dev_t dev, \
  61. int offset, type val) \
  62. { \
  63. u32 val32; \
  64. \
  65. if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
  66. *val = -1; \
  67. return -1; \
  68. } \
  69. \
  70. *val = (val32 >> ((offset & (int)off_mask) * 8)); \
  71. \
  72. return 0; \
  73. }
  74. #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
  75. int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
  76. pci_dev_t dev, \
  77. int offset, type val) \
  78. { \
  79. u32 val32, mask, ldata, shift; \
  80. \
  81. if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
  82. return -1; \
  83. \
  84. shift = ((offset & (int)off_mask) * 8); \
  85. ldata = (((unsigned long)val) & val_mask) << shift; \
  86. mask = val_mask << shift; \
  87. val32 = (val32 & ~mask) | ldata; \
  88. \
  89. if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
  90. return -1; \
  91. \
  92. return 0; \
  93. }
  94. PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
  95. PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
  96. PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
  97. PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
  98. /*
  99. *
  100. */
  101. static struct pci_controller* hose_head;
  102. struct pci_controller *pci_get_hose_head(void)
  103. {
  104. if (gd->hose)
  105. return gd->hose;
  106. return hose_head;
  107. }
  108. void pci_register_hose(struct pci_controller* hose)
  109. {
  110. struct pci_controller **phose = &hose_head;
  111. while(*phose)
  112. phose = &(*phose)->next;
  113. hose->next = NULL;
  114. *phose = hose;
  115. }
  116. struct pci_controller *pci_bus_to_hose(int bus)
  117. {
  118. struct pci_controller *hose;
  119. for (hose = pci_get_hose_head(); hose; hose = hose->next) {
  120. if (bus >= hose->first_busno && bus <= hose->last_busno)
  121. return hose;
  122. }
  123. printf("pci_bus_to_hose() failed\n");
  124. return NULL;
  125. }
  126. struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
  127. {
  128. struct pci_controller *hose;
  129. for (hose = pci_get_hose_head(); hose; hose = hose->next) {
  130. if (hose->cfg_addr == cfg_addr)
  131. return hose;
  132. }
  133. return NULL;
  134. }
  135. int pci_last_busno(void)
  136. {
  137. struct pci_controller *hose = pci_get_hose_head();
  138. if (!hose)
  139. return -1;
  140. while (hose->next)
  141. hose = hose->next;
  142. return hose->last_busno;
  143. }
  144. pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
  145. {
  146. struct pci_controller * hose;
  147. pci_dev_t bdf;
  148. int bus;
  149. for (hose = pci_get_hose_head(); hose; hose = hose->next) {
  150. for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
  151. bdf = pci_hose_find_devices(hose, bus, ids, &index);
  152. if (bdf != -1)
  153. return bdf;
  154. }
  155. }
  156. return -1;
  157. }
  158. static int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev,
  159. ulong io, pci_addr_t mem, ulong command)
  160. {
  161. u32 bar_response;
  162. unsigned int old_command;
  163. pci_addr_t bar_value;
  164. pci_size_t bar_size;
  165. unsigned char pin;
  166. int bar, found_mem64;
  167. debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
  168. (u64)mem, command);
  169. pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
  170. for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
  171. pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
  172. pci_hose_read_config_dword(hose, dev, bar, &bar_response);
  173. if (!bar_response)
  174. continue;
  175. found_mem64 = 0;
  176. /* Check the BAR type and set our address mask */
  177. if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  178. bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
  179. /* round up region base address to a multiple of size */
  180. io = ((io - 1) | (bar_size - 1)) + 1;
  181. bar_value = io;
  182. /* compute new region base address */
  183. io = io + bar_size;
  184. } else {
  185. if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  186. PCI_BASE_ADDRESS_MEM_TYPE_64) {
  187. u32 bar_response_upper;
  188. u64 bar64;
  189. pci_hose_write_config_dword(hose, dev, bar + 4,
  190. 0xffffffff);
  191. pci_hose_read_config_dword(hose, dev, bar + 4,
  192. &bar_response_upper);
  193. bar64 = ((u64)bar_response_upper << 32) | bar_response;
  194. bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
  195. found_mem64 = 1;
  196. } else {
  197. bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
  198. }
  199. /* round up region base address to multiple of size */
  200. mem = ((mem - 1) | (bar_size - 1)) + 1;
  201. bar_value = mem;
  202. /* compute new region base address */
  203. mem = mem + bar_size;
  204. }
  205. /* Write it out and update our limit */
  206. pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
  207. if (found_mem64) {
  208. bar += 4;
  209. #ifdef CONFIG_SYS_PCI_64BIT
  210. pci_hose_write_config_dword(hose, dev, bar,
  211. (u32)(bar_value >> 32));
  212. #else
  213. pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
  214. #endif
  215. }
  216. }
  217. /* Configure Cache Line Size Register */
  218. pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
  219. /* Configure Latency Timer */
  220. pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
  221. /* Disable interrupt line, if device says it wants to use interrupts */
  222. pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
  223. if (pin != 0) {
  224. pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
  225. PCI_INTERRUPT_LINE_DISABLE);
  226. }
  227. pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
  228. pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
  229. (old_command & 0xffff0000) | command);
  230. return 0;
  231. }
  232. /*
  233. *
  234. */
  235. struct pci_config_table *pci_find_config(struct pci_controller *hose,
  236. unsigned short class,
  237. unsigned int vendor,
  238. unsigned int device,
  239. unsigned int bus,
  240. unsigned int dev,
  241. unsigned int func)
  242. {
  243. struct pci_config_table *table;
  244. for (table = hose->config_table; table && table->vendor; table++) {
  245. if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
  246. (table->device == PCI_ANY_ID || table->device == device) &&
  247. (table->class == PCI_ANY_ID || table->class == class) &&
  248. (table->bus == PCI_ANY_ID || table->bus == bus) &&
  249. (table->dev == PCI_ANY_ID || table->dev == dev) &&
  250. (table->func == PCI_ANY_ID || table->func == func)) {
  251. return table;
  252. }
  253. }
  254. return NULL;
  255. }
  256. void pci_cfgfunc_config_device(struct pci_controller *hose,
  257. pci_dev_t dev,
  258. struct pci_config_table *entry)
  259. {
  260. pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
  261. entry->priv[2]);
  262. }
  263. void pci_cfgfunc_do_nothing(struct pci_controller *hose,
  264. pci_dev_t dev, struct pci_config_table *entry)
  265. {
  266. }
  267. /*
  268. * HJF: Changed this to return int. I think this is required
  269. * to get the correct result when scanning bridges
  270. */
  271. extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
  272. #ifdef CONFIG_PCI_SCAN_SHOW
  273. __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
  274. {
  275. if (dev == PCI_BDF(hose->first_busno, 0, 0))
  276. return 0;
  277. return 1;
  278. }
  279. #endif /* CONFIG_PCI_SCAN_SHOW */
  280. int pci_hose_scan_bus(struct pci_controller *hose, int bus)
  281. {
  282. unsigned int sub_bus, found_multi = 0;
  283. unsigned short vendor, device, class;
  284. unsigned char header_type;
  285. #ifndef CONFIG_PCI_PNP
  286. struct pci_config_table *cfg;
  287. #endif
  288. pci_dev_t dev;
  289. #ifdef CONFIG_PCI_SCAN_SHOW
  290. static int indent = 0;
  291. #endif
  292. sub_bus = bus;
  293. for (dev = PCI_BDF(bus,0,0);
  294. dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
  295. PCI_MAX_PCI_FUNCTIONS - 1);
  296. dev += PCI_BDF(0, 0, 1)) {
  297. if (pci_skip_dev(hose, dev))
  298. continue;
  299. if (PCI_FUNC(dev) && !found_multi)
  300. continue;
  301. pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
  302. pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
  303. if (vendor == 0xffff || vendor == 0x0000)
  304. continue;
  305. if (!PCI_FUNC(dev))
  306. found_multi = header_type & 0x80;
  307. debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
  308. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
  309. pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
  310. pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
  311. #ifdef CONFIG_PCI_FIXUP_DEV
  312. board_pci_fixup_dev(hose, dev, vendor, device, class);
  313. #endif
  314. #ifdef CONFIG_PCI_SCAN_SHOW
  315. indent++;
  316. /* Print leading space, including bus indentation */
  317. printf("%*c", indent + 1, ' ');
  318. if (pci_print_dev(hose, dev)) {
  319. printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
  320. PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
  321. vendor, device, pci_class_str(class >> 8));
  322. }
  323. #endif
  324. #ifdef CONFIG_PCI_PNP
  325. sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
  326. sub_bus);
  327. #else
  328. cfg = pci_find_config(hose, class, vendor, device,
  329. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
  330. if (cfg) {
  331. cfg->config_device(hose, dev, cfg);
  332. sub_bus = max(sub_bus,
  333. (unsigned int)hose->current_busno);
  334. }
  335. #endif
  336. #ifdef CONFIG_PCI_SCAN_SHOW
  337. indent--;
  338. #endif
  339. if (hose->fixup_irq)
  340. hose->fixup_irq(hose, dev);
  341. }
  342. return sub_bus;
  343. }
  344. int pci_hose_scan(struct pci_controller *hose)
  345. {
  346. #if defined(CONFIG_PCI_BOOTDELAY)
  347. char *s;
  348. int i;
  349. if (!gd->pcidelay_done) {
  350. /* wait "pcidelay" ms (if defined)... */
  351. s = env_get("pcidelay");
  352. if (s) {
  353. int val = simple_strtoul(s, NULL, 10);
  354. for (i = 0; i < val; i++)
  355. udelay(1000);
  356. }
  357. gd->pcidelay_done = 1;
  358. }
  359. #endif /* CONFIG_PCI_BOOTDELAY */
  360. #ifdef CONFIG_PCI_SCAN_SHOW
  361. puts("PCI:\n");
  362. #endif
  363. /*
  364. * Start scan at current_busno.
  365. * PCIe will start scan at first_busno+1.
  366. */
  367. /* For legacy support, ensure current >= first */
  368. if (hose->first_busno > hose->current_busno)
  369. hose->current_busno = hose->first_busno;
  370. #ifdef CONFIG_PCI_PNP
  371. pciauto_config_init(hose);
  372. #endif
  373. return pci_hose_scan_bus(hose, hose->current_busno);
  374. }
  375. void pci_init(void)
  376. {
  377. hose_head = NULL;
  378. /* allow env to disable pci init/enum */
  379. if (env_get("pcidisable") != NULL)
  380. return;
  381. /* now call board specific pci_init()... */
  382. pci_init_board();
  383. }
  384. /* Returns the address of the requested capability structure within the
  385. * device's PCI configuration space or 0 in case the device does not
  386. * support it.
  387. * */
  388. int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
  389. int cap)
  390. {
  391. int pos;
  392. u8 hdr_type;
  393. pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
  394. pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
  395. if (pos)
  396. pos = pci_find_cap(hose, dev, pos, cap);
  397. return pos;
  398. }
  399. /* Find the header pointer to the Capabilities*/
  400. int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
  401. u8 hdr_type)
  402. {
  403. u16 status;
  404. pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
  405. if (!(status & PCI_STATUS_CAP_LIST))
  406. return 0;
  407. switch (hdr_type) {
  408. case PCI_HEADER_TYPE_NORMAL:
  409. case PCI_HEADER_TYPE_BRIDGE:
  410. return PCI_CAPABILITY_LIST;
  411. case PCI_HEADER_TYPE_CARDBUS:
  412. return PCI_CB_CAPABILITY_LIST;
  413. default:
  414. return 0;
  415. }
  416. }
  417. int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
  418. {
  419. int ttl = PCI_FIND_CAP_TTL;
  420. u8 id;
  421. u8 next_pos;
  422. while (ttl--) {
  423. pci_hose_read_config_byte(hose, dev, pos, &next_pos);
  424. if (next_pos < CAP_START_POS)
  425. break;
  426. next_pos &= ~3;
  427. pos = (int) next_pos;
  428. pci_hose_read_config_byte(hose, dev,
  429. pos + PCI_CAP_LIST_ID, &id);
  430. if (id == 0xff)
  431. break;
  432. if (id == cap)
  433. return pos;
  434. pos += PCI_CAP_LIST_NEXT;
  435. }
  436. return 0;
  437. }
  438. /**
  439. * pci_find_next_ext_capability - Find an extended capability
  440. *
  441. * Returns the address of the next matching extended capability structure
  442. * within the device's PCI configuration space or 0 if the device does
  443. * not support it. Some capabilities can occur several times, e.g., the
  444. * vendor-specific capability, and this provides a way to find them all.
  445. */
  446. int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
  447. int start, int cap)
  448. {
  449. u32 header;
  450. int ttl, pos = PCI_CFG_SPACE_SIZE;
  451. /* minimum 8 bytes per capability */
  452. ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
  453. if (start)
  454. pos = start;
  455. pci_hose_read_config_dword(hose, dev, pos, &header);
  456. if (header == 0xffffffff || header == 0)
  457. return 0;
  458. while (ttl-- > 0) {
  459. if (PCI_EXT_CAP_ID(header) == cap && pos != start)
  460. return pos;
  461. pos = PCI_EXT_CAP_NEXT(header);
  462. if (pos < PCI_CFG_SPACE_SIZE)
  463. break;
  464. pci_hose_read_config_dword(hose, dev, pos, &header);
  465. if (header == 0xffffffff || header == 0)
  466. break;
  467. }
  468. return 0;
  469. }
  470. /**
  471. * pci_hose_find_ext_capability - Find an extended capability
  472. *
  473. * Returns the address of the requested extended capability structure
  474. * within the device's PCI configuration space or 0 if the device does
  475. * not support it.
  476. */
  477. int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
  478. int cap)
  479. {
  480. return pci_find_next_ext_capability(hose, dev, 0, cap);
  481. }