pci-rcar-gen2.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas RCar Gen2 PCIEC driver
  4. *
  5. * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <pci.h>
  13. #include <linux/bitops.h>
  14. /* AHB-PCI Bridge PCI communication registers */
  15. #define RCAR_AHBPCI_PCICOM_OFFSET 0x800
  16. #define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
  17. #define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
  18. #define RCAR_PCIAHB_PREFETCH0 0x0
  19. #define RCAR_PCIAHB_PREFETCH4 0x1
  20. #define RCAR_PCIAHB_PREFETCH8 0x2
  21. #define RCAR_PCIAHB_PREFETCH16 0x3
  22. #define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
  23. #define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
  24. #define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
  25. #define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
  26. #define RCAR_AHBPCI_WIN1_HOST BIT(30)
  27. #define RCAR_AHBPCI_WIN1_DEVICE BIT(31)
  28. #define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
  29. #define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
  30. #define RCAR_PCI_INT_SIGTABORT BIT(0)
  31. #define RCAR_PCI_INT_SIGRETABORT BIT(1)
  32. #define RCAR_PCI_INT_REMABORT BIT(2)
  33. #define RCAR_PCI_INT_PERR BIT(3)
  34. #define RCAR_PCI_INT_SIGSERR BIT(4)
  35. #define RCAR_PCI_INT_RESERR BIT(5)
  36. #define RCAR_PCI_INT_WIN1ERR BIT(12)
  37. #define RCAR_PCI_INT_WIN2ERR BIT(13)
  38. #define RCAR_PCI_INT_A BIT(16)
  39. #define RCAR_PCI_INT_B BIT(17)
  40. #define RCAR_PCI_INT_PME BIT(19)
  41. #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \
  42. RCAR_PCI_INT_SIGRETABORT | \
  43. RCAR_PCI_INT_SIGRETABORT | \
  44. RCAR_PCI_INT_REMABORT | \
  45. RCAR_PCI_INT_PERR | \
  46. RCAR_PCI_INT_SIGSERR | \
  47. RCAR_PCI_INT_RESERR | \
  48. RCAR_PCI_INT_WIN1ERR | \
  49. RCAR_PCI_INT_WIN2ERR)
  50. #define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
  51. #define RCAR_AHB_BUS_MMODE_HTRANS BIT(0)
  52. #define RCAR_AHB_BUS_MMODE_BYTE_BURST BIT(1)
  53. #define RCAR_AHB_BUS_MMODE_WR_INCR BIT(2)
  54. #define RCAR_AHB_BUS_MMODE_HBUS_REQ BIT(7)
  55. #define RCAR_AHB_BUS_SMODE_READYCTR BIT(17)
  56. #define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \
  57. RCAR_AHB_BUS_MMODE_BYTE_BURST | \
  58. RCAR_AHB_BUS_MMODE_WR_INCR | \
  59. RCAR_AHB_BUS_MMODE_HBUS_REQ | \
  60. RCAR_AHB_BUS_SMODE_READYCTR)
  61. #define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
  62. #define RCAR_USBCTR_USBH_RST BIT(0)
  63. #define RCAR_USBCTR_PCICLK_MASK BIT(1)
  64. #define RCAR_USBCTR_PLL_RST BIT(2)
  65. #define RCAR_USBCTR_DIRPD BIT(8)
  66. #define RCAR_USBCTR_PCIAHB_WIN2_EN BIT(9)
  67. #define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
  68. #define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
  69. #define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
  70. #define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
  71. #define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
  72. #define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
  73. #define RCAR_PCI_ARBITER_PCIREQ0 BIT(0)
  74. #define RCAR_PCI_ARBITER_PCIREQ1 BIT(1)
  75. #define RCAR_PCI_ARBITER_PCIBP_MODE BIT(12)
  76. #define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
  77. struct rcar_gen2_pci_priv {
  78. fdt_addr_t cfg_base;
  79. fdt_addr_t mem_base;
  80. };
  81. static int rcar_gen2_pci_addr_valid(pci_dev_t d, uint offset)
  82. {
  83. u32 slot;
  84. if (PCI_FUNC(d))
  85. return -EINVAL;
  86. /* Only one EHCI/OHCI device built-in */
  87. slot = PCI_DEV(d);
  88. if (slot != 1 && slot != 2)
  89. return -EINVAL;
  90. /* bridge logic only has registers to 0x40 */
  91. if (slot == 0x0 && offset >= 0x40)
  92. return -EINVAL;
  93. return 0;
  94. }
  95. static u32 get_bus_address(const struct udevice *dev, pci_dev_t bdf, u32 offset)
  96. {
  97. struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
  98. return priv->cfg_base + (PCI_DEV(bdf) >> 1) * 0x100 + (offset & ~3);
  99. }
  100. static u32 setup_bus_address(struct udevice *dev, pci_dev_t bdf, u32 offset)
  101. {
  102. struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
  103. u32 reg;
  104. reg = PCI_DEV(bdf) ? RCAR_AHBPCI_WIN1_DEVICE : RCAR_AHBPCI_WIN1_HOST;
  105. reg |= RCAR_AHBPCI_WIN_CTR_CFG;
  106. writel(reg, priv->cfg_base + RCAR_AHBPCI_WIN1_CTR_REG);
  107. return get_bus_address(dev, bdf, offset);
  108. }
  109. static int rcar_gen2_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
  110. uint offset, ulong *value,
  111. enum pci_size_t size)
  112. {
  113. u32 addr, reg;
  114. int ret;
  115. ret = rcar_gen2_pci_addr_valid(bdf, offset);
  116. if (ret) {
  117. *value = pci_get_ff(size);
  118. return 0;
  119. }
  120. addr = get_bus_address(dev, bdf, offset);
  121. reg = readl(addr);
  122. *value = pci_conv_32_to_size(reg, offset, size);
  123. return 0;
  124. }
  125. static int rcar_gen2_pci_write_config(struct udevice *dev, pci_dev_t bdf,
  126. uint offset, ulong value,
  127. enum pci_size_t size)
  128. {
  129. u32 addr, reg, old;
  130. int ret;
  131. ret = rcar_gen2_pci_addr_valid(bdf, offset);
  132. if (ret)
  133. return ret;
  134. addr = get_bus_address(dev, bdf, offset);
  135. old = readl(addr);
  136. reg = pci_conv_size_to_32(old, value, offset, size);
  137. writel(reg, addr);
  138. return 0;
  139. }
  140. static int rcar_gen2_pci_probe(struct udevice *dev)
  141. {
  142. struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
  143. struct clk pci_clk;
  144. u32 devad;
  145. int ret;
  146. ret = clk_get_by_index(dev, 0, &pci_clk);
  147. if (ret)
  148. return ret;
  149. ret = clk_enable(&pci_clk);
  150. if (ret)
  151. return ret;
  152. /* Clock & Reset & Direct Power Down */
  153. clrsetbits_le32(priv->cfg_base + RCAR_USBCTR_REG,
  154. RCAR_USBCTR_DIRPD | RCAR_USBCTR_PCICLK_MASK |
  155. RCAR_USBCTR_USBH_RST,
  156. RCAR_USBCTR_PCIAHB_WIN1_1G);
  157. clrbits_le32(priv->cfg_base + RCAR_USBCTR_REG, RCAR_USBCTR_PLL_RST);
  158. /* AHB-PCI Bridge Communication Registers */
  159. writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG);
  160. writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16,
  161. priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG);
  162. writel(0xf0000000 | RCAR_PCIAHB_PREFETCH16,
  163. priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG);
  164. writel(priv->mem_base | RCAR_AHBPCI_WIN_CTR_MEM,
  165. priv->cfg_base + RCAR_AHBPCI_WIN2_CTR_REG);
  166. setbits_le32(priv->cfg_base + RCAR_PCI_ARBITER_CTR_REG,
  167. RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
  168. RCAR_PCI_ARBITER_PCIBP_MODE);
  169. /* PCI Configuration Registers for AHBPCI */
  170. devad = setup_bus_address(dev, PCI_BDF(0, 0, 0), 0);
  171. writel(priv->cfg_base + 0x800, devad + PCI_BASE_ADDRESS_0);
  172. writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1);
  173. writel(0xf0000000, devad + PCI_BASE_ADDRESS_2);
  174. writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  175. PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
  176. devad + PCI_COMMAND);
  177. /* PCI Configuration Registers for OHCI */
  178. devad = setup_bus_address(dev, PCI_BDF(0, 1, 0), 0);
  179. writel(priv->mem_base + 0x0, devad + PCI_BASE_ADDRESS_0);
  180. writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  181. PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
  182. devad + PCI_COMMAND);
  183. /* PCI Configuration Registers for EHCI */
  184. devad = setup_bus_address(dev, PCI_BDF(0, 2, 0), 0);
  185. writel(priv->mem_base + 0x1000, devad + PCI_BASE_ADDRESS_0);
  186. writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  187. PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
  188. devad + PCI_COMMAND);
  189. /* Enable PCI interrupt */
  190. setbits_le32(priv->cfg_base + RCAR_PCI_INT_ENABLE_REG,
  191. RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME);
  192. return 0;
  193. }
  194. static int rcar_gen2_pci_ofdata_to_platdata(struct udevice *dev)
  195. {
  196. struct rcar_gen2_pci_priv *priv = dev_get_priv(dev);
  197. priv->cfg_base = devfdt_get_addr_index(dev, 0);
  198. priv->mem_base = devfdt_get_addr_index(dev, 1);
  199. if (!priv->cfg_base || !priv->mem_base)
  200. return -EINVAL;
  201. return 0;
  202. }
  203. static const struct dm_pci_ops rcar_gen2_pci_ops = {
  204. .read_config = rcar_gen2_pci_read_config,
  205. .write_config = rcar_gen2_pci_write_config,
  206. };
  207. static const struct udevice_id rcar_gen2_pci_ids[] = {
  208. { .compatible = "renesas,pci-rcar-gen2" },
  209. { }
  210. };
  211. U_BOOT_DRIVER(rcar_gen2_pci) = {
  212. .name = "rcar_gen2_pci",
  213. .id = UCLASS_PCI,
  214. .of_match = rcar_gen2_pci_ids,
  215. .ops = &rcar_gen2_pci_ops,
  216. .probe = rcar_gen2_pci_probe,
  217. .ofdata_to_platdata = rcar_gen2_pci_ofdata_to_platdata,
  218. .priv_auto_alloc_size = sizeof(struct rcar_gen2_pci_priv),
  219. };