pch7.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <log.h>
  8. #include <pch.h>
  9. #define GPIO_BASE 0x44
  10. #define BIOS_CTRL 0xd8
  11. static int pch7_get_spi_base(struct udevice *dev, ulong *sbasep)
  12. {
  13. u32 rcba;
  14. dm_pci_read_config32(dev, PCH_RCBA, &rcba);
  15. /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
  16. rcba = rcba & 0xffffc000;
  17. *sbasep = rcba + 0x3020;
  18. return 0;
  19. }
  20. static int pch7_set_spi_protect(struct udevice *dev, bool protect)
  21. {
  22. uint8_t bios_cntl;
  23. /* Adjust the BIOS write protect to dis/allow write commands */
  24. dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
  25. if (protect)
  26. bios_cntl &= ~BIOS_CTRL_BIOSWE;
  27. else
  28. bios_cntl |= BIOS_CTRL_BIOSWE;
  29. dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
  30. return 0;
  31. }
  32. static int pch7_get_gpio_base(struct udevice *dev, u32 *gbasep)
  33. {
  34. u32 base;
  35. /*
  36. * GPIO_BASE moved to its current offset with ICH6, but prior to
  37. * that it was unused (or undocumented). Check that it looks
  38. * okay: not all ones or zeros.
  39. *
  40. * Note we don't need check bit0 here, because the Tunnel Creek
  41. * GPIO base address register bit0 is reserved (read returns 0),
  42. * while on the Ivybridge the bit0 is used to indicate it is an
  43. * I/O space.
  44. */
  45. dm_pci_read_config32(dev, GPIO_BASE, &base);
  46. if (base == 0x00000000 || base == 0xffffffff) {
  47. debug("%s: unexpected BASE value\n", __func__);
  48. return -ENODEV;
  49. }
  50. /*
  51. * Okay, I guess we're looking at the right device. The actual
  52. * GPIO registers are in the PCI device's I/O space, starting
  53. * at the offset that we just read. Bit 0 indicates that it's
  54. * an I/O address, not a memory address, so mask that off.
  55. */
  56. *gbasep = base & 1 ? base & ~3 : base & ~15;
  57. return 0;
  58. }
  59. static const struct pch_ops pch7_ops = {
  60. .get_spi_base = pch7_get_spi_base,
  61. .set_spi_protect = pch7_set_spi_protect,
  62. .get_gpio_base = pch7_get_gpio_base,
  63. };
  64. static const struct udevice_id pch7_ids[] = {
  65. { .compatible = "intel,pch7" },
  66. { }
  67. };
  68. U_BOOT_DRIVER(pch7_drv) = {
  69. .name = "intel-pch7",
  70. .id = UCLASS_PCH,
  71. .of_match = pch7_ids,
  72. .ops = &pch7_ops,
  73. };