nvme.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2017 NXP Semiconductors
  4. * Copyright (C) 2017 Bin Meng <bmeng.cn@gmail.com>
  5. */
  6. #ifndef __DRIVER_NVME_H__
  7. #define __DRIVER_NVME_H__
  8. #include <asm/io.h>
  9. struct nvme_id_power_state {
  10. __le16 max_power; /* centiwatts */
  11. __u8 rsvd2;
  12. __u8 flags;
  13. __le32 entry_lat; /* microseconds */
  14. __le32 exit_lat; /* microseconds */
  15. __u8 read_tput;
  16. __u8 read_lat;
  17. __u8 write_tput;
  18. __u8 write_lat;
  19. __le16 idle_power;
  20. __u8 idle_scale;
  21. __u8 rsvd19;
  22. __le16 active_power;
  23. __u8 active_work_scale;
  24. __u8 rsvd23[9];
  25. };
  26. enum {
  27. NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
  28. NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
  29. };
  30. struct nvme_id_ctrl {
  31. __le16 vid;
  32. __le16 ssvid;
  33. char sn[20];
  34. char mn[40];
  35. char fr[8];
  36. __u8 rab;
  37. __u8 ieee[3];
  38. __u8 mic;
  39. __u8 mdts;
  40. __u16 cntlid;
  41. __u32 ver;
  42. __u8 rsvd84[172];
  43. __le16 oacs;
  44. __u8 acl;
  45. __u8 aerl;
  46. __u8 frmw;
  47. __u8 lpa;
  48. __u8 elpe;
  49. __u8 npss;
  50. __u8 avscc;
  51. __u8 apsta;
  52. __le16 wctemp;
  53. __le16 cctemp;
  54. __u8 rsvd270[242];
  55. __u8 sqes;
  56. __u8 cqes;
  57. __u8 rsvd514[2];
  58. __le32 nn;
  59. __le16 oncs;
  60. __le16 fuses;
  61. __u8 fna;
  62. __u8 vwc;
  63. __le16 awun;
  64. __le16 awupf;
  65. __u8 nvscc;
  66. __u8 rsvd531;
  67. __le16 acwu;
  68. __u8 rsvd534[2];
  69. __le32 sgls;
  70. __u8 rsvd540[1508];
  71. struct nvme_id_power_state psd[32];
  72. __u8 vs[1024];
  73. };
  74. enum {
  75. NVME_CTRL_ONCS_COMPARE = 1 << 0,
  76. NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
  77. NVME_CTRL_ONCS_DSM = 1 << 2,
  78. NVME_CTRL_VWC_PRESENT = 1 << 0,
  79. };
  80. struct nvme_lbaf {
  81. __le16 ms;
  82. __u8 ds;
  83. __u8 rp;
  84. };
  85. struct nvme_id_ns {
  86. __le64 nsze;
  87. __le64 ncap;
  88. __le64 nuse;
  89. __u8 nsfeat;
  90. __u8 nlbaf;
  91. __u8 flbas;
  92. __u8 mc;
  93. __u8 dpc;
  94. __u8 dps;
  95. __u8 nmic;
  96. __u8 rescap;
  97. __u8 fpi;
  98. __u8 rsvd33;
  99. __le16 nawun;
  100. __le16 nawupf;
  101. __le16 nacwu;
  102. __le16 nabsn;
  103. __le16 nabo;
  104. __le16 nabspf;
  105. __u16 rsvd46;
  106. __le64 nvmcap[2];
  107. __u8 rsvd64[40];
  108. __u8 nguid[16];
  109. __u8 eui64[8];
  110. struct nvme_lbaf lbaf[16];
  111. __u8 rsvd192[192];
  112. __u8 vs[3712];
  113. };
  114. enum {
  115. NVME_NS_FEAT_THIN = 1 << 0,
  116. NVME_NS_FLBAS_LBA_MASK = 0xf,
  117. NVME_NS_FLBAS_META_EXT = 0x10,
  118. NVME_LBAF_RP_BEST = 0,
  119. NVME_LBAF_RP_BETTER = 1,
  120. NVME_LBAF_RP_GOOD = 2,
  121. NVME_LBAF_RP_DEGRADED = 3,
  122. NVME_NS_DPC_PI_LAST = 1 << 4,
  123. NVME_NS_DPC_PI_FIRST = 1 << 3,
  124. NVME_NS_DPC_PI_TYPE3 = 1 << 2,
  125. NVME_NS_DPC_PI_TYPE2 = 1 << 1,
  126. NVME_NS_DPC_PI_TYPE1 = 1 << 0,
  127. NVME_NS_DPS_PI_FIRST = 1 << 3,
  128. NVME_NS_DPS_PI_MASK = 0x7,
  129. NVME_NS_DPS_PI_TYPE1 = 1,
  130. NVME_NS_DPS_PI_TYPE2 = 2,
  131. NVME_NS_DPS_PI_TYPE3 = 3,
  132. };
  133. struct nvme_smart_log {
  134. __u8 critical_warning;
  135. __u8 temperature[2];
  136. __u8 avail_spare;
  137. __u8 spare_thresh;
  138. __u8 percent_used;
  139. __u8 rsvd6[26];
  140. __u8 data_units_read[16];
  141. __u8 data_units_written[16];
  142. __u8 host_reads[16];
  143. __u8 host_writes[16];
  144. __u8 ctrl_busy_time[16];
  145. __u8 power_cycles[16];
  146. __u8 power_on_hours[16];
  147. __u8 unsafe_shutdowns[16];
  148. __u8 media_errors[16];
  149. __u8 num_err_log_entries[16];
  150. __le32 warning_temp_time;
  151. __le32 critical_comp_time;
  152. __le16 temp_sensor[8];
  153. __u8 rsvd216[296];
  154. };
  155. enum {
  156. NVME_SMART_CRIT_SPARE = 1 << 0,
  157. NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
  158. NVME_SMART_CRIT_RELIABILITY = 1 << 2,
  159. NVME_SMART_CRIT_MEDIA = 1 << 3,
  160. NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
  161. };
  162. struct nvme_lba_range_type {
  163. __u8 type;
  164. __u8 attributes;
  165. __u8 rsvd2[14];
  166. __u64 slba;
  167. __u64 nlb;
  168. __u8 guid[16];
  169. __u8 rsvd48[16];
  170. };
  171. enum {
  172. NVME_LBART_TYPE_FS = 0x01,
  173. NVME_LBART_TYPE_RAID = 0x02,
  174. NVME_LBART_TYPE_CACHE = 0x03,
  175. NVME_LBART_TYPE_SWAP = 0x04,
  176. NVME_LBART_ATTRIB_TEMP = 1 << 0,
  177. NVME_LBART_ATTRIB_HIDE = 1 << 1,
  178. };
  179. struct nvme_reservation_status {
  180. __le32 gen;
  181. __u8 rtype;
  182. __u8 regctl[2];
  183. __u8 resv5[2];
  184. __u8 ptpls;
  185. __u8 resv10[13];
  186. struct {
  187. __le16 cntlid;
  188. __u8 rcsts;
  189. __u8 resv3[5];
  190. __le64 hostid;
  191. __le64 rkey;
  192. } regctl_ds[];
  193. };
  194. /* I/O commands */
  195. enum nvme_opcode {
  196. nvme_cmd_flush = 0x00,
  197. nvme_cmd_write = 0x01,
  198. nvme_cmd_read = 0x02,
  199. nvme_cmd_write_uncor = 0x04,
  200. nvme_cmd_compare = 0x05,
  201. nvme_cmd_write_zeroes = 0x08,
  202. nvme_cmd_dsm = 0x09,
  203. nvme_cmd_resv_register = 0x0d,
  204. nvme_cmd_resv_report = 0x0e,
  205. nvme_cmd_resv_acquire = 0x11,
  206. nvme_cmd_resv_release = 0x15,
  207. };
  208. struct nvme_common_command {
  209. __u8 opcode;
  210. __u8 flags;
  211. __u16 command_id;
  212. __le32 nsid;
  213. __le32 cdw2[2];
  214. __le64 metadata;
  215. __le64 prp1;
  216. __le64 prp2;
  217. __le32 cdw10[6];
  218. };
  219. struct nvme_rw_command {
  220. __u8 opcode;
  221. __u8 flags;
  222. __u16 command_id;
  223. __le32 nsid;
  224. __u64 rsvd2;
  225. __le64 metadata;
  226. __le64 prp1;
  227. __le64 prp2;
  228. __le64 slba;
  229. __le16 length;
  230. __le16 control;
  231. __le32 dsmgmt;
  232. __le32 reftag;
  233. __le16 apptag;
  234. __le16 appmask;
  235. };
  236. enum {
  237. NVME_RW_LR = 1 << 15,
  238. NVME_RW_FUA = 1 << 14,
  239. NVME_RW_DSM_FREQ_UNSPEC = 0,
  240. NVME_RW_DSM_FREQ_TYPICAL = 1,
  241. NVME_RW_DSM_FREQ_RARE = 2,
  242. NVME_RW_DSM_FREQ_READS = 3,
  243. NVME_RW_DSM_FREQ_WRITES = 4,
  244. NVME_RW_DSM_FREQ_RW = 5,
  245. NVME_RW_DSM_FREQ_ONCE = 6,
  246. NVME_RW_DSM_FREQ_PREFETCH = 7,
  247. NVME_RW_DSM_FREQ_TEMP = 8,
  248. NVME_RW_DSM_LATENCY_NONE = 0 << 4,
  249. NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
  250. NVME_RW_DSM_LATENCY_NORM = 2 << 4,
  251. NVME_RW_DSM_LATENCY_LOW = 3 << 4,
  252. NVME_RW_DSM_SEQ_REQ = 1 << 6,
  253. NVME_RW_DSM_COMPRESSED = 1 << 7,
  254. NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
  255. NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
  256. NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
  257. NVME_RW_PRINFO_PRACT = 1 << 13,
  258. };
  259. struct nvme_dsm_cmd {
  260. __u8 opcode;
  261. __u8 flags;
  262. __u16 command_id;
  263. __le32 nsid;
  264. __u64 rsvd2[2];
  265. __le64 prp1;
  266. __le64 prp2;
  267. __le32 nr;
  268. __le32 attributes;
  269. __u32 rsvd12[4];
  270. };
  271. enum {
  272. NVME_DSMGMT_IDR = 1 << 0,
  273. NVME_DSMGMT_IDW = 1 << 1,
  274. NVME_DSMGMT_AD = 1 << 2,
  275. };
  276. struct nvme_dsm_range {
  277. __le32 cattr;
  278. __le32 nlb;
  279. __le64 slba;
  280. };
  281. /* Admin commands */
  282. enum nvme_admin_opcode {
  283. nvme_admin_delete_sq = 0x00,
  284. nvme_admin_create_sq = 0x01,
  285. nvme_admin_get_log_page = 0x02,
  286. nvme_admin_delete_cq = 0x04,
  287. nvme_admin_create_cq = 0x05,
  288. nvme_admin_identify = 0x06,
  289. nvme_admin_abort_cmd = 0x08,
  290. nvme_admin_set_features = 0x09,
  291. nvme_admin_get_features = 0x0a,
  292. nvme_admin_async_event = 0x0c,
  293. nvme_admin_activate_fw = 0x10,
  294. nvme_admin_download_fw = 0x11,
  295. nvme_admin_format_nvm = 0x80,
  296. nvme_admin_security_send = 0x81,
  297. nvme_admin_security_recv = 0x82,
  298. };
  299. enum {
  300. NVME_QUEUE_PHYS_CONTIG = (1 << 0),
  301. NVME_CQ_IRQ_ENABLED = (1 << 1),
  302. NVME_SQ_PRIO_URGENT = (0 << 1),
  303. NVME_SQ_PRIO_HIGH = (1 << 1),
  304. NVME_SQ_PRIO_MEDIUM = (2 << 1),
  305. NVME_SQ_PRIO_LOW = (3 << 1),
  306. NVME_FEAT_ARBITRATION = 0x01,
  307. NVME_FEAT_POWER_MGMT = 0x02,
  308. NVME_FEAT_LBA_RANGE = 0x03,
  309. NVME_FEAT_TEMP_THRESH = 0x04,
  310. NVME_FEAT_ERR_RECOVERY = 0x05,
  311. NVME_FEAT_VOLATILE_WC = 0x06,
  312. NVME_FEAT_NUM_QUEUES = 0x07,
  313. NVME_FEAT_IRQ_COALESCE = 0x08,
  314. NVME_FEAT_IRQ_CONFIG = 0x09,
  315. NVME_FEAT_WRITE_ATOMIC = 0x0a,
  316. NVME_FEAT_ASYNC_EVENT = 0x0b,
  317. NVME_FEAT_AUTO_PST = 0x0c,
  318. NVME_FEAT_SW_PROGRESS = 0x80,
  319. NVME_FEAT_HOST_ID = 0x81,
  320. NVME_FEAT_RESV_MASK = 0x82,
  321. NVME_FEAT_RESV_PERSIST = 0x83,
  322. NVME_LOG_ERROR = 0x01,
  323. NVME_LOG_SMART = 0x02,
  324. NVME_LOG_FW_SLOT = 0x03,
  325. NVME_LOG_RESERVATION = 0x80,
  326. NVME_FWACT_REPL = (0 << 3),
  327. NVME_FWACT_REPL_ACTV = (1 << 3),
  328. NVME_FWACT_ACTV = (2 << 3),
  329. };
  330. struct nvme_identify {
  331. __u8 opcode;
  332. __u8 flags;
  333. __u16 command_id;
  334. __le32 nsid;
  335. __u64 rsvd2[2];
  336. __le64 prp1;
  337. __le64 prp2;
  338. __le32 cns;
  339. __u32 rsvd11[5];
  340. };
  341. struct nvme_features {
  342. __u8 opcode;
  343. __u8 flags;
  344. __u16 command_id;
  345. __le32 nsid;
  346. __u64 rsvd2[2];
  347. __le64 prp1;
  348. __le64 prp2;
  349. __le32 fid;
  350. __le32 dword11;
  351. __u32 rsvd12[4];
  352. };
  353. struct nvme_create_cq {
  354. __u8 opcode;
  355. __u8 flags;
  356. __u16 command_id;
  357. __u32 rsvd1[5];
  358. __le64 prp1;
  359. __u64 rsvd8;
  360. __le16 cqid;
  361. __le16 qsize;
  362. __le16 cq_flags;
  363. __le16 irq_vector;
  364. __u32 rsvd12[4];
  365. };
  366. struct nvme_create_sq {
  367. __u8 opcode;
  368. __u8 flags;
  369. __u16 command_id;
  370. __u32 rsvd1[5];
  371. __le64 prp1;
  372. __u64 rsvd8;
  373. __le16 sqid;
  374. __le16 qsize;
  375. __le16 sq_flags;
  376. __le16 cqid;
  377. __u32 rsvd12[4];
  378. };
  379. struct nvme_delete_queue {
  380. __u8 opcode;
  381. __u8 flags;
  382. __u16 command_id;
  383. __u32 rsvd1[9];
  384. __le16 qid;
  385. __u16 rsvd10;
  386. __u32 rsvd11[5];
  387. };
  388. struct nvme_abort_cmd {
  389. __u8 opcode;
  390. __u8 flags;
  391. __u16 command_id;
  392. __u32 rsvd1[9];
  393. __le16 sqid;
  394. __u16 cid;
  395. __u32 rsvd11[5];
  396. };
  397. struct nvme_download_firmware {
  398. __u8 opcode;
  399. __u8 flags;
  400. __u16 command_id;
  401. __u32 rsvd1[5];
  402. __le64 prp1;
  403. __le64 prp2;
  404. __le32 numd;
  405. __le32 offset;
  406. __u32 rsvd12[4];
  407. };
  408. struct nvme_format_cmd {
  409. __u8 opcode;
  410. __u8 flags;
  411. __u16 command_id;
  412. __le32 nsid;
  413. __u64 rsvd2[4];
  414. __le32 cdw10;
  415. __u32 rsvd11[5];
  416. };
  417. struct nvme_command {
  418. union {
  419. struct nvme_common_command common;
  420. struct nvme_rw_command rw;
  421. struct nvme_identify identify;
  422. struct nvme_features features;
  423. struct nvme_create_cq create_cq;
  424. struct nvme_create_sq create_sq;
  425. struct nvme_delete_queue delete_queue;
  426. struct nvme_download_firmware dlfw;
  427. struct nvme_format_cmd format;
  428. struct nvme_dsm_cmd dsm;
  429. struct nvme_abort_cmd abort;
  430. };
  431. };
  432. enum {
  433. NVME_SC_SUCCESS = 0x0,
  434. NVME_SC_INVALID_OPCODE = 0x1,
  435. NVME_SC_INVALID_FIELD = 0x2,
  436. NVME_SC_CMDID_CONFLICT = 0x3,
  437. NVME_SC_DATA_XFER_ERROR = 0x4,
  438. NVME_SC_POWER_LOSS = 0x5,
  439. NVME_SC_INTERNAL = 0x6,
  440. NVME_SC_ABORT_REQ = 0x7,
  441. NVME_SC_ABORT_QUEUE = 0x8,
  442. NVME_SC_FUSED_FAIL = 0x9,
  443. NVME_SC_FUSED_MISSING = 0xa,
  444. NVME_SC_INVALID_NS = 0xb,
  445. NVME_SC_CMD_SEQ_ERROR = 0xc,
  446. NVME_SC_SGL_INVALID_LAST = 0xd,
  447. NVME_SC_SGL_INVALID_COUNT = 0xe,
  448. NVME_SC_SGL_INVALID_DATA = 0xf,
  449. NVME_SC_SGL_INVALID_METADATA = 0x10,
  450. NVME_SC_SGL_INVALID_TYPE = 0x11,
  451. NVME_SC_LBA_RANGE = 0x80,
  452. NVME_SC_CAP_EXCEEDED = 0x81,
  453. NVME_SC_NS_NOT_READY = 0x82,
  454. NVME_SC_RESERVATION_CONFLICT = 0x83,
  455. NVME_SC_CQ_INVALID = 0x100,
  456. NVME_SC_QID_INVALID = 0x101,
  457. NVME_SC_QUEUE_SIZE = 0x102,
  458. NVME_SC_ABORT_LIMIT = 0x103,
  459. NVME_SC_ABORT_MISSING = 0x104,
  460. NVME_SC_ASYNC_LIMIT = 0x105,
  461. NVME_SC_FIRMWARE_SLOT = 0x106,
  462. NVME_SC_FIRMWARE_IMAGE = 0x107,
  463. NVME_SC_INVALID_VECTOR = 0x108,
  464. NVME_SC_INVALID_LOG_PAGE = 0x109,
  465. NVME_SC_INVALID_FORMAT = 0x10a,
  466. NVME_SC_FIRMWARE_NEEDS_RESET = 0x10b,
  467. NVME_SC_INVALID_QUEUE = 0x10c,
  468. NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
  469. NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
  470. NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
  471. NVME_SC_FW_NEEDS_RESET_SUBSYS = 0x110,
  472. NVME_SC_BAD_ATTRIBUTES = 0x180,
  473. NVME_SC_INVALID_PI = 0x181,
  474. NVME_SC_READ_ONLY = 0x182,
  475. NVME_SC_WRITE_FAULT = 0x280,
  476. NVME_SC_READ_ERROR = 0x281,
  477. NVME_SC_GUARD_CHECK = 0x282,
  478. NVME_SC_APPTAG_CHECK = 0x283,
  479. NVME_SC_REFTAG_CHECK = 0x284,
  480. NVME_SC_COMPARE_FAILED = 0x285,
  481. NVME_SC_ACCESS_DENIED = 0x286,
  482. NVME_SC_DNR = 0x4000,
  483. };
  484. struct nvme_completion {
  485. __le32 result; /* Used by admin commands to return data */
  486. __u32 rsvd;
  487. __le16 sq_head; /* how much of this queue may be reclaimed */
  488. __le16 sq_id; /* submission queue that generated this entry */
  489. __u16 command_id; /* of the command which completed */
  490. __le16 status; /* did the command fail, and if so, why? */
  491. };
  492. /*
  493. * Registers should always be accessed with double word or quad word
  494. * accesses. Registers with 64-bit address pointers should be written
  495. * to with dword accesses by writing the low dword first (ptr[0]),
  496. * then the high dword (ptr[1]) second.
  497. */
  498. static inline u64 nvme_readq(__le64 volatile *regs)
  499. {
  500. __u32 *ptr = (__u32 *)regs;
  501. u64 val_lo = readl(ptr);
  502. u64 val_hi = readl(ptr + 1);
  503. return val_lo + (val_hi << 32);
  504. }
  505. static inline void nvme_writeq(const u64 val, __le64 volatile *regs)
  506. {
  507. __u32 *ptr = (__u32 *)regs;
  508. u32 val_lo = lower_32_bits(val);
  509. u32 val_hi = upper_32_bits(val);
  510. writel(val_lo, ptr);
  511. writel(val_hi, ptr + 1);
  512. }
  513. struct nvme_bar {
  514. __u64 cap; /* Controller Capabilities */
  515. __u32 vs; /* Version */
  516. __u32 intms; /* Interrupt Mask Set */
  517. __u32 intmc; /* Interrupt Mask Clear */
  518. __u32 cc; /* Controller Configuration */
  519. __u32 rsvd1; /* Reserved */
  520. __u32 csts; /* Controller Status */
  521. __u32 rsvd2; /* Reserved */
  522. __u32 aqa; /* Admin Queue Attributes */
  523. __u64 asq; /* Admin SQ Base Address */
  524. __u64 acq; /* Admin CQ Base Address */
  525. };
  526. #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
  527. #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
  528. #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
  529. #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
  530. #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
  531. #define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8))
  532. enum {
  533. NVME_CC_ENABLE = 1 << 0,
  534. NVME_CC_CSS_NVM = 0 << 4,
  535. NVME_CC_MPS_SHIFT = 7,
  536. NVME_CC_ARB_RR = 0 << 11,
  537. NVME_CC_ARB_WRRU = 1 << 11,
  538. NVME_CC_ARB_VS = 7 << 11,
  539. NVME_CC_SHN_NONE = 0 << 14,
  540. NVME_CC_SHN_NORMAL = 1 << 14,
  541. NVME_CC_SHN_ABRUPT = 2 << 14,
  542. NVME_CC_SHN_MASK = 3 << 14,
  543. NVME_CC_IOSQES = 6 << 16,
  544. NVME_CC_IOCQES = 4 << 20,
  545. NVME_CSTS_RDY = 1 << 0,
  546. NVME_CSTS_CFS = 1 << 1,
  547. NVME_CSTS_SHST_NORMAL = 0 << 2,
  548. NVME_CSTS_SHST_OCCUR = 1 << 2,
  549. NVME_CSTS_SHST_CMPLT = 2 << 2,
  550. NVME_CSTS_SHST_MASK = 3 << 2,
  551. };
  552. /* Represents an NVM Express device. Each nvme_dev is a PCI function. */
  553. struct nvme_dev {
  554. struct list_head node;
  555. struct nvme_queue **queues;
  556. u32 __iomem *dbs;
  557. int instance;
  558. unsigned queue_count;
  559. unsigned online_queues;
  560. unsigned max_qid;
  561. int q_depth;
  562. u32 db_stride;
  563. u32 ctrl_config;
  564. struct nvme_bar __iomem *bar;
  565. struct list_head namespaces;
  566. char serial[20];
  567. char model[40];
  568. char firmware_rev[8];
  569. u32 max_transfer_shift;
  570. u64 cap;
  571. u32 stripe_size;
  572. u32 page_size;
  573. u8 vwc;
  574. u64 *prp_pool;
  575. u32 prp_entry_num;
  576. u32 nn;
  577. };
  578. /*
  579. * An NVM Express namespace is equivalent to a SCSI LUN.
  580. * Each namespace is operated as an independent "device".
  581. */
  582. struct nvme_ns {
  583. struct list_head list;
  584. struct nvme_dev *dev;
  585. unsigned ns_id;
  586. u8 eui64[8];
  587. int devnum;
  588. int lba_shift;
  589. u8 flbas;
  590. u64 mode_select_num_blocks;
  591. u32 mode_select_block_len;
  592. };
  593. #endif /* __DRIVER_NVME_H__ */