xilinx_axi_emac.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
  4. * Copyright (C) 2011 PetaLogix
  5. * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
  6. */
  7. #include <config.h>
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <net.h>
  13. #include <malloc.h>
  14. #include <asm/io.h>
  15. #include <phy.h>
  16. #include <miiphy.h>
  17. #include <wait_bit.h>
  18. #include <linux/delay.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /* Link setup */
  21. #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
  22. #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
  23. #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
  24. #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
  25. /* Interrupt Status/Enable/Mask Registers bit definitions */
  26. #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
  27. #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
  28. /* Receive Configuration Word 1 (RCW1) Register bit definitions */
  29. #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
  30. /* Transmitter Configuration (TC) Register bit definitions */
  31. #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
  32. #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
  33. /* MDIO Management Configuration (MC) Register bit definitions */
  34. #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
  35. /* MDIO Management Control Register (MCR) Register bit definitions */
  36. #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
  37. #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
  38. #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
  39. #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
  40. #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
  41. #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
  42. #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
  43. #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
  44. #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
  45. #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
  46. /* DMA macros */
  47. /* Bitmasks of XAXIDMA_CR_OFFSET register */
  48. #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
  49. #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
  50. /* Bitmasks of XAXIDMA_SR_OFFSET register */
  51. #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
  52. /* Bitmask for interrupts */
  53. #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
  54. #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
  55. #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
  56. /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
  57. #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
  58. #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
  59. #define DMAALIGN 128
  60. static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
  61. /* Reflect dma offsets */
  62. struct axidma_reg {
  63. u32 control; /* DMACR */
  64. u32 status; /* DMASR */
  65. u32 current; /* CURDESC low 32 bit */
  66. u32 current_hi; /* CURDESC high 32 bit */
  67. u32 tail; /* TAILDESC low 32 bit */
  68. u32 tail_hi; /* TAILDESC high 32 bit */
  69. };
  70. /* Private driver structures */
  71. struct axidma_priv {
  72. struct axidma_reg *dmatx;
  73. struct axidma_reg *dmarx;
  74. int phyaddr;
  75. struct axi_regs *iobase;
  76. phy_interface_t interface;
  77. struct phy_device *phydev;
  78. struct mii_dev *bus;
  79. u8 eth_hasnobuf;
  80. int phy_of_handle;
  81. };
  82. /* BD descriptors */
  83. struct axidma_bd {
  84. u32 next_desc; /* Next descriptor pointer */
  85. u32 next_desc_msb;
  86. u32 buf_addr; /* Buffer address */
  87. u32 buf_addr_msb;
  88. u32 reserved3;
  89. u32 reserved4;
  90. u32 cntrl; /* Control */
  91. u32 status; /* Status */
  92. u32 app0;
  93. u32 app1; /* TX start << 16 | insert */
  94. u32 app2; /* TX csum seed */
  95. u32 app3;
  96. u32 app4;
  97. u32 sw_id_offset;
  98. u32 reserved5;
  99. u32 reserved6;
  100. };
  101. /* Static BDs - driver uses only one BD */
  102. static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
  103. static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
  104. struct axi_regs {
  105. u32 reserved[3];
  106. u32 is; /* 0xC: Interrupt status */
  107. u32 reserved2;
  108. u32 ie; /* 0x14: Interrupt enable */
  109. u32 reserved3[251];
  110. u32 rcw1; /* 0x404: Rx Configuration Word 1 */
  111. u32 tc; /* 0x408: Tx Configuration */
  112. u32 reserved4;
  113. u32 emmc; /* 0x410: EMAC mode configuration */
  114. u32 reserved5[59];
  115. u32 mdio_mc; /* 0x500: MII Management Config */
  116. u32 mdio_mcr; /* 0x504: MII Management Control */
  117. u32 mdio_mwd; /* 0x508: MII Management Write Data */
  118. u32 mdio_mrd; /* 0x50C: MII Management Read Data */
  119. u32 reserved6[124];
  120. u32 uaw0; /* 0x700: Unicast address word 0 */
  121. u32 uaw1; /* 0x704: Unicast address word 1 */
  122. };
  123. /* Use MII register 1 (MII status register) to detect PHY */
  124. #define PHY_DETECT_REG 1
  125. /*
  126. * Mask used to verify certain PHY features (or register contents)
  127. * in the register above:
  128. * 0x1000: 10Mbps full duplex support
  129. * 0x0800: 10Mbps half duplex support
  130. * 0x0008: Auto-negotiation support
  131. */
  132. #define PHY_DETECT_MASK 0x1808
  133. static inline int mdio_wait(struct axi_regs *regs)
  134. {
  135. u32 timeout = 200;
  136. /* Wait till MDIO interface is ready to accept a new transaction. */
  137. while (timeout && (!(readl(&regs->mdio_mcr)
  138. & XAE_MDIO_MCR_READY_MASK))) {
  139. timeout--;
  140. udelay(1);
  141. }
  142. if (!timeout) {
  143. printf("%s: Timeout\n", __func__);
  144. return 1;
  145. }
  146. return 0;
  147. }
  148. /**
  149. * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
  150. * @bd: pointer to BD descriptor structure
  151. * @desc: Address offset of DMA descriptors
  152. *
  153. * This function writes the value into the corresponding Axi DMA register.
  154. */
  155. static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
  156. {
  157. #if defined(CONFIG_PHYS_64BIT)
  158. writeq((unsigned long)bd, desc);
  159. #else
  160. writel((u32)bd, desc);
  161. #endif
  162. }
  163. static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
  164. u16 *val)
  165. {
  166. struct axi_regs *regs = priv->iobase;
  167. u32 mdioctrlreg = 0;
  168. if (mdio_wait(regs))
  169. return 1;
  170. mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
  171. XAE_MDIO_MCR_PHYAD_MASK) |
  172. ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
  173. & XAE_MDIO_MCR_REGAD_MASK) |
  174. XAE_MDIO_MCR_INITIATE_MASK |
  175. XAE_MDIO_MCR_OP_READ_MASK;
  176. writel(mdioctrlreg, &regs->mdio_mcr);
  177. if (mdio_wait(regs))
  178. return 1;
  179. /* Read data */
  180. *val = readl(&regs->mdio_mrd);
  181. return 0;
  182. }
  183. static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
  184. u32 data)
  185. {
  186. struct axi_regs *regs = priv->iobase;
  187. u32 mdioctrlreg = 0;
  188. if (mdio_wait(regs))
  189. return 1;
  190. mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
  191. XAE_MDIO_MCR_PHYAD_MASK) |
  192. ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
  193. & XAE_MDIO_MCR_REGAD_MASK) |
  194. XAE_MDIO_MCR_INITIATE_MASK |
  195. XAE_MDIO_MCR_OP_WRITE_MASK;
  196. /* Write data */
  197. writel(data, &regs->mdio_mwd);
  198. writel(mdioctrlreg, &regs->mdio_mcr);
  199. if (mdio_wait(regs))
  200. return 1;
  201. return 0;
  202. }
  203. static int axiemac_phy_init(struct udevice *dev)
  204. {
  205. u16 phyreg;
  206. int i;
  207. u32 ret;
  208. struct axidma_priv *priv = dev_get_priv(dev);
  209. struct axi_regs *regs = priv->iobase;
  210. struct phy_device *phydev;
  211. u32 supported = SUPPORTED_10baseT_Half |
  212. SUPPORTED_10baseT_Full |
  213. SUPPORTED_100baseT_Half |
  214. SUPPORTED_100baseT_Full |
  215. SUPPORTED_1000baseT_Half |
  216. SUPPORTED_1000baseT_Full;
  217. /* Set default MDIO divisor */
  218. writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
  219. if (priv->phyaddr == -1) {
  220. /* Detect the PHY address */
  221. for (i = 31; i >= 0; i--) {
  222. ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
  223. if (!ret && (phyreg != 0xFFFF) &&
  224. ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
  225. /* Found a valid PHY address */
  226. priv->phyaddr = i;
  227. debug("axiemac: Found valid phy address, %x\n",
  228. i);
  229. break;
  230. }
  231. }
  232. }
  233. /* Interface - look at tsec */
  234. phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
  235. phydev->supported &= supported;
  236. phydev->advertising = phydev->supported;
  237. priv->phydev = phydev;
  238. if (priv->phy_of_handle)
  239. priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
  240. phy_config(phydev);
  241. return 0;
  242. }
  243. /* Setting axi emac and phy to proper setting */
  244. static int setup_phy(struct udevice *dev)
  245. {
  246. u16 temp;
  247. u32 speed, emmc_reg, ret;
  248. struct axidma_priv *priv = dev_get_priv(dev);
  249. struct axi_regs *regs = priv->iobase;
  250. struct phy_device *phydev = priv->phydev;
  251. if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
  252. /*
  253. * In SGMII cases the isolate bit might set
  254. * after DMA and ethernet resets and hence
  255. * check and clear if set.
  256. */
  257. ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
  258. if (ret)
  259. return 0;
  260. if (temp & BMCR_ISOLATE) {
  261. temp &= ~BMCR_ISOLATE;
  262. ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
  263. if (ret)
  264. return 0;
  265. }
  266. }
  267. if (phy_startup(phydev)) {
  268. printf("axiemac: could not initialize PHY %s\n",
  269. phydev->dev->name);
  270. return 0;
  271. }
  272. if (!phydev->link) {
  273. printf("%s: No link.\n", phydev->dev->name);
  274. return 0;
  275. }
  276. switch (phydev->speed) {
  277. case 1000:
  278. speed = XAE_EMMC_LINKSPD_1000;
  279. break;
  280. case 100:
  281. speed = XAE_EMMC_LINKSPD_100;
  282. break;
  283. case 10:
  284. speed = XAE_EMMC_LINKSPD_10;
  285. break;
  286. default:
  287. return 0;
  288. }
  289. /* Setup the emac for the phy speed */
  290. emmc_reg = readl(&regs->emmc);
  291. emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
  292. emmc_reg |= speed;
  293. /* Write new speed setting out to Axi Ethernet */
  294. writel(emmc_reg, &regs->emmc);
  295. /*
  296. * Setting the operating speed of the MAC needs a delay. There
  297. * doesn't seem to be register to poll, so please consider this
  298. * during your application design.
  299. */
  300. udelay(1);
  301. return 1;
  302. }
  303. /* STOP DMA transfers */
  304. static void axiemac_stop(struct udevice *dev)
  305. {
  306. struct axidma_priv *priv = dev_get_priv(dev);
  307. u32 temp;
  308. /* Stop the hardware */
  309. temp = readl(&priv->dmatx->control);
  310. temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
  311. writel(temp, &priv->dmatx->control);
  312. temp = readl(&priv->dmarx->control);
  313. temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
  314. writel(temp, &priv->dmarx->control);
  315. debug("axiemac: Halted\n");
  316. }
  317. static int axi_ethernet_init(struct axidma_priv *priv)
  318. {
  319. struct axi_regs *regs = priv->iobase;
  320. int err;
  321. /*
  322. * Check the status of the MgtRdy bit in the interrupt status
  323. * registers. This must be done to allow the MGT clock to become stable
  324. * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
  325. * will be valid until this bit is valid.
  326. * The bit is always a 1 for all other PHY interfaces.
  327. * Interrupt status and enable registers are not available in non
  328. * processor mode and hence bypass in this mode
  329. */
  330. if (!priv->eth_hasnobuf) {
  331. err = wait_for_bit_le32(&regs->is, XAE_INT_MGTRDY_MASK,
  332. true, 200, false);
  333. if (err) {
  334. printf("%s: Timeout\n", __func__);
  335. return 1;
  336. }
  337. /*
  338. * Stop the device and reset HW
  339. * Disable interrupts
  340. */
  341. writel(0, &regs->ie);
  342. }
  343. /* Disable the receiver */
  344. writel(readl(&regs->rcw1) & ~XAE_RCW1_RX_MASK, &regs->rcw1);
  345. /*
  346. * Stopping the receiver in mid-packet causes a dropped packet
  347. * indication from HW. Clear it.
  348. */
  349. if (!priv->eth_hasnobuf) {
  350. /* Set the interrupt status register to clear the interrupt */
  351. writel(XAE_INT_RXRJECT_MASK, &regs->is);
  352. }
  353. /* Setup HW */
  354. /* Set default MDIO divisor */
  355. writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
  356. debug("axiemac: InitHw done\n");
  357. return 0;
  358. }
  359. static int axiemac_write_hwaddr(struct udevice *dev)
  360. {
  361. struct eth_pdata *pdata = dev_get_platdata(dev);
  362. struct axidma_priv *priv = dev_get_priv(dev);
  363. struct axi_regs *regs = priv->iobase;
  364. /* Set the MAC address */
  365. int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
  366. (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
  367. writel(val, &regs->uaw0);
  368. val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
  369. val |= readl(&regs->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
  370. writel(val, &regs->uaw1);
  371. return 0;
  372. }
  373. /* Reset DMA engine */
  374. static void axi_dma_init(struct axidma_priv *priv)
  375. {
  376. u32 timeout = 500;
  377. /* Reset the engine so the hardware starts from a known state */
  378. writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
  379. writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
  380. /* At the initialization time, hardware should finish reset quickly */
  381. while (timeout--) {
  382. /* Check transmit/receive channel */
  383. /* Reset is done when the reset bit is low */
  384. if (!((readl(&priv->dmatx->control) |
  385. readl(&priv->dmarx->control))
  386. & XAXIDMA_CR_RESET_MASK)) {
  387. break;
  388. }
  389. }
  390. if (!timeout)
  391. printf("%s: Timeout\n", __func__);
  392. }
  393. static int axiemac_start(struct udevice *dev)
  394. {
  395. struct axidma_priv *priv = dev_get_priv(dev);
  396. struct axi_regs *regs = priv->iobase;
  397. u32 temp;
  398. debug("axiemac: Init started\n");
  399. /*
  400. * Initialize AXIDMA engine. AXIDMA engine must be initialized before
  401. * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
  402. * reset, and since AXIDMA reset line is connected to AxiEthernet, this
  403. * would ensure a reset of AxiEthernet.
  404. */
  405. axi_dma_init(priv);
  406. /* Initialize AxiEthernet hardware. */
  407. if (axi_ethernet_init(priv))
  408. return -1;
  409. /* Disable all RX interrupts before RxBD space setup */
  410. temp = readl(&priv->dmarx->control);
  411. temp &= ~XAXIDMA_IRQ_ALL_MASK;
  412. writel(temp, &priv->dmarx->control);
  413. /* Start DMA RX channel. Now it's ready to receive data.*/
  414. axienet_dma_write(&rx_bd, &priv->dmarx->current);
  415. /* Setup the BD. */
  416. memset(&rx_bd, 0, sizeof(rx_bd));
  417. rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
  418. rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
  419. #if defined(CONFIG_PHYS_64BIT)
  420. rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
  421. rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
  422. #endif
  423. rx_bd.cntrl = sizeof(rxframe);
  424. /* Flush the last BD so DMA core could see the updates */
  425. flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
  426. /* It is necessary to flush rxframe because if you don't do it
  427. * then cache can contain uninitialized data */
  428. flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
  429. /* Start the hardware */
  430. temp = readl(&priv->dmarx->control);
  431. temp |= XAXIDMA_CR_RUNSTOP_MASK;
  432. writel(temp, &priv->dmarx->control);
  433. /* Rx BD is ready - start */
  434. axienet_dma_write(&rx_bd, &priv->dmarx->tail);
  435. /* Enable TX */
  436. writel(XAE_TC_TX_MASK, &regs->tc);
  437. /* Enable RX */
  438. writel(XAE_RCW1_RX_MASK, &regs->rcw1);
  439. /* PHY setup */
  440. if (!setup_phy(dev)) {
  441. axiemac_stop(dev);
  442. return -1;
  443. }
  444. debug("axiemac: Init complete\n");
  445. return 0;
  446. }
  447. static int axiemac_send(struct udevice *dev, void *ptr, int len)
  448. {
  449. struct axidma_priv *priv = dev_get_priv(dev);
  450. u32 timeout;
  451. if (len > PKTSIZE_ALIGN)
  452. len = PKTSIZE_ALIGN;
  453. /* Flush packet to main memory to be trasfered by DMA */
  454. flush_cache((phys_addr_t)ptr, len);
  455. /* Setup Tx BD */
  456. memset(&tx_bd, 0, sizeof(tx_bd));
  457. /* At the end of the ring, link the last BD back to the top */
  458. tx_bd.next_desc = lower_32_bits((unsigned long)&tx_bd);
  459. tx_bd.buf_addr = lower_32_bits((unsigned long)ptr);
  460. #if defined(CONFIG_PHYS_64BIT)
  461. tx_bd.next_desc_msb = upper_32_bits((unsigned long)&tx_bd);
  462. tx_bd.buf_addr_msb = upper_32_bits((unsigned long)ptr);
  463. #endif
  464. /* Save len */
  465. tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
  466. XAXIDMA_BD_CTRL_TXEOF_MASK;
  467. /* Flush the last BD so DMA core could see the updates */
  468. flush_cache((phys_addr_t)&tx_bd, sizeof(tx_bd));
  469. if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
  470. u32 temp;
  471. axienet_dma_write(&tx_bd, &priv->dmatx->current);
  472. /* Start the hardware */
  473. temp = readl(&priv->dmatx->control);
  474. temp |= XAXIDMA_CR_RUNSTOP_MASK;
  475. writel(temp, &priv->dmatx->control);
  476. }
  477. /* Start transfer */
  478. axienet_dma_write(&tx_bd, &priv->dmatx->tail);
  479. /* Wait for transmission to complete */
  480. debug("axiemac: Waiting for tx to be done\n");
  481. timeout = 200;
  482. while (timeout && (!(readl(&priv->dmatx->status) &
  483. (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
  484. timeout--;
  485. udelay(1);
  486. }
  487. if (!timeout) {
  488. printf("%s: Timeout\n", __func__);
  489. return 1;
  490. }
  491. debug("axiemac: Sending complete\n");
  492. return 0;
  493. }
  494. static int isrxready(struct axidma_priv *priv)
  495. {
  496. u32 status;
  497. /* Read pending interrupts */
  498. status = readl(&priv->dmarx->status);
  499. /* Acknowledge pending interrupts */
  500. writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
  501. /*
  502. * If Reception done interrupt is asserted, call RX call back function
  503. * to handle the processed BDs and then raise the according flag.
  504. */
  505. if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
  506. return 1;
  507. return 0;
  508. }
  509. static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
  510. {
  511. u32 length;
  512. struct axidma_priv *priv = dev_get_priv(dev);
  513. u32 temp;
  514. /* Wait for an incoming packet */
  515. if (!isrxready(priv))
  516. return -1;
  517. debug("axiemac: RX data ready\n");
  518. /* Disable IRQ for a moment till packet is handled */
  519. temp = readl(&priv->dmarx->control);
  520. temp &= ~XAXIDMA_IRQ_ALL_MASK;
  521. writel(temp, &priv->dmarx->control);
  522. if (!priv->eth_hasnobuf)
  523. length = rx_bd.app4 & 0xFFFF; /* max length mask */
  524. else
  525. length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
  526. #ifdef DEBUG
  527. print_buffer(&rxframe, &rxframe[0], 1, length, 16);
  528. #endif
  529. *packetp = rxframe;
  530. return length;
  531. }
  532. static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
  533. {
  534. struct axidma_priv *priv = dev_get_priv(dev);
  535. #ifdef DEBUG
  536. /* It is useful to clear buffer to be sure that it is consistent */
  537. memset(rxframe, 0, sizeof(rxframe));
  538. #endif
  539. /* Setup RxBD */
  540. /* Clear the whole buffer and setup it again - all flags are cleared */
  541. memset(&rx_bd, 0, sizeof(rx_bd));
  542. rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
  543. rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
  544. #if defined(CONFIG_PHYS_64BIT)
  545. rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
  546. rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
  547. #endif
  548. rx_bd.cntrl = sizeof(rxframe);
  549. /* Write bd to HW */
  550. flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
  551. /* It is necessary to flush rxframe because if you don't do it
  552. * then cache will contain previous packet */
  553. flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
  554. /* Rx BD is ready - start again */
  555. axienet_dma_write(&rx_bd, &priv->dmarx->tail);
  556. debug("axiemac: RX completed, framelength = %d\n", length);
  557. return 0;
  558. }
  559. static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
  560. int devad, int reg)
  561. {
  562. int ret;
  563. u16 value;
  564. ret = phyread(bus->priv, addr, reg, &value);
  565. debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
  566. value, ret);
  567. return value;
  568. }
  569. static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
  570. int reg, u16 value)
  571. {
  572. debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
  573. return phywrite(bus->priv, addr, reg, value);
  574. }
  575. static int axi_emac_probe(struct udevice *dev)
  576. {
  577. struct axidma_priv *priv = dev_get_priv(dev);
  578. int ret;
  579. priv->bus = mdio_alloc();
  580. priv->bus->read = axiemac_miiphy_read;
  581. priv->bus->write = axiemac_miiphy_write;
  582. priv->bus->priv = priv;
  583. ret = mdio_register_seq(priv->bus, dev->seq);
  584. if (ret)
  585. return ret;
  586. axiemac_phy_init(dev);
  587. return 0;
  588. }
  589. static int axi_emac_remove(struct udevice *dev)
  590. {
  591. struct axidma_priv *priv = dev_get_priv(dev);
  592. free(priv->phydev);
  593. mdio_unregister(priv->bus);
  594. mdio_free(priv->bus);
  595. return 0;
  596. }
  597. static const struct eth_ops axi_emac_ops = {
  598. .start = axiemac_start,
  599. .send = axiemac_send,
  600. .recv = axiemac_recv,
  601. .free_pkt = axiemac_free_pkt,
  602. .stop = axiemac_stop,
  603. .write_hwaddr = axiemac_write_hwaddr,
  604. };
  605. static int axi_emac_ofdata_to_platdata(struct udevice *dev)
  606. {
  607. struct eth_pdata *pdata = dev_get_platdata(dev);
  608. struct axidma_priv *priv = dev_get_priv(dev);
  609. int node = dev_of_offset(dev);
  610. int offset = 0;
  611. const char *phy_mode;
  612. pdata->iobase = dev_read_addr(dev);
  613. priv->iobase = (struct axi_regs *)pdata->iobase;
  614. offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
  615. "axistream-connected");
  616. if (offset <= 0) {
  617. printf("%s: axistream is not found\n", __func__);
  618. return -EINVAL;
  619. }
  620. priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
  621. offset, "reg");
  622. if (!priv->dmatx) {
  623. printf("%s: axi_dma register space not found\n", __func__);
  624. return -EINVAL;
  625. }
  626. /* RX channel offset is 0x30 */
  627. priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
  628. priv->phyaddr = -1;
  629. offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
  630. if (offset > 0) {
  631. priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
  632. priv->phy_of_handle = offset;
  633. }
  634. phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
  635. if (phy_mode)
  636. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  637. if (pdata->phy_interface == -1) {
  638. printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  639. return -EINVAL;
  640. }
  641. priv->interface = pdata->phy_interface;
  642. priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
  643. "xlnx,eth-hasnobuf");
  644. printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
  645. priv->phyaddr, phy_string_for_interface(priv->interface));
  646. return 0;
  647. }
  648. static const struct udevice_id axi_emac_ids[] = {
  649. { .compatible = "xlnx,axi-ethernet-1.00.a" },
  650. { }
  651. };
  652. U_BOOT_DRIVER(axi_emac) = {
  653. .name = "axi_emac",
  654. .id = UCLASS_ETH,
  655. .of_match = axi_emac_ids,
  656. .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
  657. .probe = axi_emac_probe,
  658. .remove = axi_emac_remove,
  659. .ops = &axi_emac_ops,
  660. .priv_auto_alloc_size = sizeof(struct axidma_priv),
  661. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  662. };