vsc7385.c 2.3 KB

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  1. /*
  2. * Vitesse 7385 Switch Firmware Upload
  3. *
  4. * Author: Timur Tabi <timur@freescale.com>
  5. *
  6. * Copyright 2008 Freescale Semiconductor, Inc. This file is licensed
  7. * under the terms of the GNU General Public License version 2. This
  8. * program is licensed "as is" without any warranty of any kind, whether
  9. * express or implied.
  10. *
  11. * This module uploads proprietary firmware for the Vitesse VSC7385 5-port
  12. * switch.
  13. */
  14. #include <config.h>
  15. #include <common.h>
  16. #include <console.h>
  17. #include <log.h>
  18. #include <asm/io.h>
  19. #include <linux/delay.h>
  20. #include <linux/errno.h>
  21. #include "vsc7385.h"
  22. /*
  23. * Upload a Vitesse VSC7385 firmware image to the hardware
  24. *
  25. * This function takes a pointer to a VSC7385 firmware image and a size, and
  26. * uploads that firmware to the VSC7385.
  27. *
  28. * This firmware is typically located at a board-specific flash address,
  29. * and the size is typically 8KB.
  30. *
  31. * The firmware is Vitesse proprietary.
  32. *
  33. * Further details on the register information can be obtained from Vitesse.
  34. */
  35. int vsc7385_upload_firmware(void *firmware, unsigned int size)
  36. {
  37. u8 *fw = firmware;
  38. unsigned int i;
  39. u32 *gloreset = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c050);
  40. u32 *icpu_ctrl = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c040);
  41. u32 *icpu_addr = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c044);
  42. u32 *icpu_data = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c048);
  43. u32 *icpu_rom_map = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c070);
  44. #ifdef DEBUG
  45. u32 *chipid = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c060);
  46. #endif
  47. out_be32(gloreset, 3);
  48. udelay(200);
  49. out_be32(icpu_ctrl, 0x8E);
  50. udelay(20);
  51. out_be32(icpu_rom_map, 1);
  52. udelay(20);
  53. /* Write the firmware to I-RAM */
  54. out_be32(icpu_addr, 0);
  55. udelay(20);
  56. for (i = 0; i < size; i++) {
  57. out_be32(icpu_data, fw[i]);
  58. udelay(20);
  59. if (ctrlc())
  60. return -EINTR;
  61. }
  62. /* Read back and compare */
  63. out_be32(icpu_addr, 0);
  64. udelay(20);
  65. for (i = 0; i < size; i++) {
  66. u8 value;
  67. value = (u8) in_be32(icpu_data);
  68. udelay(20);
  69. if (value != fw[i]) {
  70. debug("VSC7385: Upload mismatch: address 0x%x, "
  71. "read value 0x%x, image value 0x%x\n",
  72. i, value, fw[i]);
  73. return -EIO;
  74. }
  75. if (ctrlc())
  76. break;
  77. }
  78. out_be32(icpu_ctrl, 0x0B);
  79. udelay(20);
  80. #ifdef DEBUG
  81. printf("VSC7385: Chip ID is %08x\n", in_be32(chipid));
  82. udelay(20);
  83. #endif
  84. return 0;
  85. }