davinci_emac.h 7.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
  4. *
  5. * Based on: mach-davinci/emac_defs.h
  6. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  7. */
  8. #ifndef _DAVINCI_EMAC_H_
  9. #define _DAVINCI_EMAC_H_
  10. /* Ethernet Min/Max packet size */
  11. #define EMAC_MIN_ETHERNET_PKT_SIZE 60
  12. #define EMAC_MAX_ETHERNET_PKT_SIZE 1518
  13. /* Buffer size (should be aligned on 32 byte and cache line) */
  14. #define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\
  15. ARCH_DMA_MINALIGN)
  16. /* Number of RX packet buffers
  17. * NOTE: Only 1 buffer supported as of now
  18. */
  19. #define EMAC_MAX_RX_BUFFERS 10
  20. /***********************************************
  21. ******** Internally used macros ***************
  22. ***********************************************/
  23. #define EMAC_CH_TX 1
  24. #define EMAC_CH_RX 0
  25. /* Each descriptor occupies 4 words, lets start RX desc's at 0 and
  26. * reserve space for 64 descriptors max
  27. */
  28. #define EMAC_RX_DESC_BASE 0x0
  29. #define EMAC_TX_DESC_BASE 0x1000
  30. /* EMAC Teardown value */
  31. #define EMAC_TEARDOWN_VALUE 0xfffffffc
  32. /* MII Status Register */
  33. #define MII_STATUS_REG 1
  34. /* PHY Configuration register */
  35. #define PHY_CONF_TXCLKEN (1 << 5)
  36. /* Number of statistics registers */
  37. #define EMAC_NUM_STATS 36
  38. /* EMAC Descriptor */
  39. typedef volatile struct _emac_desc
  40. {
  41. u_int32_t next; /* Pointer to next descriptor
  42. in chain */
  43. u_int8_t *buffer; /* Pointer to data buffer */
  44. u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
  45. u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
  46. } emac_desc;
  47. /* CPPI bit positions */
  48. #define EMAC_CPPI_SOP_BIT (0x80000000)
  49. #define EMAC_CPPI_EOP_BIT (0x40000000)
  50. #define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
  51. #define EMAC_CPPI_EOQ_BIT (0x10000000)
  52. #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
  53. #define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
  54. #define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
  55. #define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
  56. #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
  57. #define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
  58. #define EMAC_MACCONTROL_GIGFORCE (1 << 17)
  59. #define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
  60. #define EMAC_MAC_ADDR_MATCH (1 << 19)
  61. #define EMAC_MAC_ADDR_IS_VALID (1 << 20)
  62. #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
  63. #define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
  64. #define MDIO_CONTROL_IDLE (0x80000000)
  65. #define MDIO_CONTROL_ENABLE (0x40000000)
  66. #define MDIO_CONTROL_FAULT_ENABLE (0x40000)
  67. #define MDIO_CONTROL_FAULT (0x80000)
  68. #define MDIO_USERACCESS0_GO (0x80000000)
  69. #define MDIO_USERACCESS0_WRITE_READ (0x0)
  70. #define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
  71. #define MDIO_USERACCESS0_ACK (0x20000000)
  72. /* Ethernet MAC Registers Structure */
  73. typedef struct {
  74. dv_reg TXIDVER;
  75. dv_reg TXCONTROL;
  76. dv_reg TXTEARDOWN;
  77. u_int8_t RSVD0[4];
  78. dv_reg RXIDVER;
  79. dv_reg RXCONTROL;
  80. dv_reg RXTEARDOWN;
  81. u_int8_t RSVD1[100];
  82. dv_reg TXINTSTATRAW;
  83. dv_reg TXINTSTATMASKED;
  84. dv_reg TXINTMASKSET;
  85. dv_reg TXINTMASKCLEAR;
  86. dv_reg MACINVECTOR;
  87. u_int8_t RSVD2[12];
  88. dv_reg RXINTSTATRAW;
  89. dv_reg RXINTSTATMASKED;
  90. dv_reg RXINTMASKSET;
  91. dv_reg RXINTMASKCLEAR;
  92. dv_reg MACINTSTATRAW;
  93. dv_reg MACINTSTATMASKED;
  94. dv_reg MACINTMASKSET;
  95. dv_reg MACINTMASKCLEAR;
  96. u_int8_t RSVD3[64];
  97. dv_reg RXMBPENABLE;
  98. dv_reg RXUNICASTSET;
  99. dv_reg RXUNICASTCLEAR;
  100. dv_reg RXMAXLEN;
  101. dv_reg RXBUFFEROFFSET;
  102. dv_reg RXFILTERLOWTHRESH;
  103. u_int8_t RSVD4[8];
  104. dv_reg RX0FLOWTHRESH;
  105. dv_reg RX1FLOWTHRESH;
  106. dv_reg RX2FLOWTHRESH;
  107. dv_reg RX3FLOWTHRESH;
  108. dv_reg RX4FLOWTHRESH;
  109. dv_reg RX5FLOWTHRESH;
  110. dv_reg RX6FLOWTHRESH;
  111. dv_reg RX7FLOWTHRESH;
  112. dv_reg RX0FREEBUFFER;
  113. dv_reg RX1FREEBUFFER;
  114. dv_reg RX2FREEBUFFER;
  115. dv_reg RX3FREEBUFFER;
  116. dv_reg RX4FREEBUFFER;
  117. dv_reg RX5FREEBUFFER;
  118. dv_reg RX6FREEBUFFER;
  119. dv_reg RX7FREEBUFFER;
  120. dv_reg MACCONTROL;
  121. dv_reg MACSTATUS;
  122. dv_reg EMCONTROL;
  123. dv_reg FIFOCONTROL;
  124. dv_reg MACCONFIG;
  125. dv_reg SOFTRESET;
  126. u_int8_t RSVD5[88];
  127. dv_reg MACSRCADDRLO;
  128. dv_reg MACSRCADDRHI;
  129. dv_reg MACHASH1;
  130. dv_reg MACHASH2;
  131. dv_reg BOFFTEST;
  132. dv_reg TPACETEST;
  133. dv_reg RXPAUSE;
  134. dv_reg TXPAUSE;
  135. u_int8_t RSVD6[16];
  136. dv_reg RXGOODFRAMES;
  137. dv_reg RXBCASTFRAMES;
  138. dv_reg RXMCASTFRAMES;
  139. dv_reg RXPAUSEFRAMES;
  140. dv_reg RXCRCERRORS;
  141. dv_reg RXALIGNCODEERRORS;
  142. dv_reg RXOVERSIZED;
  143. dv_reg RXJABBER;
  144. dv_reg RXUNDERSIZED;
  145. dv_reg RXFRAGMENTS;
  146. dv_reg RXFILTERED;
  147. dv_reg RXQOSFILTERED;
  148. dv_reg RXOCTETS;
  149. dv_reg TXGOODFRAMES;
  150. dv_reg TXBCASTFRAMES;
  151. dv_reg TXMCASTFRAMES;
  152. dv_reg TXPAUSEFRAMES;
  153. dv_reg TXDEFERRED;
  154. dv_reg TXCOLLISION;
  155. dv_reg TXSINGLECOLL;
  156. dv_reg TXMULTICOLL;
  157. dv_reg TXEXCESSIVECOLL;
  158. dv_reg TXLATECOLL;
  159. dv_reg TXUNDERRUN;
  160. dv_reg TXCARRIERSENSE;
  161. dv_reg TXOCTETS;
  162. dv_reg FRAME64;
  163. dv_reg FRAME65T127;
  164. dv_reg FRAME128T255;
  165. dv_reg FRAME256T511;
  166. dv_reg FRAME512T1023;
  167. dv_reg FRAME1024TUP;
  168. dv_reg NETOCTETS;
  169. dv_reg RXSOFOVERRUNS;
  170. dv_reg RXMOFOVERRUNS;
  171. dv_reg RXDMAOVERRUNS;
  172. u_int8_t RSVD7[624];
  173. dv_reg MACADDRLO;
  174. dv_reg MACADDRHI;
  175. dv_reg MACINDEX;
  176. u_int8_t RSVD8[244];
  177. dv_reg TX0HDP;
  178. dv_reg TX1HDP;
  179. dv_reg TX2HDP;
  180. dv_reg TX3HDP;
  181. dv_reg TX4HDP;
  182. dv_reg TX5HDP;
  183. dv_reg TX6HDP;
  184. dv_reg TX7HDP;
  185. dv_reg RX0HDP;
  186. dv_reg RX1HDP;
  187. dv_reg RX2HDP;
  188. dv_reg RX3HDP;
  189. dv_reg RX4HDP;
  190. dv_reg RX5HDP;
  191. dv_reg RX6HDP;
  192. dv_reg RX7HDP;
  193. dv_reg TX0CP;
  194. dv_reg TX1CP;
  195. dv_reg TX2CP;
  196. dv_reg TX3CP;
  197. dv_reg TX4CP;
  198. dv_reg TX5CP;
  199. dv_reg TX6CP;
  200. dv_reg TX7CP;
  201. dv_reg RX0CP;
  202. dv_reg RX1CP;
  203. dv_reg RX2CP;
  204. dv_reg RX3CP;
  205. dv_reg RX4CP;
  206. dv_reg RX5CP;
  207. dv_reg RX6CP;
  208. dv_reg RX7CP;
  209. } emac_regs;
  210. /* EMAC Wrapper Registers Structure */
  211. typedef struct {
  212. #ifdef DAVINCI_EMAC_VERSION2
  213. dv_reg idver;
  214. dv_reg softrst;
  215. dv_reg emctrl;
  216. dv_reg c0rxthreshen;
  217. dv_reg c0rxen;
  218. dv_reg c0txen;
  219. dv_reg c0miscen;
  220. dv_reg c1rxthreshen;
  221. dv_reg c1rxen;
  222. dv_reg c1txen;
  223. dv_reg c1miscen;
  224. dv_reg c2rxthreshen;
  225. dv_reg c2rxen;
  226. dv_reg c2txen;
  227. dv_reg c2miscen;
  228. dv_reg c0rxthreshstat;
  229. dv_reg c0rxstat;
  230. dv_reg c0txstat;
  231. dv_reg c0miscstat;
  232. dv_reg c1rxthreshstat;
  233. dv_reg c1rxstat;
  234. dv_reg c1txstat;
  235. dv_reg c1miscstat;
  236. dv_reg c2rxthreshstat;
  237. dv_reg c2rxstat;
  238. dv_reg c2txstat;
  239. dv_reg c2miscstat;
  240. dv_reg c0rximax;
  241. dv_reg c0tximax;
  242. dv_reg c1rximax;
  243. dv_reg c1tximax;
  244. dv_reg c2rximax;
  245. dv_reg c2tximax;
  246. #else
  247. u_int8_t RSVD0[4100];
  248. dv_reg EWCTL;
  249. dv_reg EWINTTCNT;
  250. #endif
  251. } ewrap_regs;
  252. /* EMAC MDIO Registers Structure */
  253. typedef struct {
  254. dv_reg VERSION;
  255. dv_reg CONTROL;
  256. dv_reg ALIVE;
  257. dv_reg LINK;
  258. dv_reg LINKINTRAW;
  259. dv_reg LINKINTMASKED;
  260. u_int8_t RSVD0[8];
  261. dv_reg USERINTRAW;
  262. dv_reg USERINTMASKED;
  263. dv_reg USERINTMASKSET;
  264. dv_reg USERINTMASKCLEAR;
  265. u_int8_t RSVD1[80];
  266. dv_reg USERACCESS0;
  267. dv_reg USERPHYSEL0;
  268. dv_reg USERACCESS1;
  269. dv_reg USERPHYSEL1;
  270. } mdio_regs;
  271. int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
  272. int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
  273. typedef struct {
  274. char name[64];
  275. int (*init)(int phy_addr);
  276. int (*is_phy_connected)(int phy_addr);
  277. int (*get_link_speed)(int phy_addr);
  278. int (*auto_negotiate)(int phy_addr);
  279. } phy_t;
  280. #endif /* _DAVINCI_EMAC_H_ */