sunxi_emac.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * sunxi_emac.c -- Allwinner A10 ethernet driver
  4. *
  5. * (C) Copyright 2012, Stefan Roese <sr@denx.de>
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <dm/device_compat.h>
  12. #include <linux/delay.h>
  13. #include <linux/err.h>
  14. #include <malloc.h>
  15. #include <miiphy.h>
  16. #include <net.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/gpio.h>
  20. /* EMAC register */
  21. struct emac_regs {
  22. u32 ctl; /* 0x00 */
  23. u32 tx_mode; /* 0x04 */
  24. u32 tx_flow; /* 0x08 */
  25. u32 tx_ctl0; /* 0x0c */
  26. u32 tx_ctl1; /* 0x10 */
  27. u32 tx_ins; /* 0x14 */
  28. u32 tx_pl0; /* 0x18 */
  29. u32 tx_pl1; /* 0x1c */
  30. u32 tx_sta; /* 0x20 */
  31. u32 tx_io_data; /* 0x24 */
  32. u32 tx_io_data1;/* 0x28 */
  33. u32 tx_tsvl0; /* 0x2c */
  34. u32 tx_tsvh0; /* 0x30 */
  35. u32 tx_tsvl1; /* 0x34 */
  36. u32 tx_tsvh1; /* 0x38 */
  37. u32 rx_ctl; /* 0x3c */
  38. u32 rx_hash0; /* 0x40 */
  39. u32 rx_hash1; /* 0x44 */
  40. u32 rx_sta; /* 0x48 */
  41. u32 rx_io_data; /* 0x4c */
  42. u32 rx_fbc; /* 0x50 */
  43. u32 int_ctl; /* 0x54 */
  44. u32 int_sta; /* 0x58 */
  45. u32 mac_ctl0; /* 0x5c */
  46. u32 mac_ctl1; /* 0x60 */
  47. u32 mac_ipgt; /* 0x64 */
  48. u32 mac_ipgr; /* 0x68 */
  49. u32 mac_clrt; /* 0x6c */
  50. u32 mac_maxf; /* 0x70 */
  51. u32 mac_supp; /* 0x74 */
  52. u32 mac_test; /* 0x78 */
  53. u32 mac_mcfg; /* 0x7c */
  54. u32 mac_mcmd; /* 0x80 */
  55. u32 mac_madr; /* 0x84 */
  56. u32 mac_mwtd; /* 0x88 */
  57. u32 mac_mrdd; /* 0x8c */
  58. u32 mac_mind; /* 0x90 */
  59. u32 mac_ssrr; /* 0x94 */
  60. u32 mac_a0; /* 0x98 */
  61. u32 mac_a1; /* 0x9c */
  62. };
  63. /* SRAMC register */
  64. struct sunxi_sramc_regs {
  65. u32 ctrl0;
  66. u32 ctrl1;
  67. };
  68. /* 0: Disable 1: Aborted frame enable(default) */
  69. #define EMAC_TX_AB_M (0x1 << 0)
  70. /* 0: CPU 1: DMA(default) */
  71. #define EMAC_TX_TM (0x1 << 1)
  72. #define EMAC_TX_SETUP (0)
  73. /* 0: DRQ asserted 1: DRQ automatically(default) */
  74. #define EMAC_RX_DRQ_MODE (0x1 << 1)
  75. /* 0: CPU 1: DMA(default) */
  76. #define EMAC_RX_TM (0x1 << 2)
  77. /* 0: Normal(default) 1: Pass all Frames */
  78. #define EMAC_RX_PA (0x1 << 4)
  79. /* 0: Normal(default) 1: Pass Control Frames */
  80. #define EMAC_RX_PCF (0x1 << 5)
  81. /* 0: Normal(default) 1: Pass Frames with CRC Error */
  82. #define EMAC_RX_PCRCE (0x1 << 6)
  83. /* 0: Normal(default) 1: Pass Frames with Length Error */
  84. #define EMAC_RX_PLE (0x1 << 7)
  85. /* 0: Normal 1: Pass Frames length out of range(default) */
  86. #define EMAC_RX_POR (0x1 << 8)
  87. /* 0: Not accept 1: Accept unicast Packets(default) */
  88. #define EMAC_RX_UCAD (0x1 << 16)
  89. /* 0: Normal(default) 1: DA Filtering */
  90. #define EMAC_RX_DAF (0x1 << 17)
  91. /* 0: Not accept 1: Accept multicast Packets(default) */
  92. #define EMAC_RX_MCO (0x1 << 20)
  93. /* 0: Disable(default) 1: Enable Hash filter */
  94. #define EMAC_RX_MHF (0x1 << 21)
  95. /* 0: Not accept 1: Accept Broadcast Packets(default) */
  96. #define EMAC_RX_BCO (0x1 << 22)
  97. /* 0: Disable(default) 1: Enable SA Filtering */
  98. #define EMAC_RX_SAF (0x1 << 24)
  99. /* 0: Normal(default) 1: Inverse Filtering */
  100. #define EMAC_RX_SAIF (0x1 << 25)
  101. #define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
  102. EMAC_RX_MCO | EMAC_RX_BCO)
  103. /* 0: Disable 1: Enable Receive Flow Control(default) */
  104. #define EMAC_MAC_CTL0_RFC (0x1 << 2)
  105. /* 0: Disable 1: Enable Transmit Flow Control(default) */
  106. #define EMAC_MAC_CTL0_TFC (0x1 << 3)
  107. #define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
  108. /* 0: Disable 1: Enable MAC Frame Length Checking(default) */
  109. #define EMAC_MAC_CTL1_FLC (0x1 << 1)
  110. /* 0: Disable(default) 1: Enable Huge Frame */
  111. #define EMAC_MAC_CTL1_HF (0x1 << 2)
  112. /* 0: Disable(default) 1: Enable MAC Delayed CRC */
  113. #define EMAC_MAC_CTL1_DCRC (0x1 << 3)
  114. /* 0: Disable 1: Enable MAC CRC(default) */
  115. #define EMAC_MAC_CTL1_CRC (0x1 << 4)
  116. /* 0: Disable 1: Enable MAC PAD Short frames(default) */
  117. #define EMAC_MAC_CTL1_PC (0x1 << 5)
  118. /* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
  119. #define EMAC_MAC_CTL1_VC (0x1 << 6)
  120. /* 0: Disable(default) 1: Enable MAC auto detect Short frames */
  121. #define EMAC_MAC_CTL1_ADP (0x1 << 7)
  122. /* 0: Disable(default) 1: Enable */
  123. #define EMAC_MAC_CTL1_PRE (0x1 << 8)
  124. /* 0: Disable(default) 1: Enable */
  125. #define EMAC_MAC_CTL1_LPE (0x1 << 9)
  126. /* 0: Disable(default) 1: Enable no back off */
  127. #define EMAC_MAC_CTL1_NB (0x1 << 12)
  128. /* 0: Disable(default) 1: Enable */
  129. #define EMAC_MAC_CTL1_BNB (0x1 << 13)
  130. /* 0: Disable(default) 1: Enable */
  131. #define EMAC_MAC_CTL1_ED (0x1 << 14)
  132. #define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
  133. EMAC_MAC_CTL1_PC)
  134. #define EMAC_MAC_IPGT 0x15
  135. #define EMAC_MAC_NBTB_IPG1 0xc
  136. #define EMAC_MAC_NBTB_IPG2 0x12
  137. #define EMAC_MAC_CW 0x37
  138. #define EMAC_MAC_RM 0xf
  139. #define EMAC_MAC_MFL 0x0600
  140. /* Receive status */
  141. #define EMAC_CRCERR (0x1 << 4)
  142. #define EMAC_LENERR (0x3 << 5)
  143. #define EMAC_RX_BUFSIZE 2000
  144. struct emac_eth_dev {
  145. struct emac_regs *regs;
  146. struct clk clk;
  147. struct mii_dev *bus;
  148. struct phy_device *phydev;
  149. int link_printed;
  150. #ifdef CONFIG_DM_ETH
  151. uchar rx_buf[EMAC_RX_BUFSIZE];
  152. #endif
  153. };
  154. struct emac_rxhdr {
  155. s16 rx_len;
  156. u16 rx_status;
  157. };
  158. static void emac_inblk_32bit(void *reg, void *data, int count)
  159. {
  160. int cnt = (count + 3) >> 2;
  161. if (cnt) {
  162. u32 *buf = data;
  163. do {
  164. u32 x = readl(reg);
  165. *buf++ = x;
  166. } while (--cnt);
  167. }
  168. }
  169. static void emac_outblk_32bit(void *reg, void *data, int count)
  170. {
  171. int cnt = (count + 3) >> 2;
  172. if (cnt) {
  173. const u32 *buf = data;
  174. do {
  175. writel(*buf++, reg);
  176. } while (--cnt);
  177. }
  178. }
  179. /* Read a word from phyxcer */
  180. static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  181. {
  182. struct emac_eth_dev *priv = bus->priv;
  183. struct emac_regs *regs = priv->regs;
  184. /* issue the phy address and reg */
  185. writel(addr << 8 | reg, &regs->mac_madr);
  186. /* pull up the phy io line */
  187. writel(0x1, &regs->mac_mcmd);
  188. /* Wait read complete */
  189. mdelay(1);
  190. /* push down the phy io line */
  191. writel(0x0, &regs->mac_mcmd);
  192. /* And read data */
  193. return readl(&regs->mac_mrdd);
  194. }
  195. /* Write a word to phyxcer */
  196. static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  197. u16 value)
  198. {
  199. struct emac_eth_dev *priv = bus->priv;
  200. struct emac_regs *regs = priv->regs;
  201. /* issue the phy address and reg */
  202. writel(addr << 8 | reg, &regs->mac_madr);
  203. /* pull up the phy io line */
  204. writel(0x1, &regs->mac_mcmd);
  205. /* Wait write complete */
  206. mdelay(1);
  207. /* push down the phy io line */
  208. writel(0x0, &regs->mac_mcmd);
  209. /* and write data */
  210. writel(value, &regs->mac_mwtd);
  211. return 0;
  212. }
  213. static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
  214. {
  215. int ret, mask = 0xffffffff;
  216. #ifdef CONFIG_PHY_ADDR
  217. mask = 1 << CONFIG_PHY_ADDR;
  218. #endif
  219. priv->bus = mdio_alloc();
  220. if (!priv->bus) {
  221. printf("Failed to allocate MDIO bus\n");
  222. return -ENOMEM;
  223. }
  224. priv->bus->read = emac_mdio_read;
  225. priv->bus->write = emac_mdio_write;
  226. priv->bus->priv = priv;
  227. strcpy(priv->bus->name, "emac");
  228. ret = mdio_register(priv->bus);
  229. if (ret)
  230. return ret;
  231. priv->phydev = phy_find_by_mask(priv->bus, mask,
  232. PHY_INTERFACE_MODE_MII);
  233. if (!priv->phydev)
  234. return -ENODEV;
  235. phy_connect_dev(priv->phydev, dev);
  236. phy_config(priv->phydev);
  237. return 0;
  238. }
  239. static void emac_setup(struct emac_eth_dev *priv)
  240. {
  241. struct emac_regs *regs = priv->regs;
  242. u32 reg_val;
  243. /* Set up TX */
  244. writel(EMAC_TX_SETUP, &regs->tx_mode);
  245. /* Set up RX */
  246. writel(EMAC_RX_SETUP, &regs->rx_ctl);
  247. /* Set MAC */
  248. /* Set MAC CTL0 */
  249. writel(EMAC_MAC_CTL0_SETUP, &regs->mac_ctl0);
  250. /* Set MAC CTL1 */
  251. reg_val = 0;
  252. if (priv->phydev->duplex == DUPLEX_FULL)
  253. reg_val = (0x1 << 0);
  254. writel(EMAC_MAC_CTL1_SETUP | reg_val, &regs->mac_ctl1);
  255. /* Set up IPGT */
  256. writel(EMAC_MAC_IPGT, &regs->mac_ipgt);
  257. /* Set up IPGR */
  258. writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), &regs->mac_ipgr);
  259. /* Set up Collison window */
  260. writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), &regs->mac_clrt);
  261. /* Set up Max Frame Length */
  262. writel(EMAC_MAC_MFL, &regs->mac_maxf);
  263. }
  264. static void emac_reset(struct emac_eth_dev *priv)
  265. {
  266. struct emac_regs *regs = priv->regs;
  267. debug("resetting device\n");
  268. /* RESET device */
  269. writel(0, &regs->ctl);
  270. udelay(200);
  271. writel(1, &regs->ctl);
  272. udelay(200);
  273. }
  274. static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr)
  275. {
  276. struct emac_regs *regs = priv->regs;
  277. u32 enetaddr_lo, enetaddr_hi;
  278. enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16);
  279. enetaddr_hi = enetaddr[5] | (enetaddr[4] << 8) | (enetaddr[3] << 16);
  280. writel(enetaddr_hi, &regs->mac_a0);
  281. writel(enetaddr_lo, &regs->mac_a1);
  282. return 0;
  283. }
  284. static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
  285. {
  286. struct emac_regs *regs = priv->regs;
  287. int ret;
  288. /* Init EMAC */
  289. /* Flush RX FIFO */
  290. setbits_le32(&regs->rx_ctl, 0x8);
  291. udelay(1);
  292. /* Init MAC */
  293. /* Soft reset MAC */
  294. clrbits_le32(&regs->mac_ctl0, 0x1 << 15);
  295. /* Clear RX counter */
  296. writel(0x0, &regs->rx_fbc);
  297. udelay(1);
  298. /* Set up EMAC */
  299. emac_setup(priv);
  300. _sunxi_write_hwaddr(priv, enetaddr);
  301. mdelay(1);
  302. emac_reset(priv);
  303. /* PHY POWER UP */
  304. ret = phy_startup(priv->phydev);
  305. if (ret) {
  306. printf("Could not initialize PHY %s\n",
  307. priv->phydev->dev->name);
  308. return ret;
  309. }
  310. /* Print link status only once */
  311. if (!priv->link_printed) {
  312. printf("ENET Speed is %d Mbps - %s duplex connection\n",
  313. priv->phydev->speed,
  314. priv->phydev->duplex ? "FULL" : "HALF");
  315. priv->link_printed = 1;
  316. }
  317. /* Set EMAC SPEED depend on PHY */
  318. if (priv->phydev->speed == SPEED_100)
  319. setbits_le32(&regs->mac_supp, 1 << 8);
  320. else
  321. clrbits_le32(&regs->mac_supp, 1 << 8);
  322. /* Set duplex depend on phy */
  323. if (priv->phydev->duplex == DUPLEX_FULL)
  324. setbits_le32(&regs->mac_ctl1, 1 << 0);
  325. else
  326. clrbits_le32(&regs->mac_ctl1, 1 << 0);
  327. /* Enable RX/TX */
  328. setbits_le32(&regs->ctl, 0x7);
  329. return 0;
  330. }
  331. static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet)
  332. {
  333. struct emac_regs *regs = priv->regs;
  334. struct emac_rxhdr rxhdr;
  335. u32 rxcount;
  336. u32 reg_val;
  337. int rx_len;
  338. int rx_status;
  339. int good_packet;
  340. /* Check packet ready or not */
  341. /* Race warning: The first packet might arrive with
  342. * the interrupts disabled, but the second will fix
  343. */
  344. rxcount = readl(&regs->rx_fbc);
  345. if (!rxcount) {
  346. /* Had one stuck? */
  347. rxcount = readl(&regs->rx_fbc);
  348. if (!rxcount)
  349. return -EAGAIN;
  350. }
  351. reg_val = readl(&regs->rx_io_data);
  352. if (reg_val != 0x0143414d) {
  353. /* Disable RX */
  354. clrbits_le32(&regs->ctl, 0x1 << 2);
  355. /* Flush RX FIFO */
  356. setbits_le32(&regs->rx_ctl, 0x1 << 3);
  357. while (readl(&regs->rx_ctl) & (0x1 << 3))
  358. ;
  359. /* Enable RX */
  360. setbits_le32(&regs->ctl, 0x1 << 2);
  361. return -EAGAIN;
  362. }
  363. /* A packet ready now
  364. * Get status/length
  365. */
  366. good_packet = 1;
  367. emac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));
  368. rx_len = rxhdr.rx_len;
  369. rx_status = rxhdr.rx_status;
  370. /* Packet Status check */
  371. if (rx_len < 0x40) {
  372. good_packet = 0;
  373. debug("RX: Bad Packet (runt)\n");
  374. }
  375. /* rx_status is identical to RSR register. */
  376. if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
  377. good_packet = 0;
  378. if (rx_status & EMAC_CRCERR)
  379. printf("crc error\n");
  380. if (rx_status & EMAC_LENERR)
  381. printf("length error\n");
  382. }
  383. /* Move data from EMAC */
  384. if (good_packet) {
  385. if (rx_len > EMAC_RX_BUFSIZE) {
  386. printf("Received packet is too big (len=%d)\n", rx_len);
  387. return -EMSGSIZE;
  388. }
  389. emac_inblk_32bit((void *)&regs->rx_io_data, packet, rx_len);
  390. return rx_len;
  391. }
  392. return -EIO; /* Bad packet */
  393. }
  394. static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
  395. int len)
  396. {
  397. struct emac_regs *regs = priv->regs;
  398. /* Select channel 0 */
  399. writel(0, &regs->tx_ins);
  400. /* Write packet */
  401. emac_outblk_32bit((void *)&regs->tx_io_data, packet, len);
  402. /* Set TX len */
  403. writel(len, &regs->tx_pl0);
  404. /* Start translate from fifo to phy */
  405. setbits_le32(&regs->tx_ctl0, 1);
  406. return 0;
  407. }
  408. static int sunxi_emac_board_setup(struct udevice *dev,
  409. struct emac_eth_dev *priv)
  410. {
  411. struct sunxi_sramc_regs *sram =
  412. (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
  413. struct emac_regs *regs = priv->regs;
  414. int pin, ret;
  415. /* Map SRAM to EMAC */
  416. setbits_le32(&sram->ctrl1, 0x5 << 2);
  417. /* Configure pin mux settings for MII Ethernet */
  418. for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
  419. sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
  420. /* Set up clock gating */
  421. ret = clk_enable(&priv->clk);
  422. if (ret) {
  423. dev_err(dev, "failed to enable emac clock\n");
  424. return ret;
  425. }
  426. /* Set MII clock */
  427. clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
  428. return 0;
  429. }
  430. static int sunxi_emac_eth_start(struct udevice *dev)
  431. {
  432. struct eth_pdata *pdata = dev_get_platdata(dev);
  433. return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr);
  434. }
  435. static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length)
  436. {
  437. struct emac_eth_dev *priv = dev_get_priv(dev);
  438. return _sunxi_emac_eth_send(priv, packet, length);
  439. }
  440. static int sunxi_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  441. {
  442. struct emac_eth_dev *priv = dev_get_priv(dev);
  443. int rx_len;
  444. rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf);
  445. *packetp = priv->rx_buf;
  446. return rx_len;
  447. }
  448. static void sunxi_emac_eth_stop(struct udevice *dev)
  449. {
  450. /* Nothing to do here */
  451. }
  452. static int sunxi_emac_eth_probe(struct udevice *dev)
  453. {
  454. struct eth_pdata *pdata = dev_get_platdata(dev);
  455. struct emac_eth_dev *priv = dev_get_priv(dev);
  456. int ret;
  457. priv->regs = (struct emac_regs *)pdata->iobase;
  458. ret = clk_get_by_index(dev, 0, &priv->clk);
  459. if (ret) {
  460. dev_err(dev, "failed to get emac clock\n");
  461. return ret;
  462. }
  463. ret = sunxi_emac_board_setup(dev, priv);
  464. if (ret)
  465. return ret;
  466. return sunxi_emac_init_phy(priv, dev);
  467. }
  468. static const struct eth_ops sunxi_emac_eth_ops = {
  469. .start = sunxi_emac_eth_start,
  470. .send = sunxi_emac_eth_send,
  471. .recv = sunxi_emac_eth_recv,
  472. .stop = sunxi_emac_eth_stop,
  473. };
  474. static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev)
  475. {
  476. struct eth_pdata *pdata = dev_get_platdata(dev);
  477. pdata->iobase = dev_read_addr(dev);
  478. return 0;
  479. }
  480. static const struct udevice_id sunxi_emac_eth_ids[] = {
  481. { .compatible = "allwinner,sun4i-a10-emac" },
  482. { }
  483. };
  484. U_BOOT_DRIVER(eth_sunxi_emac) = {
  485. .name = "eth_sunxi_emac",
  486. .id = UCLASS_ETH,
  487. .of_match = sunxi_emac_eth_ids,
  488. .ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata,
  489. .probe = sunxi_emac_eth_probe,
  490. .ops = &sunxi_emac_eth_ops,
  491. .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
  492. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  493. };