sun8i_emac.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016
  4. * Author: Amit Singh Tomar, amittomer25@gmail.com
  5. *
  6. * Ethernet driver for H3/A64/A83T based SoC's
  7. *
  8. * It is derived from the work done by
  9. * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
  10. *
  11. */
  12. #include <cpu_func.h>
  13. #include <log.h>
  14. #include <asm/cache.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/gpio.h>
  18. #include <common.h>
  19. #include <clk.h>
  20. #include <dm.h>
  21. #include <fdt_support.h>
  22. #include <dm/device_compat.h>
  23. #include <linux/bitops.h>
  24. #include <linux/delay.h>
  25. #include <linux/err.h>
  26. #include <malloc.h>
  27. #include <miiphy.h>
  28. #include <net.h>
  29. #include <reset.h>
  30. #include <dt-bindings/pinctrl/sun4i-a10.h>
  31. #include <wait_bit.h>
  32. #if CONFIG_IS_ENABLED(DM_GPIO)
  33. #include <asm-generic/gpio.h>
  34. #endif
  35. #define MDIO_CMD_MII_BUSY BIT(0)
  36. #define MDIO_CMD_MII_WRITE BIT(1)
  37. #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
  38. #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
  39. #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
  40. #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
  41. #define MDIO_CMD_MII_CLK_CSR_DIV_16 0x0
  42. #define MDIO_CMD_MII_CLK_CSR_DIV_32 0x1
  43. #define MDIO_CMD_MII_CLK_CSR_DIV_64 0x2
  44. #define MDIO_CMD_MII_CLK_CSR_DIV_128 0x3
  45. #define MDIO_CMD_MII_CLK_CSR_SHIFT 20
  46. #define CONFIG_TX_DESCR_NUM 32
  47. #define CONFIG_RX_DESCR_NUM 32
  48. #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
  49. /*
  50. * The datasheet says that each descriptor can transfers up to 4096 bytes
  51. * But later, the register documentation reduces that value to 2048,
  52. * using 2048 cause strange behaviours and even BSP driver use 2047
  53. */
  54. #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
  55. #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
  56. #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
  57. #define H3_EPHY_DEFAULT_VALUE 0x58000
  58. #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
  59. #define H3_EPHY_ADDR_SHIFT 20
  60. #define REG_PHY_ADDR_MASK GENMASK(4, 0)
  61. #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
  62. #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
  63. #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
  64. #define SC_RMII_EN BIT(13)
  65. #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
  66. #define SC_ETCS_MASK GENMASK(1, 0)
  67. #define SC_ETCS_EXT_GMII 0x1
  68. #define SC_ETCS_INT_GMII 0x2
  69. #define SC_ETXDC_MASK GENMASK(12, 10)
  70. #define SC_ETXDC_OFFSET 10
  71. #define SC_ERXDC_MASK GENMASK(9, 5)
  72. #define SC_ERXDC_OFFSET 5
  73. #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
  74. #define AHB_GATE_OFFSET_EPHY 0
  75. /* IO mux settings */
  76. #define SUN8I_IOMUX_H3 2
  77. #define SUN8I_IOMUX_R40 5
  78. #define SUN8I_IOMUX 4
  79. /* H3/A64 EMAC Register's offset */
  80. #define EMAC_CTL0 0x00
  81. #define EMAC_CTL0_FULL_DUPLEX BIT(0)
  82. #define EMAC_CTL0_SPEED_MASK GENMASK(3, 2)
  83. #define EMAC_CTL0_SPEED_10 (0x2 << 2)
  84. #define EMAC_CTL0_SPEED_100 (0x3 << 2)
  85. #define EMAC_CTL0_SPEED_1000 (0x0 << 2)
  86. #define EMAC_CTL1 0x04
  87. #define EMAC_CTL1_SOFT_RST BIT(0)
  88. #define EMAC_CTL1_BURST_LEN_SHIFT 24
  89. #define EMAC_INT_STA 0x08
  90. #define EMAC_INT_EN 0x0c
  91. #define EMAC_TX_CTL0 0x10
  92. #define EMAC_TX_CTL0_TX_EN BIT(31)
  93. #define EMAC_TX_CTL1 0x14
  94. #define EMAC_TX_CTL1_TX_MD BIT(1)
  95. #define EMAC_TX_CTL1_TX_DMA_EN BIT(30)
  96. #define EMAC_TX_CTL1_TX_DMA_START BIT(31)
  97. #define EMAC_TX_FLOW_CTL 0x1c
  98. #define EMAC_TX_DMA_DESC 0x20
  99. #define EMAC_RX_CTL0 0x24
  100. #define EMAC_RX_CTL0_RX_EN BIT(31)
  101. #define EMAC_RX_CTL1 0x28
  102. #define EMAC_RX_CTL1_RX_MD BIT(1)
  103. #define EMAC_RX_CTL1_RX_RUNT_FRM BIT(2)
  104. #define EMAC_RX_CTL1_RX_ERR_FRM BIT(3)
  105. #define EMAC_RX_CTL1_RX_DMA_EN BIT(30)
  106. #define EMAC_RX_CTL1_RX_DMA_START BIT(31)
  107. #define EMAC_RX_DMA_DESC 0x34
  108. #define EMAC_MII_CMD 0x48
  109. #define EMAC_MII_DATA 0x4c
  110. #define EMAC_ADDR0_HIGH 0x50
  111. #define EMAC_ADDR0_LOW 0x54
  112. #define EMAC_TX_DMA_STA 0xb0
  113. #define EMAC_TX_CUR_DESC 0xb4
  114. #define EMAC_TX_CUR_BUF 0xb8
  115. #define EMAC_RX_DMA_STA 0xc0
  116. #define EMAC_RX_CUR_DESC 0xc4
  117. #define EMAC_DESC_OWN_DMA BIT(31)
  118. #define EMAC_DESC_LAST_DESC BIT(30)
  119. #define EMAC_DESC_FIRST_DESC BIT(29)
  120. #define EMAC_DESC_CHAIN_SECOND BIT(24)
  121. #define EMAC_DESC_RX_ERROR_MASK 0x400068db
  122. DECLARE_GLOBAL_DATA_PTR;
  123. enum emac_variant {
  124. A83T_EMAC = 1,
  125. H3_EMAC,
  126. A64_EMAC,
  127. R40_GMAC,
  128. H6_EMAC,
  129. };
  130. struct emac_dma_desc {
  131. u32 status;
  132. u32 ctl_size;
  133. u32 buf_addr;
  134. u32 next;
  135. } __aligned(ARCH_DMA_MINALIGN);
  136. struct emac_eth_dev {
  137. struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
  138. struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
  139. char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  140. char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  141. u32 interface;
  142. u32 phyaddr;
  143. u32 link;
  144. u32 speed;
  145. u32 duplex;
  146. u32 phy_configured;
  147. u32 tx_currdescnum;
  148. u32 rx_currdescnum;
  149. u32 addr;
  150. u32 tx_slot;
  151. bool use_internal_phy;
  152. enum emac_variant variant;
  153. void *mac_reg;
  154. phys_addr_t sysctl_reg;
  155. struct phy_device *phydev;
  156. struct mii_dev *bus;
  157. struct clk tx_clk;
  158. struct clk ephy_clk;
  159. struct reset_ctl tx_rst;
  160. struct reset_ctl ephy_rst;
  161. #if CONFIG_IS_ENABLED(DM_GPIO)
  162. struct gpio_desc reset_gpio;
  163. #endif
  164. };
  165. struct sun8i_eth_pdata {
  166. struct eth_pdata eth_pdata;
  167. u32 reset_delays[3];
  168. int tx_delay_ps;
  169. int rx_delay_ps;
  170. };
  171. static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  172. {
  173. struct udevice *dev = bus->priv;
  174. struct emac_eth_dev *priv = dev_get_priv(dev);
  175. u32 mii_cmd;
  176. int ret;
  177. mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
  178. MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  179. mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
  180. MDIO_CMD_MII_PHY_ADDR_MASK;
  181. /*
  182. * The EMAC clock is either 200 or 300 MHz, so we need a divider
  183. * of 128 to get the MDIO frequency below the required 2.5 MHz.
  184. */
  185. mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT;
  186. mii_cmd |= MDIO_CMD_MII_BUSY;
  187. writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
  188. ret = wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
  189. MDIO_CMD_MII_BUSY, false,
  190. CONFIG_MDIO_TIMEOUT, true);
  191. if (ret < 0)
  192. return ret;
  193. return readl(priv->mac_reg + EMAC_MII_DATA);
  194. }
  195. static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  196. u16 val)
  197. {
  198. struct udevice *dev = bus->priv;
  199. struct emac_eth_dev *priv = dev_get_priv(dev);
  200. u32 mii_cmd;
  201. mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
  202. MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  203. mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
  204. MDIO_CMD_MII_PHY_ADDR_MASK;
  205. /*
  206. * The EMAC clock is either 200 or 300 MHz, so we need a divider
  207. * of 128 to get the MDIO frequency below the required 2.5 MHz.
  208. */
  209. mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT;
  210. mii_cmd |= MDIO_CMD_MII_WRITE;
  211. mii_cmd |= MDIO_CMD_MII_BUSY;
  212. writel(val, priv->mac_reg + EMAC_MII_DATA);
  213. writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
  214. return wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
  215. MDIO_CMD_MII_BUSY, false,
  216. CONFIG_MDIO_TIMEOUT, true);
  217. }
  218. static int sun8i_eth_write_hwaddr(struct udevice *dev)
  219. {
  220. struct emac_eth_dev *priv = dev_get_priv(dev);
  221. struct eth_pdata *pdata = dev_get_platdata(dev);
  222. uchar *mac_id = pdata->enetaddr;
  223. u32 macid_lo, macid_hi;
  224. macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
  225. (mac_id[3] << 24);
  226. macid_hi = mac_id[4] + (mac_id[5] << 8);
  227. writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
  228. writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
  229. return 0;
  230. }
  231. static void sun8i_adjust_link(struct emac_eth_dev *priv,
  232. struct phy_device *phydev)
  233. {
  234. u32 v;
  235. v = readl(priv->mac_reg + EMAC_CTL0);
  236. if (phydev->duplex)
  237. v |= EMAC_CTL0_FULL_DUPLEX;
  238. else
  239. v &= ~EMAC_CTL0_FULL_DUPLEX;
  240. v &= ~EMAC_CTL0_SPEED_MASK;
  241. switch (phydev->speed) {
  242. case 1000:
  243. v |= EMAC_CTL0_SPEED_1000;
  244. break;
  245. case 100:
  246. v |= EMAC_CTL0_SPEED_100;
  247. break;
  248. case 10:
  249. v |= EMAC_CTL0_SPEED_10;
  250. break;
  251. }
  252. writel(v, priv->mac_reg + EMAC_CTL0);
  253. }
  254. static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
  255. {
  256. if (priv->use_internal_phy) {
  257. /* H3 based SoC's that has an Internal 100MBit PHY
  258. * needs to be configured and powered up before use
  259. */
  260. *reg &= ~H3_EPHY_DEFAULT_MASK;
  261. *reg |= H3_EPHY_DEFAULT_VALUE;
  262. *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
  263. *reg &= ~H3_EPHY_SHUTDOWN;
  264. *reg |= H3_EPHY_SELECT;
  265. } else
  266. /* This is to select External Gigabit PHY on
  267. * the boards with H3 SoC.
  268. */
  269. *reg &= ~H3_EPHY_SELECT;
  270. return 0;
  271. }
  272. static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
  273. struct emac_eth_dev *priv)
  274. {
  275. int ret;
  276. u32 reg;
  277. if (priv->variant == R40_GMAC) {
  278. /* Select RGMII for R40 */
  279. reg = readl(priv->sysctl_reg + 0x164);
  280. reg |= SC_ETCS_INT_GMII |
  281. SC_EPIT |
  282. (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
  283. writel(reg, priv->sysctl_reg + 0x164);
  284. return 0;
  285. }
  286. reg = readl(priv->sysctl_reg + 0x30);
  287. if (priv->variant == H3_EMAC || priv->variant == H6_EMAC) {
  288. ret = sun8i_emac_set_syscon_ephy(priv, &reg);
  289. if (ret)
  290. return ret;
  291. }
  292. reg &= ~(SC_ETCS_MASK | SC_EPIT);
  293. if (priv->variant == H3_EMAC ||
  294. priv->variant == A64_EMAC ||
  295. priv->variant == H6_EMAC)
  296. reg &= ~SC_RMII_EN;
  297. switch (priv->interface) {
  298. case PHY_INTERFACE_MODE_MII:
  299. /* default */
  300. break;
  301. case PHY_INTERFACE_MODE_RGMII:
  302. reg |= SC_EPIT | SC_ETCS_INT_GMII;
  303. break;
  304. case PHY_INTERFACE_MODE_RMII:
  305. if (priv->variant == H3_EMAC ||
  306. priv->variant == A64_EMAC ||
  307. priv->variant == H6_EMAC) {
  308. reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
  309. break;
  310. }
  311. /* RMII not supported on A83T */
  312. default:
  313. debug("%s: Invalid PHY interface\n", __func__);
  314. return -EINVAL;
  315. }
  316. if (pdata->tx_delay_ps)
  317. reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
  318. & SC_ETXDC_MASK;
  319. if (pdata->rx_delay_ps)
  320. reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
  321. & SC_ERXDC_MASK;
  322. writel(reg, priv->sysctl_reg + 0x30);
  323. return 0;
  324. }
  325. static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
  326. {
  327. struct phy_device *phydev;
  328. phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
  329. if (!phydev)
  330. return -ENODEV;
  331. phy_connect_dev(phydev, dev);
  332. priv->phydev = phydev;
  333. phy_config(priv->phydev);
  334. return 0;
  335. }
  336. #define cache_clean_descriptor(desc) \
  337. flush_dcache_range((uintptr_t)(desc), \
  338. (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
  339. #define cache_inv_descriptor(desc) \
  340. invalidate_dcache_range((uintptr_t)(desc), \
  341. (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
  342. static void rx_descs_init(struct emac_eth_dev *priv)
  343. {
  344. struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
  345. char *rxbuffs = &priv->rxbuffer[0];
  346. struct emac_dma_desc *desc_p;
  347. int i;
  348. /*
  349. * Make sure we don't have dirty cache lines around, which could
  350. * be cleaned to DRAM *after* the MAC has already written data to it.
  351. */
  352. invalidate_dcache_range((uintptr_t)desc_table_p,
  353. (uintptr_t)desc_table_p + sizeof(priv->rx_chain));
  354. invalidate_dcache_range((uintptr_t)rxbuffs,
  355. (uintptr_t)rxbuffs + sizeof(priv->rxbuffer));
  356. for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
  357. desc_p = &desc_table_p[i];
  358. desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CONFIG_ETH_BUFSIZE];
  359. desc_p->next = (uintptr_t)&desc_table_p[i + 1];
  360. desc_p->ctl_size = CONFIG_ETH_RXSIZE;
  361. desc_p->status = EMAC_DESC_OWN_DMA;
  362. }
  363. /* Correcting the last pointer of the chain */
  364. desc_p->next = (uintptr_t)&desc_table_p[0];
  365. flush_dcache_range((uintptr_t)priv->rx_chain,
  366. (uintptr_t)priv->rx_chain +
  367. sizeof(priv->rx_chain));
  368. writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
  369. priv->rx_currdescnum = 0;
  370. }
  371. static void tx_descs_init(struct emac_eth_dev *priv)
  372. {
  373. struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
  374. char *txbuffs = &priv->txbuffer[0];
  375. struct emac_dma_desc *desc_p;
  376. int i;
  377. for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
  378. desc_p = &desc_table_p[i];
  379. desc_p->buf_addr = (uintptr_t)&txbuffs[i * CONFIG_ETH_BUFSIZE];
  380. desc_p->next = (uintptr_t)&desc_table_p[i + 1];
  381. desc_p->ctl_size = 0;
  382. desc_p->status = 0;
  383. }
  384. /* Correcting the last pointer of the chain */
  385. desc_p->next = (uintptr_t)&desc_table_p[0];
  386. /* Flush the first TX buffer descriptor we will tell the MAC about. */
  387. cache_clean_descriptor(desc_table_p);
  388. writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
  389. priv->tx_currdescnum = 0;
  390. }
  391. static int sun8i_emac_eth_start(struct udevice *dev)
  392. {
  393. struct emac_eth_dev *priv = dev_get_priv(dev);
  394. int ret;
  395. /* Soft reset MAC */
  396. writel(EMAC_CTL1_SOFT_RST, priv->mac_reg + EMAC_CTL1);
  397. ret = wait_for_bit_le32(priv->mac_reg + EMAC_CTL1,
  398. EMAC_CTL1_SOFT_RST, false, 10, true);
  399. if (ret) {
  400. printf("%s: Timeout\n", __func__);
  401. return ret;
  402. }
  403. /* Rewrite mac address after reset */
  404. sun8i_eth_write_hwaddr(dev);
  405. /* transmission starts after the full frame arrived in TX DMA FIFO */
  406. setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_MD);
  407. /*
  408. * RX DMA reads data from RX DMA FIFO to host memory after a
  409. * complete frame has been written to RX DMA FIFO
  410. */
  411. setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_MD);
  412. /* DMA burst length */
  413. writel(8 << EMAC_CTL1_BURST_LEN_SHIFT, priv->mac_reg + EMAC_CTL1);
  414. /* Initialize rx/tx descriptors */
  415. rx_descs_init(priv);
  416. tx_descs_init(priv);
  417. /* PHY Start Up */
  418. ret = phy_startup(priv->phydev);
  419. if (ret)
  420. return ret;
  421. sun8i_adjust_link(priv, priv->phydev);
  422. /* Start RX/TX DMA */
  423. setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN |
  424. EMAC_RX_CTL1_RX_ERR_FRM | EMAC_RX_CTL1_RX_RUNT_FRM);
  425. setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
  426. /* Enable RX/TX */
  427. setbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
  428. setbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
  429. return 0;
  430. }
  431. static int parse_phy_pins(struct udevice *dev)
  432. {
  433. struct emac_eth_dev *priv = dev_get_priv(dev);
  434. int offset;
  435. const char *pin_name;
  436. int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
  437. offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
  438. "pinctrl-0");
  439. if (offset < 0) {
  440. printf("WARNING: emac: cannot find pinctrl-0 node\n");
  441. return offset;
  442. }
  443. drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
  444. "drive-strength", ~0);
  445. if (drive != ~0) {
  446. if (drive <= 10)
  447. drive = SUN4I_PINCTRL_10_MA;
  448. else if (drive <= 20)
  449. drive = SUN4I_PINCTRL_20_MA;
  450. else if (drive <= 30)
  451. drive = SUN4I_PINCTRL_30_MA;
  452. else
  453. drive = SUN4I_PINCTRL_40_MA;
  454. }
  455. if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
  456. pull = SUN4I_PINCTRL_PULL_UP;
  457. else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
  458. pull = SUN4I_PINCTRL_PULL_DOWN;
  459. for (i = 0; ; i++) {
  460. int pin;
  461. pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
  462. "pins", i, NULL);
  463. if (!pin_name)
  464. break;
  465. pin = sunxi_name_to_gpio(pin_name);
  466. if (pin < 0)
  467. continue;
  468. if (priv->variant == H3_EMAC)
  469. sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
  470. else if (priv->variant == R40_GMAC || priv->variant == H6_EMAC)
  471. sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40);
  472. else
  473. sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
  474. if (drive != ~0)
  475. sunxi_gpio_set_drv(pin, drive);
  476. if (pull != ~0)
  477. sunxi_gpio_set_pull(pin, pull);
  478. }
  479. if (!i) {
  480. printf("WARNING: emac: cannot find pins property\n");
  481. return -2;
  482. }
  483. return 0;
  484. }
  485. static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  486. {
  487. struct emac_eth_dev *priv = dev_get_priv(dev);
  488. u32 status, desc_num = priv->rx_currdescnum;
  489. struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
  490. uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
  491. int length;
  492. /* Invalidate entire buffer descriptor */
  493. cache_inv_descriptor(desc_p);
  494. status = desc_p->status;
  495. /* Check for DMA own bit */
  496. if (status & EMAC_DESC_OWN_DMA)
  497. return -EAGAIN;
  498. length = (status >> 16) & 0x3fff;
  499. /* make sure we read from DRAM, not our cache */
  500. invalidate_dcache_range(data_start,
  501. data_start + roundup(length, ARCH_DMA_MINALIGN));
  502. if (status & EMAC_DESC_RX_ERROR_MASK) {
  503. debug("RX: packet error: 0x%x\n",
  504. status & EMAC_DESC_RX_ERROR_MASK);
  505. return 0;
  506. }
  507. if (length < 0x40) {
  508. debug("RX: Bad Packet (runt)\n");
  509. return 0;
  510. }
  511. if (length > CONFIG_ETH_RXSIZE) {
  512. debug("RX: Too large packet (%d bytes)\n", length);
  513. return 0;
  514. }
  515. *packetp = (uchar *)(ulong)desc_p->buf_addr;
  516. return length;
  517. }
  518. static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
  519. {
  520. struct emac_eth_dev *priv = dev_get_priv(dev);
  521. u32 desc_num = priv->tx_currdescnum;
  522. struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
  523. uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
  524. uintptr_t data_end = data_start +
  525. roundup(length, ARCH_DMA_MINALIGN);
  526. desc_p->ctl_size = length | EMAC_DESC_CHAIN_SECOND;
  527. memcpy((void *)data_start, packet, length);
  528. /* Flush data to be sent */
  529. flush_dcache_range(data_start, data_end);
  530. /* frame begin and end */
  531. desc_p->ctl_size |= EMAC_DESC_LAST_DESC | EMAC_DESC_FIRST_DESC;
  532. desc_p->status = EMAC_DESC_OWN_DMA;
  533. /* make sure the MAC reads the actual data from DRAM */
  534. cache_clean_descriptor(desc_p);
  535. /* Move to next Descriptor and wrap around */
  536. if (++desc_num >= CONFIG_TX_DESCR_NUM)
  537. desc_num = 0;
  538. priv->tx_currdescnum = desc_num;
  539. /* Start the DMA */
  540. setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_START);
  541. /*
  542. * Since we copied the data above, we return here without waiting
  543. * for the packet to be actually send out.
  544. */
  545. return 0;
  546. }
  547. static int sun8i_emac_board_setup(struct udevice *dev,
  548. struct emac_eth_dev *priv)
  549. {
  550. int ret;
  551. ret = clk_enable(&priv->tx_clk);
  552. if (ret) {
  553. dev_err(dev, "failed to enable TX clock\n");
  554. return ret;
  555. }
  556. if (reset_valid(&priv->tx_rst)) {
  557. ret = reset_deassert(&priv->tx_rst);
  558. if (ret) {
  559. dev_err(dev, "failed to deassert TX reset\n");
  560. goto err_tx_clk;
  561. }
  562. }
  563. /* Only H3/H5 have clock controls for internal EPHY */
  564. if (clk_valid(&priv->ephy_clk)) {
  565. ret = clk_enable(&priv->ephy_clk);
  566. if (ret) {
  567. dev_err(dev, "failed to enable EPHY TX clock\n");
  568. return ret;
  569. }
  570. }
  571. if (reset_valid(&priv->ephy_rst)) {
  572. ret = reset_deassert(&priv->ephy_rst);
  573. if (ret) {
  574. dev_err(dev, "failed to deassert EPHY TX clock\n");
  575. return ret;
  576. }
  577. }
  578. return 0;
  579. err_tx_clk:
  580. clk_disable(&priv->tx_clk);
  581. return ret;
  582. }
  583. #if CONFIG_IS_ENABLED(DM_GPIO)
  584. static int sun8i_mdio_reset(struct mii_dev *bus)
  585. {
  586. struct udevice *dev = bus->priv;
  587. struct emac_eth_dev *priv = dev_get_priv(dev);
  588. struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
  589. int ret;
  590. if (!dm_gpio_is_valid(&priv->reset_gpio))
  591. return 0;
  592. /* reset the phy */
  593. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  594. if (ret)
  595. return ret;
  596. udelay(pdata->reset_delays[0]);
  597. ret = dm_gpio_set_value(&priv->reset_gpio, 1);
  598. if (ret)
  599. return ret;
  600. udelay(pdata->reset_delays[1]);
  601. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  602. if (ret)
  603. return ret;
  604. udelay(pdata->reset_delays[2]);
  605. return 0;
  606. }
  607. #endif
  608. static int sun8i_mdio_init(const char *name, struct udevice *priv)
  609. {
  610. struct mii_dev *bus = mdio_alloc();
  611. if (!bus) {
  612. debug("Failed to allocate MDIO bus\n");
  613. return -ENOMEM;
  614. }
  615. bus->read = sun8i_mdio_read;
  616. bus->write = sun8i_mdio_write;
  617. snprintf(bus->name, sizeof(bus->name), name);
  618. bus->priv = (void *)priv;
  619. #if CONFIG_IS_ENABLED(DM_GPIO)
  620. bus->reset = sun8i_mdio_reset;
  621. #endif
  622. return mdio_register(bus);
  623. }
  624. static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
  625. int length)
  626. {
  627. struct emac_eth_dev *priv = dev_get_priv(dev);
  628. u32 desc_num = priv->rx_currdescnum;
  629. struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
  630. /* give the current descriptor back to the MAC */
  631. desc_p->status |= EMAC_DESC_OWN_DMA;
  632. /* Flush Status field of descriptor */
  633. cache_clean_descriptor(desc_p);
  634. /* Move to next desc and wrap-around condition. */
  635. if (++desc_num >= CONFIG_RX_DESCR_NUM)
  636. desc_num = 0;
  637. priv->rx_currdescnum = desc_num;
  638. return 0;
  639. }
  640. static void sun8i_emac_eth_stop(struct udevice *dev)
  641. {
  642. struct emac_eth_dev *priv = dev_get_priv(dev);
  643. /* Stop Rx/Tx transmitter */
  644. clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
  645. clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
  646. /* Stop RX/TX DMA */
  647. clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
  648. clrbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN);
  649. phy_shutdown(priv->phydev);
  650. }
  651. static int sun8i_emac_eth_probe(struct udevice *dev)
  652. {
  653. struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
  654. struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
  655. struct emac_eth_dev *priv = dev_get_priv(dev);
  656. int ret;
  657. priv->mac_reg = (void *)pdata->iobase;
  658. ret = sun8i_emac_board_setup(dev, priv);
  659. if (ret)
  660. return ret;
  661. sun8i_emac_set_syscon(sun8i_pdata, priv);
  662. sun8i_mdio_init(dev->name, dev);
  663. priv->bus = miiphy_get_dev_by_name(dev->name);
  664. return sun8i_phy_init(priv, dev);
  665. }
  666. static const struct eth_ops sun8i_emac_eth_ops = {
  667. .start = sun8i_emac_eth_start,
  668. .write_hwaddr = sun8i_eth_write_hwaddr,
  669. .send = sun8i_emac_eth_send,
  670. .recv = sun8i_emac_eth_recv,
  671. .free_pkt = sun8i_eth_free_pkt,
  672. .stop = sun8i_emac_eth_stop,
  673. };
  674. static int sun8i_handle_internal_phy(struct udevice *dev, struct emac_eth_dev *priv)
  675. {
  676. struct ofnode_phandle_args phandle;
  677. int ret;
  678. ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle",
  679. NULL, 0, 0, &phandle);
  680. if (ret)
  681. return ret;
  682. /* If the PHY node is not a child of the internal MDIO bus, we are
  683. * using some external PHY.
  684. */
  685. if (!ofnode_device_is_compatible(ofnode_get_parent(phandle.node),
  686. "allwinner,sun8i-h3-mdio-internal"))
  687. return 0;
  688. ret = clk_get_by_index_nodev(phandle.node, 0, &priv->ephy_clk);
  689. if (ret) {
  690. dev_err(dev, "failed to get EPHY TX clock\n");
  691. return ret;
  692. }
  693. ret = reset_get_by_index_nodev(phandle.node, 0, &priv->ephy_rst);
  694. if (ret) {
  695. dev_err(dev, "failed to get EPHY TX reset\n");
  696. return ret;
  697. }
  698. priv->use_internal_phy = true;
  699. return 0;
  700. }
  701. static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
  702. {
  703. struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
  704. struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
  705. struct emac_eth_dev *priv = dev_get_priv(dev);
  706. const char *phy_mode;
  707. const fdt32_t *reg;
  708. int node = dev_of_offset(dev);
  709. int offset = 0;
  710. #if CONFIG_IS_ENABLED(DM_GPIO)
  711. int reset_flags = GPIOD_IS_OUT;
  712. #endif
  713. int ret;
  714. pdata->iobase = dev_read_addr(dev);
  715. if (pdata->iobase == FDT_ADDR_T_NONE) {
  716. debug("%s: Cannot find MAC base address\n", __func__);
  717. return -EINVAL;
  718. }
  719. priv->variant = dev_get_driver_data(dev);
  720. if (!priv->variant) {
  721. printf("%s: Missing variant\n", __func__);
  722. return -EINVAL;
  723. }
  724. ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
  725. if (ret) {
  726. dev_err(dev, "failed to get TX clock\n");
  727. return ret;
  728. }
  729. ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
  730. if (ret && ret != -ENOENT) {
  731. dev_err(dev, "failed to get TX reset\n");
  732. return ret;
  733. }
  734. offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
  735. if (offset < 0) {
  736. debug("%s: cannot find syscon node\n", __func__);
  737. return -EINVAL;
  738. }
  739. reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
  740. if (!reg) {
  741. debug("%s: cannot find reg property in syscon node\n",
  742. __func__);
  743. return -EINVAL;
  744. }
  745. priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
  746. offset, reg);
  747. if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
  748. debug("%s: Cannot find syscon base address\n", __func__);
  749. return -EINVAL;
  750. }
  751. pdata->phy_interface = -1;
  752. priv->phyaddr = -1;
  753. priv->use_internal_phy = false;
  754. offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
  755. if (offset < 0) {
  756. debug("%s: Cannot find PHY address\n", __func__);
  757. return -EINVAL;
  758. }
  759. priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
  760. phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
  761. if (phy_mode)
  762. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  763. printf("phy interface%d\n", pdata->phy_interface);
  764. if (pdata->phy_interface == -1) {
  765. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  766. return -EINVAL;
  767. }
  768. if (priv->variant == H3_EMAC) {
  769. ret = sun8i_handle_internal_phy(dev, priv);
  770. if (ret)
  771. return ret;
  772. }
  773. priv->interface = pdata->phy_interface;
  774. if (!priv->use_internal_phy)
  775. parse_phy_pins(dev);
  776. sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
  777. "allwinner,tx-delay-ps", 0);
  778. if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
  779. printf("%s: Invalid TX delay value %d\n", __func__,
  780. sun8i_pdata->tx_delay_ps);
  781. sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
  782. "allwinner,rx-delay-ps", 0);
  783. if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
  784. printf("%s: Invalid RX delay value %d\n", __func__,
  785. sun8i_pdata->rx_delay_ps);
  786. #if CONFIG_IS_ENABLED(DM_GPIO)
  787. if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
  788. "snps,reset-active-low"))
  789. reset_flags |= GPIOD_ACTIVE_LOW;
  790. ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
  791. &priv->reset_gpio, reset_flags);
  792. if (ret == 0) {
  793. ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
  794. "snps,reset-delays-us",
  795. sun8i_pdata->reset_delays, 3);
  796. } else if (ret == -ENOENT) {
  797. ret = 0;
  798. }
  799. #endif
  800. return 0;
  801. }
  802. static const struct udevice_id sun8i_emac_eth_ids[] = {
  803. {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
  804. {.compatible = "allwinner,sun50i-a64-emac",
  805. .data = (uintptr_t)A64_EMAC },
  806. {.compatible = "allwinner,sun8i-a83t-emac",
  807. .data = (uintptr_t)A83T_EMAC },
  808. {.compatible = "allwinner,sun8i-r40-gmac",
  809. .data = (uintptr_t)R40_GMAC },
  810. {.compatible = "allwinner,sun50i-h6-emac",
  811. .data = (uintptr_t)H6_EMAC },
  812. { }
  813. };
  814. U_BOOT_DRIVER(eth_sun8i_emac) = {
  815. .name = "eth_sun8i_emac",
  816. .id = UCLASS_ETH,
  817. .of_match = sun8i_emac_eth_ids,
  818. .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
  819. .probe = sun8i_emac_eth_probe,
  820. .ops = &sun8i_emac_eth_ops,
  821. .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
  822. .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
  823. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  824. };