sni_ave.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**
  3. * sni_ave.c - Socionext UniPhier AVE ethernet driver
  4. * Copyright 2016-2018 Socionext inc.
  5. */
  6. #include <clk.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <fdt_support.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <miiphy.h>
  13. #include <net.h>
  14. #include <regmap.h>
  15. #include <reset.h>
  16. #include <syscon.h>
  17. #include <asm/cache.h>
  18. #include <dm/device_compat.h>
  19. #include <linux/bitops.h>
  20. #include <linux/delay.h>
  21. #include <linux/err.h>
  22. #include <linux/io.h>
  23. #include <linux/iopoll.h>
  24. #define AVE_GRST_DELAY_MSEC 40
  25. #define AVE_MIN_XMITSIZE 60
  26. #define AVE_SEND_TIMEOUT_COUNT 1000
  27. #define AVE_MDIO_TIMEOUT_USEC 10000
  28. #define AVE_HALT_TIMEOUT_USEC 10000
  29. /* General Register Group */
  30. #define AVE_IDR 0x000 /* ID */
  31. #define AVE_VR 0x004 /* Version */
  32. #define AVE_GRR 0x008 /* Global Reset */
  33. #define AVE_CFGR 0x00c /* Configuration */
  34. /* Interrupt Register Group */
  35. #define AVE_GIMR 0x100 /* Global Interrupt Mask */
  36. #define AVE_GISR 0x104 /* Global Interrupt Status */
  37. /* MAC Register Group */
  38. #define AVE_TXCR 0x200 /* TX Setup */
  39. #define AVE_RXCR 0x204 /* RX Setup */
  40. #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
  41. #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
  42. #define AVE_MDIOCTR 0x214 /* MDIO Control */
  43. #define AVE_MDIOAR 0x218 /* MDIO Address */
  44. #define AVE_MDIOWDR 0x21c /* MDIO Data */
  45. #define AVE_MDIOSR 0x220 /* MDIO Status */
  46. #define AVE_MDIORDR 0x224 /* MDIO Rd Data */
  47. /* Descriptor Control Register Group */
  48. #define AVE_DESCC 0x300 /* Descriptor Control */
  49. #define AVE_TXDC 0x304 /* TX Descriptor Configuration */
  50. #define AVE_RXDC 0x308 /* RX Descriptor Ring0 Configuration */
  51. #define AVE_IIRQC 0x34c /* Interval IRQ Control */
  52. /* 64bit descriptor memory */
  53. #define AVE_DESC_SIZE_64 12 /* Descriptor Size */
  54. #define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */
  55. #define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */
  56. /* 32bit descriptor memory */
  57. #define AVE_DESC_SIZE_32 8 /* Descriptor Size */
  58. #define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */
  59. #define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */
  60. /* RMII Bridge Register Group */
  61. #define AVE_RSTCTRL 0x8028 /* Reset control */
  62. #define AVE_RSTCTRL_RMIIRST BIT(16)
  63. #define AVE_LINKSEL 0x8034 /* Link speed setting */
  64. #define AVE_LINKSEL_100M BIT(0)
  65. /* AVE_GRR */
  66. #define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */
  67. #define AVE_GRR_GRST BIT(0) /* Reset all MAC */
  68. /* AVE_CFGR */
  69. #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */
  70. /* AVE_GISR (common with GIMR) */
  71. #define AVE_GIMR_CLR 0
  72. #define AVE_GISR_CLR GENMASK(31, 0)
  73. /* AVE_TXCR */
  74. #define AVE_TXCR_FLOCTR BIT(18) /* Flow control */
  75. #define AVE_TXCR_TXSPD_1G BIT(17)
  76. #define AVE_TXCR_TXSPD_100 BIT(16)
  77. /* AVE_RXCR */
  78. #define AVE_RXCR_RXEN BIT(30) /* Rx enable */
  79. #define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */
  80. #define AVE_RXCR_FLOCTR BIT(21) /* Flow control */
  81. /* AVE_MDIOCTR */
  82. #define AVE_MDIOCTR_RREQ BIT(3) /* Read request */
  83. #define AVE_MDIOCTR_WREQ BIT(2) /* Write request */
  84. /* AVE_MDIOSR */
  85. #define AVE_MDIOSR_STS BIT(0) /* access status */
  86. /* AVE_DESCC */
  87. #define AVE_DESCC_RXDSTPSTS BIT(20)
  88. #define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */
  89. #define AVE_DESCC_RXDSTP BIT(4) /* Pause Rx descriptor */
  90. #define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */
  91. /* AVE_TXDC/RXDC */
  92. #define AVE_DESC_SIZE(priv, num) \
  93. ((num) * ((priv)->data->is_desc_64bit ? AVE_DESC_SIZE_64 : \
  94. AVE_DESC_SIZE_32))
  95. /* Command status for descriptor */
  96. #define AVE_STS_OWN BIT(31) /* Descriptor ownership */
  97. #define AVE_STS_OK BIT(27) /* Normal transmit */
  98. #define AVE_STS_1ST BIT(26) /* Head of buffer chain */
  99. #define AVE_STS_LAST BIT(25) /* Tail of buffer chain */
  100. #define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0)
  101. #define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0)
  102. #define AVE_DESC_OFS_CMDSTS 0
  103. #define AVE_DESC_OFS_ADDRL 4
  104. #define AVE_DESC_OFS_ADDRU 8
  105. /* Parameter for ethernet frame */
  106. #define AVE_RXCR_MTU 1518
  107. /* SG */
  108. #define SG_ETPINMODE 0x540
  109. #define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */
  110. #define SG_ETPINMODE_RMII(ins) BIT(ins)
  111. #define AVE_MAX_CLKS 4
  112. #define AVE_MAX_RSTS 2
  113. enum desc_id {
  114. AVE_DESCID_TX,
  115. AVE_DESCID_RX,
  116. };
  117. struct ave_private {
  118. phys_addr_t iobase;
  119. unsigned int nclks;
  120. struct clk clk[AVE_MAX_CLKS];
  121. unsigned int nrsts;
  122. struct reset_ctl rst[AVE_MAX_RSTS];
  123. struct regmap *regmap;
  124. unsigned int regmap_arg;
  125. struct mii_dev *bus;
  126. struct phy_device *phydev;
  127. int phy_mode;
  128. int max_speed;
  129. int rx_pos;
  130. int rx_siz;
  131. int rx_off;
  132. int tx_num;
  133. u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN];
  134. void *tx_adj_buf;
  135. const struct ave_soc_data *data;
  136. };
  137. struct ave_soc_data {
  138. bool is_desc_64bit;
  139. const char *clock_names[AVE_MAX_CLKS];
  140. const char *reset_names[AVE_MAX_RSTS];
  141. int (*get_pinmode)(struct ave_private *priv);
  142. };
  143. static u32 ave_desc_read(struct ave_private *priv, enum desc_id id, int entry,
  144. int offset)
  145. {
  146. int desc_size;
  147. u32 addr;
  148. if (priv->data->is_desc_64bit) {
  149. desc_size = AVE_DESC_SIZE_64;
  150. addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64;
  151. } else {
  152. desc_size = AVE_DESC_SIZE_32;
  153. addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32;
  154. }
  155. addr += entry * desc_size + offset;
  156. return readl(priv->iobase + addr);
  157. }
  158. static u32 ave_desc_read_cmdsts(struct ave_private *priv, enum desc_id id,
  159. int entry)
  160. {
  161. return ave_desc_read(priv, id, entry, AVE_DESC_OFS_CMDSTS);
  162. }
  163. static void ave_desc_write(struct ave_private *priv, enum desc_id id,
  164. int entry, int offset, u32 val)
  165. {
  166. int desc_size;
  167. u32 addr;
  168. if (priv->data->is_desc_64bit) {
  169. desc_size = AVE_DESC_SIZE_64;
  170. addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64;
  171. } else {
  172. desc_size = AVE_DESC_SIZE_32;
  173. addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32;
  174. }
  175. addr += entry * desc_size + offset;
  176. writel(val, priv->iobase + addr);
  177. }
  178. static void ave_desc_write_cmdsts(struct ave_private *priv, enum desc_id id,
  179. int entry, u32 val)
  180. {
  181. ave_desc_write(priv, id, entry, AVE_DESC_OFS_CMDSTS, val);
  182. }
  183. static void ave_desc_write_addr(struct ave_private *priv, enum desc_id id,
  184. int entry, uintptr_t paddr)
  185. {
  186. ave_desc_write(priv, id, entry,
  187. AVE_DESC_OFS_ADDRL, lower_32_bits(paddr));
  188. if (priv->data->is_desc_64bit)
  189. ave_desc_write(priv, id, entry,
  190. AVE_DESC_OFS_ADDRU, upper_32_bits(paddr));
  191. }
  192. static void ave_cache_invalidate(uintptr_t vaddr, int len)
  193. {
  194. invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
  195. roundup(vaddr + len, ARCH_DMA_MINALIGN));
  196. }
  197. static void ave_cache_flush(uintptr_t vaddr, int len)
  198. {
  199. flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
  200. roundup(vaddr + len, ARCH_DMA_MINALIGN));
  201. }
  202. static int ave_mdiobus_read(struct mii_dev *bus,
  203. int phyid, int devad, int regnum)
  204. {
  205. struct ave_private *priv = bus->priv;
  206. u32 mdioctl, mdiosr;
  207. int ret;
  208. /* write address */
  209. writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
  210. /* read request */
  211. mdioctl = readl(priv->iobase + AVE_MDIOCTR);
  212. writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR);
  213. ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
  214. !(mdiosr & AVE_MDIOSR_STS),
  215. AVE_MDIO_TIMEOUT_USEC);
  216. if (ret) {
  217. pr_err("%s: failed to read from mdio (phy:%d reg:%x)\n",
  218. priv->phydev->dev->name, phyid, regnum);
  219. return ret;
  220. }
  221. return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0);
  222. }
  223. static int ave_mdiobus_write(struct mii_dev *bus,
  224. int phyid, int devad, int regnum, u16 val)
  225. {
  226. struct ave_private *priv = bus->priv;
  227. u32 mdioctl, mdiosr;
  228. int ret;
  229. /* write address */
  230. writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
  231. /* write data */
  232. writel(val, priv->iobase + AVE_MDIOWDR);
  233. /* write request */
  234. mdioctl = readl(priv->iobase + AVE_MDIOCTR);
  235. writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ,
  236. priv->iobase + AVE_MDIOCTR);
  237. ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
  238. !(mdiosr & AVE_MDIOSR_STS),
  239. AVE_MDIO_TIMEOUT_USEC);
  240. if (ret)
  241. pr_err("%s: failed to write to mdio (phy:%d reg:%x)\n",
  242. priv->phydev->dev->name, phyid, regnum);
  243. return ret;
  244. }
  245. static int ave_adjust_link(struct ave_private *priv)
  246. {
  247. struct phy_device *phydev = priv->phydev;
  248. struct eth_pdata *pdata = dev_get_platdata(phydev->dev);
  249. u32 val, txcr, rxcr, rxcr_org;
  250. u16 rmt_adv = 0, lcl_adv = 0;
  251. u8 cap;
  252. /* set RGMII speed */
  253. val = readl(priv->iobase + AVE_TXCR);
  254. val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G);
  255. if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000)
  256. val |= AVE_TXCR_TXSPD_1G;
  257. else if (phydev->speed == SPEED_100)
  258. val |= AVE_TXCR_TXSPD_100;
  259. writel(val, priv->iobase + AVE_TXCR);
  260. /* set RMII speed (100M/10M only) */
  261. if (!phy_interface_is_rgmii(phydev)) {
  262. val = readl(priv->iobase + AVE_LINKSEL);
  263. if (phydev->speed == SPEED_10)
  264. val &= ~AVE_LINKSEL_100M;
  265. else
  266. val |= AVE_LINKSEL_100M;
  267. writel(val, priv->iobase + AVE_LINKSEL);
  268. }
  269. /* check current RXCR/TXCR */
  270. rxcr = readl(priv->iobase + AVE_RXCR);
  271. txcr = readl(priv->iobase + AVE_TXCR);
  272. rxcr_org = rxcr;
  273. if (phydev->duplex) {
  274. rxcr |= AVE_RXCR_FDUPEN;
  275. if (phydev->pause)
  276. rmt_adv |= LPA_PAUSE_CAP;
  277. if (phydev->asym_pause)
  278. rmt_adv |= LPA_PAUSE_ASYM;
  279. if (phydev->advertising & ADVERTISED_Pause)
  280. lcl_adv |= ADVERTISE_PAUSE_CAP;
  281. if (phydev->advertising & ADVERTISED_Asym_Pause)
  282. lcl_adv |= ADVERTISE_PAUSE_ASYM;
  283. cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
  284. if (cap & FLOW_CTRL_TX)
  285. txcr |= AVE_TXCR_FLOCTR;
  286. else
  287. txcr &= ~AVE_TXCR_FLOCTR;
  288. if (cap & FLOW_CTRL_RX)
  289. rxcr |= AVE_RXCR_FLOCTR;
  290. else
  291. rxcr &= ~AVE_RXCR_FLOCTR;
  292. } else {
  293. rxcr &= ~AVE_RXCR_FDUPEN;
  294. rxcr &= ~AVE_RXCR_FLOCTR;
  295. txcr &= ~AVE_TXCR_FLOCTR;
  296. }
  297. if (rxcr_org != rxcr) {
  298. /* disable Rx mac */
  299. writel(rxcr & ~AVE_RXCR_RXEN, priv->iobase + AVE_RXCR);
  300. /* change and enable TX/Rx mac */
  301. writel(txcr, priv->iobase + AVE_TXCR);
  302. writel(rxcr, priv->iobase + AVE_RXCR);
  303. }
  304. pr_notice("%s: phy:%s speed:%d mac:%pM\n",
  305. phydev->dev->name, phydev->drv->name, phydev->speed,
  306. pdata->enetaddr);
  307. return phydev->link;
  308. }
  309. static int ave_mdiobus_init(struct ave_private *priv, const char *name)
  310. {
  311. struct mii_dev *bus = mdio_alloc();
  312. if (!bus)
  313. return -ENOMEM;
  314. bus->read = ave_mdiobus_read;
  315. bus->write = ave_mdiobus_write;
  316. snprintf(bus->name, sizeof(bus->name), "%s", name);
  317. bus->priv = priv;
  318. return mdio_register(bus);
  319. }
  320. static int ave_phy_init(struct ave_private *priv, void *dev)
  321. {
  322. struct phy_device *phydev;
  323. int mask = GENMASK(31, 0), ret;
  324. phydev = phy_find_by_mask(priv->bus, mask, priv->phy_mode);
  325. if (!phydev)
  326. return -ENODEV;
  327. phy_connect_dev(phydev, dev);
  328. phydev->supported &= PHY_GBIT_FEATURES;
  329. if (priv->max_speed) {
  330. ret = phy_set_supported(phydev, priv->max_speed);
  331. if (ret)
  332. return ret;
  333. }
  334. phydev->advertising = phydev->supported;
  335. priv->phydev = phydev;
  336. phy_config(phydev);
  337. return 0;
  338. }
  339. static void ave_stop(struct udevice *dev)
  340. {
  341. struct ave_private *priv = dev_get_priv(dev);
  342. u32 val;
  343. int ret;
  344. val = readl(priv->iobase + AVE_GRR);
  345. if (val)
  346. return;
  347. val = readl(priv->iobase + AVE_RXCR);
  348. val &= ~AVE_RXCR_RXEN;
  349. writel(val, priv->iobase + AVE_RXCR);
  350. writel(0, priv->iobase + AVE_DESCC);
  351. ret = readl_poll_timeout(priv->iobase + AVE_DESCC, val, !val,
  352. AVE_HALT_TIMEOUT_USEC);
  353. if (ret)
  354. pr_warn("%s: halt timeout\n", priv->phydev->dev->name);
  355. writel(AVE_GRR_GRST, priv->iobase + AVE_GRR);
  356. phy_shutdown(priv->phydev);
  357. }
  358. static void ave_reset(struct ave_private *priv)
  359. {
  360. u32 val;
  361. /* reset RMII register */
  362. val = readl(priv->iobase + AVE_RSTCTRL);
  363. val &= ~AVE_RSTCTRL_RMIIRST;
  364. writel(val, priv->iobase + AVE_RSTCTRL);
  365. /* assert reset */
  366. writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->iobase + AVE_GRR);
  367. mdelay(AVE_GRST_DELAY_MSEC);
  368. /* 1st, negate PHY reset only */
  369. writel(AVE_GRR_GRST, priv->iobase + AVE_GRR);
  370. mdelay(AVE_GRST_DELAY_MSEC);
  371. /* negate reset */
  372. writel(0, priv->iobase + AVE_GRR);
  373. mdelay(AVE_GRST_DELAY_MSEC);
  374. /* negate RMII register */
  375. val = readl(priv->iobase + AVE_RSTCTRL);
  376. val |= AVE_RSTCTRL_RMIIRST;
  377. writel(val, priv->iobase + AVE_RSTCTRL);
  378. }
  379. static int ave_start(struct udevice *dev)
  380. {
  381. struct ave_private *priv = dev_get_priv(dev);
  382. uintptr_t paddr;
  383. u32 val;
  384. int i;
  385. ave_reset(priv);
  386. priv->rx_pos = 0;
  387. priv->rx_off = 2; /* RX data has 2byte offsets */
  388. priv->tx_num = 0;
  389. priv->tx_adj_buf =
  390. (void *)roundup((uintptr_t)&priv->tx_adj_packetbuf[0],
  391. PKTALIGN);
  392. priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off);
  393. val = 0;
  394. if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII)
  395. val |= AVE_CFGR_MII;
  396. writel(val, priv->iobase + AVE_CFGR);
  397. /* use one descriptor for Tx */
  398. writel(AVE_DESC_SIZE(priv, 1) << 16, priv->iobase + AVE_TXDC);
  399. ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, 0);
  400. ave_desc_write_addr(priv, AVE_DESCID_TX, 0, 0);
  401. /* use PKTBUFSRX descriptors for Rx */
  402. writel(AVE_DESC_SIZE(priv, PKTBUFSRX) << 16, priv->iobase + AVE_RXDC);
  403. for (i = 0; i < PKTBUFSRX; i++) {
  404. paddr = (uintptr_t)net_rx_packets[i];
  405. ave_cache_flush(paddr, priv->rx_siz + priv->rx_off);
  406. ave_desc_write_addr(priv, AVE_DESCID_RX, i, paddr);
  407. ave_desc_write_cmdsts(priv, AVE_DESCID_RX, i, priv->rx_siz);
  408. }
  409. writel(AVE_GISR_CLR, priv->iobase + AVE_GISR);
  410. writel(AVE_GIMR_CLR, priv->iobase + AVE_GIMR);
  411. writel(AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_FLOCTR | AVE_RXCR_MTU,
  412. priv->iobase + AVE_RXCR);
  413. writel(AVE_DESCC_RD0 | AVE_DESCC_TD, priv->iobase + AVE_DESCC);
  414. phy_startup(priv->phydev);
  415. ave_adjust_link(priv);
  416. return 0;
  417. }
  418. static int ave_write_hwaddr(struct udevice *dev)
  419. {
  420. struct ave_private *priv = dev_get_priv(dev);
  421. struct eth_pdata *pdata = dev_get_platdata(dev);
  422. u8 *mac = pdata->enetaddr;
  423. writel(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24,
  424. priv->iobase + AVE_RXMAC1R);
  425. writel(mac[4] | mac[5] << 8, priv->iobase + AVE_RXMAC2R);
  426. return 0;
  427. }
  428. static int ave_send(struct udevice *dev, void *packet, int length)
  429. {
  430. struct ave_private *priv = dev_get_priv(dev);
  431. u32 val;
  432. void *ptr = packet;
  433. int count;
  434. /* adjust alignment for descriptor */
  435. if ((uintptr_t)ptr & 0x3) {
  436. memcpy(priv->tx_adj_buf, (const void *)ptr, length);
  437. ptr = priv->tx_adj_buf;
  438. }
  439. /* padding for minimum length */
  440. if (length < AVE_MIN_XMITSIZE) {
  441. memset(ptr + length, 0, AVE_MIN_XMITSIZE - length);
  442. length = AVE_MIN_XMITSIZE;
  443. }
  444. /* check ownership and wait for previous xmit done */
  445. count = AVE_SEND_TIMEOUT_COUNT;
  446. do {
  447. val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0);
  448. } while ((val & AVE_STS_OWN) && --count);
  449. if (!count)
  450. return -ETIMEDOUT;
  451. ave_cache_flush((uintptr_t)ptr, length);
  452. ave_desc_write_addr(priv, AVE_DESCID_TX, 0, (uintptr_t)ptr);
  453. val = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST |
  454. (length & AVE_STS_PKTLEN_TX_MASK);
  455. ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, val);
  456. priv->tx_num++;
  457. count = AVE_SEND_TIMEOUT_COUNT;
  458. do {
  459. val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0);
  460. } while ((val & AVE_STS_OWN) && --count);
  461. if (!count)
  462. return -ETIMEDOUT;
  463. if (!(val & AVE_STS_OK))
  464. pr_warn("%s: bad send packet status:%08x\n",
  465. priv->phydev->dev->name, le32_to_cpu(val));
  466. return 0;
  467. }
  468. static int ave_recv(struct udevice *dev, int flags, uchar **packetp)
  469. {
  470. struct ave_private *priv = dev_get_priv(dev);
  471. uchar *ptr;
  472. int length = 0;
  473. u32 cmdsts;
  474. while (1) {
  475. cmdsts = ave_desc_read_cmdsts(priv, AVE_DESCID_RX,
  476. priv->rx_pos);
  477. if (!(cmdsts & AVE_STS_OWN))
  478. /* hardware ownership, no received packets */
  479. return -EAGAIN;
  480. ptr = net_rx_packets[priv->rx_pos] + priv->rx_off;
  481. if (cmdsts & AVE_STS_OK)
  482. break;
  483. pr_warn("%s: bad packet[%d] status:%08x ptr:%p\n",
  484. priv->phydev->dev->name, priv->rx_pos,
  485. le32_to_cpu(cmdsts), ptr);
  486. }
  487. length = cmdsts & AVE_STS_PKTLEN_RX_MASK;
  488. /* invalidate after DMA is done */
  489. ave_cache_invalidate((uintptr_t)ptr, length);
  490. *packetp = ptr;
  491. return length;
  492. }
  493. static int ave_free_packet(struct udevice *dev, uchar *packet, int length)
  494. {
  495. struct ave_private *priv = dev_get_priv(dev);
  496. ave_cache_flush((uintptr_t)net_rx_packets[priv->rx_pos],
  497. priv->rx_siz + priv->rx_off);
  498. ave_desc_write_cmdsts(priv, AVE_DESCID_RX,
  499. priv->rx_pos, priv->rx_siz);
  500. if (++priv->rx_pos >= PKTBUFSRX)
  501. priv->rx_pos = 0;
  502. return 0;
  503. }
  504. static int ave_pro4_get_pinmode(struct ave_private *priv)
  505. {
  506. u32 reg, mask, val = 0;
  507. if (priv->regmap_arg > 0)
  508. return -EINVAL;
  509. mask = SG_ETPINMODE_RMII(0);
  510. switch (priv->phy_mode) {
  511. case PHY_INTERFACE_MODE_RMII:
  512. val = SG_ETPINMODE_RMII(0);
  513. break;
  514. case PHY_INTERFACE_MODE_MII:
  515. case PHY_INTERFACE_MODE_RGMII:
  516. break;
  517. default:
  518. return -EINVAL;
  519. }
  520. regmap_read(priv->regmap, SG_ETPINMODE, &reg);
  521. reg &= ~mask;
  522. reg |= val;
  523. regmap_write(priv->regmap, SG_ETPINMODE, reg);
  524. return 0;
  525. }
  526. static int ave_ld11_get_pinmode(struct ave_private *priv)
  527. {
  528. u32 reg, mask, val = 0;
  529. if (priv->regmap_arg > 0)
  530. return -EINVAL;
  531. mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
  532. switch (priv->phy_mode) {
  533. case PHY_INTERFACE_MODE_INTERNAL:
  534. break;
  535. case PHY_INTERFACE_MODE_RMII:
  536. val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
  537. break;
  538. default:
  539. return -EINVAL;
  540. }
  541. regmap_read(priv->regmap, SG_ETPINMODE, &reg);
  542. reg &= ~mask;
  543. reg |= val;
  544. regmap_write(priv->regmap, SG_ETPINMODE, reg);
  545. return 0;
  546. }
  547. static int ave_ld20_get_pinmode(struct ave_private *priv)
  548. {
  549. u32 reg, mask, val = 0;
  550. if (priv->regmap_arg > 0)
  551. return -EINVAL;
  552. mask = SG_ETPINMODE_RMII(0);
  553. switch (priv->phy_mode) {
  554. case PHY_INTERFACE_MODE_RMII:
  555. val = SG_ETPINMODE_RMII(0);
  556. break;
  557. case PHY_INTERFACE_MODE_RGMII:
  558. break;
  559. default:
  560. return -EINVAL;
  561. }
  562. regmap_read(priv->regmap, SG_ETPINMODE, &reg);
  563. reg &= ~mask;
  564. reg |= val;
  565. regmap_write(priv->regmap, SG_ETPINMODE, reg);
  566. return 0;
  567. }
  568. static int ave_pxs3_get_pinmode(struct ave_private *priv)
  569. {
  570. u32 reg, mask, val = 0;
  571. if (priv->regmap_arg > 1)
  572. return -EINVAL;
  573. mask = SG_ETPINMODE_RMII(priv->regmap_arg);
  574. switch (priv->phy_mode) {
  575. case PHY_INTERFACE_MODE_RMII:
  576. val = SG_ETPINMODE_RMII(priv->regmap_arg);
  577. break;
  578. case PHY_INTERFACE_MODE_RGMII:
  579. break;
  580. default:
  581. return -EINVAL;
  582. }
  583. regmap_read(priv->regmap, SG_ETPINMODE, &reg);
  584. reg &= ~mask;
  585. reg |= val;
  586. regmap_write(priv->regmap, SG_ETPINMODE, reg);
  587. return 0;
  588. }
  589. static int ave_ofdata_to_platdata(struct udevice *dev)
  590. {
  591. struct eth_pdata *pdata = dev_get_platdata(dev);
  592. struct ave_private *priv = dev_get_priv(dev);
  593. struct ofnode_phandle_args args;
  594. const char *phy_mode;
  595. const u32 *valp;
  596. int ret, nc, nr;
  597. const char *name;
  598. priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev);
  599. if (!priv->data)
  600. return -EINVAL;
  601. pdata->iobase = dev_read_addr(dev);
  602. pdata->phy_interface = -1;
  603. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  604. NULL);
  605. if (phy_mode)
  606. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  607. if (pdata->phy_interface == -1) {
  608. dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
  609. return -EINVAL;
  610. }
  611. pdata->max_speed = 0;
  612. valp = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed",
  613. NULL);
  614. if (valp)
  615. pdata->max_speed = fdt32_to_cpu(*valp);
  616. for (nc = 0; nc < AVE_MAX_CLKS; nc++) {
  617. name = priv->data->clock_names[nc];
  618. if (!name)
  619. break;
  620. ret = clk_get_by_name(dev, name, &priv->clk[nc]);
  621. if (ret) {
  622. dev_err(dev, "Failed to get clocks property: %d\n",
  623. ret);
  624. goto out_clk_free;
  625. }
  626. priv->nclks++;
  627. }
  628. for (nr = 0; nr < AVE_MAX_RSTS; nr++) {
  629. name = priv->data->reset_names[nr];
  630. if (!name)
  631. break;
  632. ret = reset_get_by_name(dev, name, &priv->rst[nr]);
  633. if (ret) {
  634. dev_err(dev, "Failed to get resets property: %d\n",
  635. ret);
  636. goto out_reset_free;
  637. }
  638. priv->nrsts++;
  639. }
  640. ret = dev_read_phandle_with_args(dev, "socionext,syscon-phy-mode",
  641. NULL, 1, 0, &args);
  642. if (ret) {
  643. dev_err(dev, "Failed to get syscon-phy-mode property: %d\n",
  644. ret);
  645. goto out_reset_free;
  646. }
  647. priv->regmap = syscon_node_to_regmap(args.node);
  648. if (IS_ERR(priv->regmap)) {
  649. ret = PTR_ERR(priv->regmap);
  650. dev_err(dev, "can't get syscon: %d\n", ret);
  651. goto out_reset_free;
  652. }
  653. if (args.args_count != 1) {
  654. ret = -EINVAL;
  655. dev_err(dev, "Invalid argument of syscon-phy-mode\n");
  656. goto out_reset_free;
  657. }
  658. priv->regmap_arg = args.args[0];
  659. return 0;
  660. out_reset_free:
  661. while (--nr >= 0)
  662. reset_free(&priv->rst[nr]);
  663. out_clk_free:
  664. while (--nc >= 0)
  665. clk_free(&priv->clk[nc]);
  666. return ret;
  667. }
  668. static int ave_probe(struct udevice *dev)
  669. {
  670. struct eth_pdata *pdata = dev_get_platdata(dev);
  671. struct ave_private *priv = dev_get_priv(dev);
  672. int ret, nc, nr;
  673. priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev);
  674. if (!priv->data)
  675. return -EINVAL;
  676. priv->iobase = pdata->iobase;
  677. priv->phy_mode = pdata->phy_interface;
  678. priv->max_speed = pdata->max_speed;
  679. ret = priv->data->get_pinmode(priv);
  680. if (ret) {
  681. dev_err(dev, "Invalid phy-mode\n");
  682. return -EINVAL;
  683. }
  684. for (nc = 0; nc < priv->nclks; nc++) {
  685. ret = clk_enable(&priv->clk[nc]);
  686. if (ret) {
  687. dev_err(dev, "Failed to enable clk: %d\n", ret);
  688. goto out_clk_release;
  689. }
  690. }
  691. for (nr = 0; nr < priv->nrsts; nr++) {
  692. ret = reset_deassert(&priv->rst[nr]);
  693. if (ret) {
  694. dev_err(dev, "Failed to deassert reset: %d\n", ret);
  695. goto out_reset_release;
  696. }
  697. }
  698. ave_reset(priv);
  699. ret = ave_mdiobus_init(priv, dev->name);
  700. if (ret) {
  701. dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
  702. goto out_reset_release;
  703. }
  704. priv->bus = miiphy_get_dev_by_name(dev->name);
  705. ret = ave_phy_init(priv, dev);
  706. if (ret) {
  707. dev_err(dev, "Failed to initialize phy: %d\n", ret);
  708. goto out_mdiobus_release;
  709. }
  710. return 0;
  711. out_mdiobus_release:
  712. mdio_unregister(priv->bus);
  713. mdio_free(priv->bus);
  714. out_reset_release:
  715. reset_release_all(priv->rst, nr);
  716. out_clk_release:
  717. clk_release_all(priv->clk, nc);
  718. return ret;
  719. }
  720. static int ave_remove(struct udevice *dev)
  721. {
  722. struct ave_private *priv = dev_get_priv(dev);
  723. free(priv->phydev);
  724. mdio_unregister(priv->bus);
  725. mdio_free(priv->bus);
  726. reset_release_all(priv->rst, priv->nrsts);
  727. clk_release_all(priv->clk, priv->nclks);
  728. return 0;
  729. }
  730. static const struct eth_ops ave_ops = {
  731. .start = ave_start,
  732. .stop = ave_stop,
  733. .send = ave_send,
  734. .recv = ave_recv,
  735. .free_pkt = ave_free_packet,
  736. .write_hwaddr = ave_write_hwaddr,
  737. };
  738. static const struct ave_soc_data ave_pro4_data = {
  739. .is_desc_64bit = false,
  740. .clock_names = {
  741. "gio", "ether", "ether-gb", "ether-phy",
  742. },
  743. .reset_names = {
  744. "gio", "ether",
  745. },
  746. .get_pinmode = ave_pro4_get_pinmode,
  747. };
  748. static const struct ave_soc_data ave_pxs2_data = {
  749. .is_desc_64bit = false,
  750. .clock_names = {
  751. "ether",
  752. },
  753. .reset_names = {
  754. "ether",
  755. },
  756. .get_pinmode = ave_pro4_get_pinmode,
  757. };
  758. static const struct ave_soc_data ave_ld11_data = {
  759. .is_desc_64bit = false,
  760. .clock_names = {
  761. "ether",
  762. },
  763. .reset_names = {
  764. "ether",
  765. },
  766. .get_pinmode = ave_ld11_get_pinmode,
  767. };
  768. static const struct ave_soc_data ave_ld20_data = {
  769. .is_desc_64bit = true,
  770. .clock_names = {
  771. "ether",
  772. },
  773. .reset_names = {
  774. "ether",
  775. },
  776. .get_pinmode = ave_ld20_get_pinmode,
  777. };
  778. static const struct ave_soc_data ave_pxs3_data = {
  779. .is_desc_64bit = false,
  780. .clock_names = {
  781. "ether",
  782. },
  783. .reset_names = {
  784. "ether",
  785. },
  786. .get_pinmode = ave_pxs3_get_pinmode,
  787. };
  788. static const struct udevice_id ave_ids[] = {
  789. {
  790. .compatible = "socionext,uniphier-pro4-ave4",
  791. .data = (ulong)&ave_pro4_data,
  792. },
  793. {
  794. .compatible = "socionext,uniphier-pxs2-ave4",
  795. .data = (ulong)&ave_pxs2_data,
  796. },
  797. {
  798. .compatible = "socionext,uniphier-ld11-ave4",
  799. .data = (ulong)&ave_ld11_data,
  800. },
  801. {
  802. .compatible = "socionext,uniphier-ld20-ave4",
  803. .data = (ulong)&ave_ld20_data,
  804. },
  805. {
  806. .compatible = "socionext,uniphier-pxs3-ave4",
  807. .data = (ulong)&ave_pxs3_data,
  808. },
  809. { /* Sentinel */ }
  810. };
  811. U_BOOT_DRIVER(ave) = {
  812. .name = "ave",
  813. .id = UCLASS_ETH,
  814. .of_match = ave_ids,
  815. .probe = ave_probe,
  816. .remove = ave_remove,
  817. .ofdata_to_platdata = ave_ofdata_to_platdata,
  818. .ops = &ave_ops,
  819. .priv_auto_alloc_size = sizeof(struct ave_private),
  820. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  821. };