smc911x.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * SMSC LAN9[12]1[567] Network driver
  4. *
  5. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <malloc.h>
  10. #include <net.h>
  11. #include <miiphy.h>
  12. #include <linux/io.h>
  13. #include <linux/delay.h>
  14. #include <linux/types.h>
  15. #include "smc911x.h"
  16. struct chip_id {
  17. u16 id;
  18. char *name;
  19. };
  20. struct smc911x_priv {
  21. #ifndef CONFIG_DM_ETH
  22. struct eth_device dev;
  23. #endif
  24. phys_addr_t iobase;
  25. const struct chip_id *chipid;
  26. unsigned char enetaddr[6];
  27. };
  28. static const struct chip_id chip_ids[] = {
  29. { CHIP_89218, "LAN89218" },
  30. { CHIP_9115, "LAN9115" },
  31. { CHIP_9116, "LAN9116" },
  32. { CHIP_9117, "LAN9117" },
  33. { CHIP_9118, "LAN9118" },
  34. { CHIP_9211, "LAN9211" },
  35. { CHIP_9215, "LAN9215" },
  36. { CHIP_9216, "LAN9216" },
  37. { CHIP_9217, "LAN9217" },
  38. { CHIP_9218, "LAN9218" },
  39. { CHIP_9220, "LAN9220" },
  40. { CHIP_9221, "LAN9221" },
  41. { 0, NULL },
  42. };
  43. #define DRIVERNAME "smc911x"
  44. #if defined (CONFIG_SMC911X_32_BIT) && \
  45. defined (CONFIG_SMC911X_16_BIT)
  46. #error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
  47. CONFIG_SMC911X_16_BIT shall be set"
  48. #endif
  49. #if defined (CONFIG_SMC911X_32_BIT)
  50. static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
  51. {
  52. return readl(priv->iobase + offset);
  53. }
  54. static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
  55. {
  56. writel(val, priv->iobase + offset);
  57. }
  58. #elif defined (CONFIG_SMC911X_16_BIT)
  59. static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
  60. {
  61. return (readw(priv->iobase + offset) & 0xffff) |
  62. (readw(priv->iobase + offset + 2) << 16);
  63. }
  64. static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
  65. {
  66. writew(val & 0xffff, priv->iobase + offset);
  67. writew(val >> 16, priv->iobase + offset + 2);
  68. }
  69. #else
  70. #error "SMC911X: undefined bus width"
  71. #endif /* CONFIG_SMC911X_16_BIT */
  72. static u32 smc911x_get_mac_csr(struct smc911x_priv *priv, u8 reg)
  73. {
  74. while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
  75. ;
  76. smc911x_reg_write(priv, MAC_CSR_CMD,
  77. MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
  78. while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
  79. ;
  80. return smc911x_reg_read(priv, MAC_CSR_DATA);
  81. }
  82. static void smc911x_set_mac_csr(struct smc911x_priv *priv, u8 reg, u32 data)
  83. {
  84. while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
  85. ;
  86. smc911x_reg_write(priv, MAC_CSR_DATA, data);
  87. smc911x_reg_write(priv, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
  88. while (smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
  89. ;
  90. }
  91. static int smc911x_detect_chip(struct smc911x_priv *priv)
  92. {
  93. unsigned long val, i;
  94. val = smc911x_reg_read(priv, BYTE_TEST);
  95. if (val == 0xffffffff) {
  96. /* Special case -- no chip present */
  97. return -1;
  98. } else if (val != 0x87654321) {
  99. printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
  100. return -1;
  101. }
  102. val = smc911x_reg_read(priv, ID_REV) >> 16;
  103. for (i = 0; chip_ids[i].id != 0; i++) {
  104. if (chip_ids[i].id == val) break;
  105. }
  106. if (!chip_ids[i].id) {
  107. printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
  108. return -1;
  109. }
  110. priv->chipid = &chip_ids[i];
  111. return 0;
  112. }
  113. static void smc911x_reset(struct smc911x_priv *priv)
  114. {
  115. int timeout;
  116. /*
  117. * Take out of PM setting first
  118. * Device is already wake up if PMT_CTRL_READY bit is set
  119. */
  120. if ((smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY) == 0) {
  121. /* Write to the bytetest will take out of powerdown */
  122. smc911x_reg_write(priv, BYTE_TEST, 0x0);
  123. timeout = 10;
  124. while (timeout-- &&
  125. !(smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY))
  126. udelay(10);
  127. if (timeout < 0) {
  128. printf(DRIVERNAME
  129. ": timeout waiting for PM restore\n");
  130. return;
  131. }
  132. }
  133. /* Disable interrupts */
  134. smc911x_reg_write(priv, INT_EN, 0);
  135. smc911x_reg_write(priv, HW_CFG, HW_CFG_SRST);
  136. timeout = 1000;
  137. while (timeout-- && smc911x_reg_read(priv, E2P_CMD) & E2P_CMD_EPC_BUSY)
  138. udelay(10);
  139. if (timeout < 0) {
  140. printf(DRIVERNAME ": reset timeout\n");
  141. return;
  142. }
  143. /* Reset the FIFO level and flow control settings */
  144. smc911x_set_mac_csr(priv, FLOW, FLOW_FCPT | FLOW_FCEN);
  145. smc911x_reg_write(priv, AFC_CFG, 0x0050287F);
  146. /* Set to LED outputs */
  147. smc911x_reg_write(priv, GPIO_CFG, 0x70070000);
  148. }
  149. static void smc911x_handle_mac_address(struct smc911x_priv *priv)
  150. {
  151. unsigned long addrh, addrl;
  152. unsigned char *m = priv->enetaddr;
  153. addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
  154. addrh = m[4] | (m[5] << 8);
  155. smc911x_set_mac_csr(priv, ADDRL, addrl);
  156. smc911x_set_mac_csr(priv, ADDRH, addrh);
  157. printf(DRIVERNAME ": MAC %pM\n", m);
  158. }
  159. static bool smc911x_read_mac_address(struct smc911x_priv *priv)
  160. {
  161. u32 addrh, addrl;
  162. /* address is obtained from optional eeprom */
  163. addrh = smc911x_get_mac_csr(priv, ADDRH);
  164. addrl = smc911x_get_mac_csr(priv, ADDRL);
  165. if (addrl == 0xffffffff && addrh == 0x0000ffff)
  166. return false;
  167. priv->enetaddr[0] = addrl;
  168. priv->enetaddr[1] = addrl >> 8;
  169. priv->enetaddr[2] = addrl >> 16;
  170. priv->enetaddr[3] = addrl >> 24;
  171. priv->enetaddr[4] = addrh;
  172. priv->enetaddr[5] = addrh >> 8;
  173. return true;
  174. }
  175. static int smc911x_eth_phy_read(struct smc911x_priv *priv,
  176. u8 phy, u8 reg, u16 *val)
  177. {
  178. while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
  179. ;
  180. smc911x_set_mac_csr(priv, MII_ACC, phy << 11 | reg << 6 |
  181. MII_ACC_MII_BUSY);
  182. while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
  183. ;
  184. *val = smc911x_get_mac_csr(priv, MII_DATA);
  185. return 0;
  186. }
  187. static int smc911x_eth_phy_write(struct smc911x_priv *priv,
  188. u8 phy, u8 reg, u16 val)
  189. {
  190. while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
  191. ;
  192. smc911x_set_mac_csr(priv, MII_DATA, val);
  193. smc911x_set_mac_csr(priv, MII_ACC,
  194. phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
  195. while (smc911x_get_mac_csr(priv, MII_ACC) & MII_ACC_MII_BUSY)
  196. ;
  197. return 0;
  198. }
  199. static int smc911x_phy_reset(struct smc911x_priv *priv)
  200. {
  201. u32 reg;
  202. reg = smc911x_reg_read(priv, PMT_CTRL);
  203. reg &= ~0xfffff030;
  204. reg |= PMT_CTRL_PHY_RST;
  205. smc911x_reg_write(priv, PMT_CTRL, reg);
  206. mdelay(100);
  207. return 0;
  208. }
  209. static void smc911x_phy_configure(struct smc911x_priv *priv)
  210. {
  211. int timeout;
  212. u16 status;
  213. smc911x_phy_reset(priv);
  214. smc911x_eth_phy_write(priv, 1, MII_BMCR, BMCR_RESET);
  215. mdelay(1);
  216. smc911x_eth_phy_write(priv, 1, MII_ADVERTISE, 0x01e1);
  217. smc911x_eth_phy_write(priv, 1, MII_BMCR, BMCR_ANENABLE |
  218. BMCR_ANRESTART);
  219. timeout = 5000;
  220. do {
  221. mdelay(1);
  222. if ((timeout--) == 0)
  223. goto err_out;
  224. if (smc911x_eth_phy_read(priv, 1, MII_BMSR, &status) != 0)
  225. goto err_out;
  226. } while (!(status & BMSR_LSTATUS));
  227. printf(DRIVERNAME ": phy initialized\n");
  228. return;
  229. err_out:
  230. printf(DRIVERNAME ": autonegotiation timed out\n");
  231. }
  232. static void smc911x_enable(struct smc911x_priv *priv)
  233. {
  234. /* Enable TX */
  235. smc911x_reg_write(priv, HW_CFG, 8 << 16 | HW_CFG_SF);
  236. smc911x_reg_write(priv, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
  237. smc911x_reg_write(priv, TX_CFG, TX_CFG_TX_ON);
  238. /* no padding to start of packets */
  239. smc911x_reg_write(priv, RX_CFG, 0);
  240. smc911x_set_mac_csr(priv, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
  241. MAC_CR_HBDIS);
  242. }
  243. static int smc911x_init_common(struct smc911x_priv *priv)
  244. {
  245. const struct chip_id *id = priv->chipid;
  246. printf(DRIVERNAME ": detected %s controller\n", id->name);
  247. smc911x_reset(priv);
  248. /* Configure the PHY, initialize the link state */
  249. smc911x_phy_configure(priv);
  250. smc911x_handle_mac_address(priv);
  251. /* Turn on Tx + Rx */
  252. smc911x_enable(priv);
  253. return 0;
  254. }
  255. static int smc911x_send_common(struct smc911x_priv *priv,
  256. void *packet, int length)
  257. {
  258. u32 *data = (u32*)packet;
  259. u32 tmplen;
  260. u32 status;
  261. smc911x_reg_write(priv, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG |
  262. TX_CMD_A_INT_LAST_SEG | length);
  263. smc911x_reg_write(priv, TX_DATA_FIFO, length);
  264. tmplen = (length + 3) / 4;
  265. while (tmplen--)
  266. smc911x_reg_write(priv, TX_DATA_FIFO, *data++);
  267. /* wait for transmission */
  268. while (!((smc911x_reg_read(priv, TX_FIFO_INF) &
  269. TX_FIFO_INF_TSUSED) >> 16));
  270. /* get status. Ignore 'no carrier' error, it has no meaning for
  271. * full duplex operation
  272. */
  273. status = smc911x_reg_read(priv, TX_STATUS_FIFO) &
  274. (TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL |
  275. TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
  276. if (!status)
  277. return 0;
  278. printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
  279. status & TX_STS_LOC ? "TX_STS_LOC " : "",
  280. status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
  281. status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
  282. status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "",
  283. status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : "");
  284. return -1;
  285. }
  286. static void smc911x_halt_common(struct smc911x_priv *priv)
  287. {
  288. smc911x_reset(priv);
  289. smc911x_handle_mac_address(priv);
  290. }
  291. static int smc911x_recv_common(struct smc911x_priv *priv, u32 *data)
  292. {
  293. u32 pktlen, tmplen;
  294. u32 status;
  295. status = smc911x_reg_read(priv, RX_FIFO_INF);
  296. if (!(status & RX_FIFO_INF_RXSUSED))
  297. return 0;
  298. status = smc911x_reg_read(priv, RX_STATUS_FIFO);
  299. pktlen = (status & RX_STS_PKT_LEN) >> 16;
  300. smc911x_reg_write(priv, RX_CFG, 0);
  301. tmplen = (pktlen + 3) / 4;
  302. while (tmplen--)
  303. *data++ = smc911x_reg_read(priv, RX_DATA_FIFO);
  304. if (status & RX_STS_ES) {
  305. printf(DRIVERNAME
  306. ": dropped bad packet. Status: 0x%08x\n",
  307. status);
  308. return 0;
  309. }
  310. return pktlen;
  311. }
  312. #ifndef CONFIG_DM_ETH
  313. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  314. /* wrapper for smc911x_eth_phy_read */
  315. static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
  316. int reg)
  317. {
  318. struct eth_device *dev = eth_get_dev_by_name(bus->name);
  319. struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
  320. u16 val = 0;
  321. int ret;
  322. if (!dev || !priv)
  323. return -ENODEV;
  324. ret = smc911x_eth_phy_read(priv, phy, reg, &val);
  325. if (ret < 0)
  326. return ret;
  327. return val;
  328. }
  329. /* wrapper for smc911x_eth_phy_write */
  330. static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
  331. int reg, u16 val)
  332. {
  333. struct eth_device *dev = eth_get_dev_by_name(bus->name);
  334. struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
  335. if (!dev || !priv)
  336. return -ENODEV;
  337. return smc911x_eth_phy_write(priv, phy, reg, val);
  338. }
  339. static int smc911x_initialize_mii(struct smc911x_priv *priv)
  340. {
  341. struct mii_dev *mdiodev = mdio_alloc();
  342. int ret;
  343. if (!mdiodev)
  344. return -ENOMEM;
  345. strncpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN);
  346. mdiodev->read = smc911x_miiphy_read;
  347. mdiodev->write = smc911x_miiphy_write;
  348. ret = mdio_register(mdiodev);
  349. if (ret < 0) {
  350. mdio_free(mdiodev);
  351. return ret;
  352. }
  353. return 0;
  354. }
  355. #else
  356. static int smc911x_initialize_mii(struct smc911x_priv *priv)
  357. {
  358. return 0;
  359. }
  360. #endif
  361. static int smc911x_init(struct eth_device *dev, struct bd_info *bd)
  362. {
  363. struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
  364. return smc911x_init_common(priv);
  365. }
  366. static void smc911x_halt(struct eth_device *dev)
  367. {
  368. struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
  369. smc911x_halt_common(priv);
  370. }
  371. static int smc911x_send(struct eth_device *dev, void *packet, int length)
  372. {
  373. struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
  374. return smc911x_send_common(priv, packet, length);
  375. }
  376. static int smc911x_recv(struct eth_device *dev)
  377. {
  378. struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
  379. u32 *data = (u32 *)net_rx_packets[0];
  380. int ret;
  381. ret = smc911x_recv_common(priv, data);
  382. if (ret)
  383. net_process_received_packet(net_rx_packets[0], ret);
  384. return ret;
  385. }
  386. int smc911x_initialize(u8 dev_num, int base_addr)
  387. {
  388. struct smc911x_priv *priv;
  389. int ret;
  390. priv = calloc(1, sizeof(*priv));
  391. if (!priv)
  392. return -ENOMEM;
  393. priv->iobase = base_addr;
  394. priv->dev.iobase = base_addr;
  395. /* Try to detect chip. Will fail if not present. */
  396. ret = smc911x_detect_chip(priv);
  397. if (ret) {
  398. ret = 0; /* Card not detected is not an error */
  399. goto err_detect;
  400. }
  401. if (smc911x_read_mac_address(priv))
  402. memcpy(priv->dev.enetaddr, priv->enetaddr, 6);
  403. priv->dev.init = smc911x_init;
  404. priv->dev.halt = smc911x_halt;
  405. priv->dev.send = smc911x_send;
  406. priv->dev.recv = smc911x_recv;
  407. sprintf(priv->dev.name, "%s-%hu", DRIVERNAME, dev_num);
  408. eth_register(&priv->dev);
  409. ret = smc911x_initialize_mii(priv);
  410. if (ret)
  411. goto err_mii;
  412. return 1;
  413. err_mii:
  414. eth_unregister(&priv->dev);
  415. err_detect:
  416. free(priv);
  417. return ret;
  418. }
  419. #else /* ifdef CONFIG_DM_ETH */
  420. static int smc911x_start(struct udevice *dev)
  421. {
  422. struct eth_pdata *plat = dev_get_platdata(dev);
  423. struct smc911x_priv *priv = dev_get_priv(dev);
  424. memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
  425. return smc911x_init_common(priv);
  426. }
  427. static void smc911x_stop(struct udevice *dev)
  428. {
  429. struct smc911x_priv *priv = dev_get_priv(dev);
  430. smc911x_halt_common(priv);
  431. }
  432. static int smc911x_send(struct udevice *dev, void *packet, int length)
  433. {
  434. struct smc911x_priv *priv = dev_get_priv(dev);
  435. int ret;
  436. ret = smc911x_send_common(priv, packet, length);
  437. return ret ? 0 : -ETIMEDOUT;
  438. }
  439. static int smc911x_recv(struct udevice *dev, int flags, uchar **packetp)
  440. {
  441. struct smc911x_priv *priv = dev_get_priv(dev);
  442. u32 *data = (u32 *)net_rx_packets[0];
  443. int ret;
  444. ret = smc911x_recv_common(priv, data);
  445. if (ret)
  446. *packetp = (void *)data;
  447. return ret ? ret : -EAGAIN;
  448. }
  449. static int smc911x_read_rom_hwaddr(struct udevice *dev)
  450. {
  451. struct smc911x_priv *priv = dev_get_priv(dev);
  452. struct eth_pdata *pdata = dev_get_platdata(dev);
  453. if (!smc911x_read_mac_address(priv))
  454. return -ENODEV;
  455. memcpy(pdata->enetaddr, priv->enetaddr, sizeof(pdata->enetaddr));
  456. return 0;
  457. }
  458. static int smc911x_bind(struct udevice *dev)
  459. {
  460. return device_set_name(dev, dev->name);
  461. }
  462. static int smc911x_probe(struct udevice *dev)
  463. {
  464. struct smc911x_priv *priv = dev_get_priv(dev);
  465. int ret;
  466. /* Try to detect chip. Will fail if not present. */
  467. ret = smc911x_detect_chip(priv);
  468. if (ret)
  469. return ret;
  470. smc911x_read_rom_hwaddr(dev);
  471. return 0;
  472. }
  473. static int smc911x_ofdata_to_platdata(struct udevice *dev)
  474. {
  475. struct smc911x_priv *priv = dev_get_priv(dev);
  476. struct eth_pdata *pdata = dev_get_platdata(dev);
  477. pdata->iobase = dev_read_addr(dev);
  478. priv->iobase = pdata->iobase;
  479. return 0;
  480. }
  481. static const struct eth_ops smc911x_ops = {
  482. .start = smc911x_start,
  483. .send = smc911x_send,
  484. .recv = smc911x_recv,
  485. .stop = smc911x_stop,
  486. .read_rom_hwaddr = smc911x_read_rom_hwaddr,
  487. };
  488. static const struct udevice_id smc911x_ids[] = {
  489. { .compatible = "smsc,lan9115" },
  490. { }
  491. };
  492. U_BOOT_DRIVER(smc911x) = {
  493. .name = "eth_smc911x",
  494. .id = UCLASS_ETH,
  495. .of_match = smc911x_ids,
  496. .bind = smc911x_bind,
  497. .ofdata_to_platdata = smc911x_ofdata_to_platdata,
  498. .probe = smc911x_probe,
  499. .ops = &smc911x_ops,
  500. .priv_auto_alloc_size = sizeof(struct smc911x_priv),
  501. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  502. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  503. };
  504. #endif