rtl8169.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * rtl8169.c : U-Boot driver for the RealTek RTL8169
  4. *
  5. * Masami Komiya (mkomiya@sonare.it)
  6. *
  7. * Most part is taken from r8169.c of etherboot
  8. *
  9. */
  10. /**************************************************************************
  11. * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
  12. * Written 2003 by Timothy Legge <tlegge@rogers.com>
  13. *
  14. * Portions of this code based on:
  15. * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
  16. * for Linux kernel 2.4.x.
  17. *
  18. * Written 2002 ShuChen <shuchen@realtek.com.tw>
  19. * See Linux Driver for full information
  20. *
  21. * Linux Driver Version 1.27a, 10.02.2002
  22. *
  23. * Thanks to:
  24. * Jean Chen of RealTek Semiconductor Corp. for
  25. * providing the evaluation NIC used to develop
  26. * this driver. RealTek's support for Etherboot
  27. * is appreciated.
  28. *
  29. * REVISION HISTORY:
  30. * ================
  31. *
  32. * v1.0 11-26-2003 timlegge Initial port of Linux driver
  33. * v1.5 01-17-2004 timlegge Initial driver output cleanup
  34. *
  35. * Indent Options: indent -kr -i8
  36. ***************************************************************************/
  37. /*
  38. * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
  39. * Modified to use le32_to_cpu and cpu_to_le32 properly
  40. */
  41. #include <common.h>
  42. #include <cpu_func.h>
  43. #include <dm.h>
  44. #include <errno.h>
  45. #include <log.h>
  46. #include <malloc.h>
  47. #include <memalign.h>
  48. #include <net.h>
  49. #ifndef CONFIG_DM_ETH
  50. #include <netdev.h>
  51. #endif
  52. #include <asm/cache.h>
  53. #include <asm/io.h>
  54. #include <pci.h>
  55. #include <linux/delay.h>
  56. #undef DEBUG_RTL8169
  57. #undef DEBUG_RTL8169_TX
  58. #undef DEBUG_RTL8169_RX
  59. #define drv_version "v1.5"
  60. #define drv_date "01-17-2004"
  61. static unsigned long ioaddr;
  62. /* Condensed operations for readability. */
  63. #define currticks() get_timer(0)
  64. /* media options */
  65. #define MAX_UNITS 8
  66. static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
  67. /* MAC address length*/
  68. #define MAC_ADDR_LEN 6
  69. /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
  70. #define MAX_ETH_FRAME_SIZE 1536
  71. #define TX_FIFO_THRESH 256 /* In bytes */
  72. #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  73. #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
  74. #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
  75. #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
  76. #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
  77. #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
  78. #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
  79. #ifdef CONFIG_SYS_RX_ETH_BUFFER
  80. #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER
  81. #else
  82. #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
  83. #endif
  84. #define RX_BUF_SIZE 1536 /* Rx Buffer size */
  85. #define RX_BUF_LEN 8192
  86. #define RTL_MIN_IO_SIZE 0x80
  87. #define TX_TIMEOUT (6*HZ)
  88. /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
  89. #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg))
  90. #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg))
  91. #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg))
  92. #define RTL_R8(reg) readb(ioaddr + (reg))
  93. #define RTL_R16(reg) readw(ioaddr + (reg))
  94. #define RTL_R32(reg) readl(ioaddr + (reg))
  95. #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
  96. (pci_addr_t)(unsigned long)a)
  97. #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
  98. (phys_addr_t)a)
  99. enum RTL8169_registers {
  100. MAC0 = 0, /* Ethernet hardware address. */
  101. MAR0 = 8, /* Multicast filter. */
  102. TxDescStartAddrLow = 0x20,
  103. TxDescStartAddrHigh = 0x24,
  104. TxHDescStartAddrLow = 0x28,
  105. TxHDescStartAddrHigh = 0x2c,
  106. FLASH = 0x30,
  107. ERSR = 0x36,
  108. ChipCmd = 0x37,
  109. TxPoll = 0x38,
  110. IntrMask = 0x3C,
  111. IntrStatus = 0x3E,
  112. TxConfig = 0x40,
  113. RxConfig = 0x44,
  114. RxMissed = 0x4C,
  115. Cfg9346 = 0x50,
  116. Config0 = 0x51,
  117. Config1 = 0x52,
  118. Config2 = 0x53,
  119. Config3 = 0x54,
  120. Config4 = 0x55,
  121. Config5 = 0x56,
  122. MultiIntr = 0x5C,
  123. PHYAR = 0x60,
  124. TBICSR = 0x64,
  125. TBI_ANAR = 0x68,
  126. TBI_LPAR = 0x6A,
  127. PHYstatus = 0x6C,
  128. RxMaxSize = 0xDA,
  129. CPlusCmd = 0xE0,
  130. RxDescStartAddrLow = 0xE4,
  131. RxDescStartAddrHigh = 0xE8,
  132. EarlyTxThres = 0xEC,
  133. FuncEvent = 0xF0,
  134. FuncEventMask = 0xF4,
  135. FuncPresetState = 0xF8,
  136. FuncForceEvent = 0xFC,
  137. };
  138. enum RTL8169_register_content {
  139. /*InterruptStatusBits */
  140. SYSErr = 0x8000,
  141. PCSTimeout = 0x4000,
  142. SWInt = 0x0100,
  143. TxDescUnavail = 0x80,
  144. RxFIFOOver = 0x40,
  145. RxUnderrun = 0x20,
  146. RxOverflow = 0x10,
  147. TxErr = 0x08,
  148. TxOK = 0x04,
  149. RxErr = 0x02,
  150. RxOK = 0x01,
  151. /*RxStatusDesc */
  152. RxRES = 0x00200000,
  153. RxCRC = 0x00080000,
  154. RxRUNT = 0x00100000,
  155. RxRWT = 0x00400000,
  156. /*ChipCmdBits */
  157. CmdReset = 0x10,
  158. CmdRxEnb = 0x08,
  159. CmdTxEnb = 0x04,
  160. RxBufEmpty = 0x01,
  161. /*Cfg9346Bits */
  162. Cfg9346_Lock = 0x00,
  163. Cfg9346_Unlock = 0xC0,
  164. /*rx_mode_bits */
  165. AcceptErr = 0x20,
  166. AcceptRunt = 0x10,
  167. AcceptBroadcast = 0x08,
  168. AcceptMulticast = 0x04,
  169. AcceptMyPhys = 0x02,
  170. AcceptAllPhys = 0x01,
  171. /*RxConfigBits */
  172. RxCfgFIFOShift = 13,
  173. RxCfgDMAShift = 8,
  174. /*TxConfigBits */
  175. TxInterFrameGapShift = 24,
  176. TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
  177. /*rtl8169_PHYstatus */
  178. TBI_Enable = 0x80,
  179. TxFlowCtrl = 0x40,
  180. RxFlowCtrl = 0x20,
  181. _1000bpsF = 0x10,
  182. _100bps = 0x08,
  183. _10bps = 0x04,
  184. LinkStatus = 0x02,
  185. FullDup = 0x01,
  186. /*GIGABIT_PHY_registers */
  187. PHY_CTRL_REG = 0,
  188. PHY_STAT_REG = 1,
  189. PHY_AUTO_NEGO_REG = 4,
  190. PHY_1000_CTRL_REG = 9,
  191. /*GIGABIT_PHY_REG_BIT */
  192. PHY_Restart_Auto_Nego = 0x0200,
  193. PHY_Enable_Auto_Nego = 0x1000,
  194. /* PHY_STAT_REG = 1; */
  195. PHY_Auto_Nego_Comp = 0x0020,
  196. /* PHY_AUTO_NEGO_REG = 4; */
  197. PHY_Cap_10_Half = 0x0020,
  198. PHY_Cap_10_Full = 0x0040,
  199. PHY_Cap_100_Half = 0x0080,
  200. PHY_Cap_100_Full = 0x0100,
  201. /* PHY_1000_CTRL_REG = 9; */
  202. PHY_Cap_1000_Full = 0x0200,
  203. PHY_Cap_Null = 0x0,
  204. /*_MediaType*/
  205. _10_Half = 0x01,
  206. _10_Full = 0x02,
  207. _100_Half = 0x04,
  208. _100_Full = 0x08,
  209. _1000_Full = 0x10,
  210. /*_TBICSRBit*/
  211. TBILinkOK = 0x02000000,
  212. /* FuncEvent/Misc */
  213. RxDv_Gated_En = 0x80000,
  214. };
  215. static struct {
  216. const char *name;
  217. u8 version; /* depend on RTL8169 docs */
  218. u32 RxConfigMask; /* should clear the bits supported by this chip */
  219. } rtl_chip_info[] = {
  220. {"RTL-8169", 0x00, 0xff7e1880,},
  221. {"RTL-8169", 0x04, 0xff7e1880,},
  222. {"RTL-8169", 0x00, 0xff7e1880,},
  223. {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
  224. {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
  225. {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
  226. {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
  227. {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
  228. {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
  229. {"RTL-8168c/8111c", 0x3c, 0xff7e1880,},
  230. {"RTL-8168d/8111d", 0x28, 0xff7e1880,},
  231. {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
  232. {"RTL-8168/8111g", 0x4c, 0xff7e1880,},
  233. {"RTL-8101e", 0x34, 0xff7e1880,},
  234. {"RTL-8100e", 0x32, 0xff7e1880,},
  235. {"RTL-8168h/8111h", 0x54, 0xff7e1880,},
  236. };
  237. enum _DescStatusBit {
  238. OWNbit = 0x80000000,
  239. EORbit = 0x40000000,
  240. FSbit = 0x20000000,
  241. LSbit = 0x10000000,
  242. };
  243. struct TxDesc {
  244. u32 status;
  245. u32 vlan_tag;
  246. u32 buf_addr;
  247. u32 buf_Haddr;
  248. };
  249. struct RxDesc {
  250. u32 status;
  251. u32 vlan_tag;
  252. u32 buf_addr;
  253. u32 buf_Haddr;
  254. };
  255. static unsigned char rxdata[RX_BUF_LEN];
  256. #define RTL8169_DESC_SIZE 16
  257. #if ARCH_DMA_MINALIGN > 256
  258. # define RTL8169_ALIGN ARCH_DMA_MINALIGN
  259. #else
  260. # define RTL8169_ALIGN 256
  261. #endif
  262. /*
  263. * Warn if the cache-line size is larger than the descriptor size. In such
  264. * cases the driver will likely fail because the CPU needs to flush the cache
  265. * when requeuing RX buffers, therefore descriptors written by the hardware
  266. * may be discarded.
  267. *
  268. * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
  269. * the driver to allocate descriptors from a pool of non-cached memory.
  270. */
  271. #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
  272. #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
  273. !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
  274. #warning cache-line size is larger than descriptor size
  275. #endif
  276. #endif
  277. /*
  278. * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
  279. * descriptors point to a part of this buffer.
  280. */
  281. DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
  282. /*
  283. * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
  284. * descriptors point to a part of this buffer.
  285. */
  286. DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
  287. struct rtl8169_private {
  288. ulong iobase;
  289. void *mmio_addr; /* memory map physical address */
  290. int chipset;
  291. unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
  292. unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
  293. unsigned long dirty_tx;
  294. struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
  295. struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
  296. unsigned char *RxBufferRings; /* Index of Rx Buffer */
  297. unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
  298. unsigned char *Tx_skbuff[NUM_TX_DESC];
  299. } tpx;
  300. static struct rtl8169_private *tpc;
  301. static const unsigned int rtl8169_rx_config =
  302. (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
  303. static struct pci_device_id supported[] = {
  304. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
  305. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
  306. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
  307. {}
  308. };
  309. void mdio_write(int RegAddr, int value)
  310. {
  311. int i;
  312. RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
  313. udelay(1000);
  314. for (i = 2000; i > 0; i--) {
  315. /* Check if the RTL8169 has completed writing to the specified MII register */
  316. if (!(RTL_R32(PHYAR) & 0x80000000)) {
  317. break;
  318. } else {
  319. udelay(100);
  320. }
  321. }
  322. }
  323. int mdio_read(int RegAddr)
  324. {
  325. int i, value = -1;
  326. RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
  327. udelay(1000);
  328. for (i = 2000; i > 0; i--) {
  329. /* Check if the RTL8169 has completed retrieving data from the specified MII register */
  330. if (RTL_R32(PHYAR) & 0x80000000) {
  331. value = (int) (RTL_R32(PHYAR) & 0xFFFF);
  332. break;
  333. } else {
  334. udelay(100);
  335. }
  336. }
  337. return value;
  338. }
  339. static int rtl8169_init_board(unsigned long dev_iobase, const char *name)
  340. {
  341. int i;
  342. u32 tmp;
  343. #ifdef DEBUG_RTL8169
  344. printf ("%s\n", __FUNCTION__);
  345. #endif
  346. ioaddr = dev_iobase;
  347. /* Soft reset the chip. */
  348. RTL_W8(ChipCmd, CmdReset);
  349. /* Check that the chip has finished the reset. */
  350. for (i = 1000; i > 0; i--)
  351. if ((RTL_R8(ChipCmd) & CmdReset) == 0)
  352. break;
  353. else
  354. udelay(10);
  355. /* identify chip attached to board */
  356. tmp = RTL_R32(TxConfig);
  357. tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
  358. for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
  359. if (tmp == rtl_chip_info[i].version) {
  360. tpc->chipset = i;
  361. goto match;
  362. }
  363. }
  364. /* if unknown chip, assume array element #0, original RTL-8169 in this case */
  365. printf("PCI device %s: unknown chip version, assuming RTL-8169\n",
  366. name);
  367. printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
  368. tpc->chipset = 0;
  369. match:
  370. return 0;
  371. }
  372. /*
  373. * TX and RX descriptors are 16 bytes. This causes problems with the cache
  374. * maintenance on CPUs where the cache-line size exceeds the size of these
  375. * descriptors. What will happen is that when the driver receives a packet
  376. * it will be immediately requeued for the hardware to reuse. The CPU will
  377. * therefore need to flush the cache-line containing the descriptor, which
  378. * will cause all other descriptors in the same cache-line to be flushed
  379. * along with it. If one of those descriptors had been written to by the
  380. * device those changes (and the associated packet) will be lost.
  381. *
  382. * To work around this, we make use of non-cached memory if available. If
  383. * descriptors are mapped uncached there's no need to manually flush them
  384. * or invalidate them.
  385. *
  386. * Note that this only applies to descriptors. The packet data buffers do
  387. * not have the same constraints since they are 1536 bytes large, so they
  388. * are unlikely to share cache-lines.
  389. */
  390. static void *rtl_alloc_descs(unsigned int num)
  391. {
  392. size_t size = num * RTL8169_DESC_SIZE;
  393. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  394. return (void *)noncached_alloc(size, RTL8169_ALIGN);
  395. #else
  396. return memalign(RTL8169_ALIGN, size);
  397. #endif
  398. }
  399. /*
  400. * Cache maintenance functions. These are simple wrappers around the more
  401. * general purpose flush_cache() and invalidate_dcache_range() functions.
  402. */
  403. static void rtl_inval_rx_desc(struct RxDesc *desc)
  404. {
  405. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  406. unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
  407. unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
  408. invalidate_dcache_range(start, end);
  409. #endif
  410. }
  411. static void rtl_flush_rx_desc(struct RxDesc *desc)
  412. {
  413. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  414. flush_cache((unsigned long)desc, sizeof(*desc));
  415. #endif
  416. }
  417. static void rtl_inval_tx_desc(struct TxDesc *desc)
  418. {
  419. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  420. unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
  421. unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
  422. invalidate_dcache_range(start, end);
  423. #endif
  424. }
  425. static void rtl_flush_tx_desc(struct TxDesc *desc)
  426. {
  427. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  428. flush_cache((unsigned long)desc, sizeof(*desc));
  429. #endif
  430. }
  431. static void rtl_inval_buffer(void *buf, size_t size)
  432. {
  433. unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
  434. unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
  435. invalidate_dcache_range(start, end);
  436. }
  437. static void rtl_flush_buffer(void *buf, size_t size)
  438. {
  439. flush_cache((unsigned long)buf, size);
  440. }
  441. /**************************************************************************
  442. RECV - Receive a frame
  443. ***************************************************************************/
  444. #ifdef CONFIG_DM_ETH
  445. static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
  446. uchar **packetp)
  447. #else
  448. static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
  449. uchar **packetp)
  450. #endif
  451. {
  452. /* return true if there's an ethernet packet ready to read */
  453. /* nic->packet should contain data on return */
  454. /* nic->packetlen should contain length of data */
  455. int cur_rx;
  456. int length = 0;
  457. #ifdef DEBUG_RTL8169_RX
  458. printf ("%s\n", __FUNCTION__);
  459. #endif
  460. ioaddr = dev_iobase;
  461. cur_rx = tpc->cur_rx;
  462. rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
  463. if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
  464. if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
  465. length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
  466. status) & 0x00001FFF) - 4;
  467. rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
  468. memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
  469. if (cur_rx == NUM_RX_DESC - 1)
  470. tpc->RxDescArray[cur_rx].status =
  471. cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
  472. else
  473. tpc->RxDescArray[cur_rx].status =
  474. cpu_to_le32(OWNbit + RX_BUF_SIZE);
  475. #ifdef CONFIG_DM_ETH
  476. tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
  477. dm_pci_mem_to_phys(dev,
  478. (pci_addr_t)(unsigned long)
  479. tpc->RxBufferRing[cur_rx]));
  480. #else
  481. tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
  482. pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
  483. tpc->RxBufferRing[cur_rx]));
  484. #endif
  485. rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
  486. #ifdef CONFIG_DM_ETH
  487. *packetp = rxdata;
  488. #else
  489. net_process_received_packet(rxdata, length);
  490. #endif
  491. } else {
  492. puts("Error Rx");
  493. length = -EIO;
  494. }
  495. cur_rx = (cur_rx + 1) % NUM_RX_DESC;
  496. tpc->cur_rx = cur_rx;
  497. return length;
  498. } else {
  499. ushort sts = RTL_R8(IntrStatus);
  500. RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
  501. udelay(100); /* wait */
  502. }
  503. tpc->cur_rx = cur_rx;
  504. return (0); /* initially as this is called to flush the input */
  505. }
  506. #ifdef CONFIG_DM_ETH
  507. int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  508. {
  509. struct rtl8169_private *priv = dev_get_priv(dev);
  510. return rtl_recv_common(dev, priv->iobase, packetp);
  511. }
  512. #else
  513. static int rtl_recv(struct eth_device *dev)
  514. {
  515. return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv,
  516. dev->iobase, NULL);
  517. }
  518. #endif /* nCONFIG_DM_ETH */
  519. #define HZ 1000
  520. /**************************************************************************
  521. SEND - Transmit a frame
  522. ***************************************************************************/
  523. #ifdef CONFIG_DM_ETH
  524. static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
  525. void *packet, int length)
  526. #else
  527. static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
  528. void *packet, int length)
  529. #endif
  530. {
  531. /* send the packet to destination */
  532. u32 to;
  533. u8 *ptxb;
  534. int entry = tpc->cur_tx % NUM_TX_DESC;
  535. u32 len = length;
  536. int ret;
  537. #ifdef DEBUG_RTL8169_TX
  538. int stime = currticks();
  539. printf ("%s\n", __FUNCTION__);
  540. printf("sending %d bytes\n", len);
  541. #endif
  542. ioaddr = dev_iobase;
  543. /* point to the current txb incase multiple tx_rings are used */
  544. ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
  545. memcpy(ptxb, (char *)packet, (int)length);
  546. while (len < ETH_ZLEN)
  547. ptxb[len++] = '\0';
  548. rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN));
  549. tpc->TxDescArray[entry].buf_Haddr = 0;
  550. #ifdef CONFIG_DM_ETH
  551. tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
  552. dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
  553. #else
  554. tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
  555. pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
  556. #endif
  557. if (entry != (NUM_TX_DESC - 1)) {
  558. tpc->TxDescArray[entry].status =
  559. cpu_to_le32((OWNbit | FSbit | LSbit) |
  560. ((len > ETH_ZLEN) ? len : ETH_ZLEN));
  561. } else {
  562. tpc->TxDescArray[entry].status =
  563. cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
  564. ((len > ETH_ZLEN) ? len : ETH_ZLEN));
  565. }
  566. rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
  567. RTL_W8(TxPoll, 0x40); /* set polling bit */
  568. tpc->cur_tx++;
  569. to = currticks() + TX_TIMEOUT;
  570. do {
  571. rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
  572. } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
  573. && (currticks() < to)); /* wait */
  574. if (currticks() >= to) {
  575. #ifdef DEBUG_RTL8169_TX
  576. puts("tx timeout/error\n");
  577. printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
  578. #endif
  579. ret = -ETIMEDOUT;
  580. } else {
  581. #ifdef DEBUG_RTL8169_TX
  582. puts("tx done\n");
  583. #endif
  584. ret = 0;
  585. }
  586. /* Delay to make net console (nc) work properly */
  587. udelay(20);
  588. return ret;
  589. }
  590. #ifdef CONFIG_DM_ETH
  591. int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
  592. {
  593. struct rtl8169_private *priv = dev_get_priv(dev);
  594. return rtl_send_common(dev, priv->iobase, packet, length);
  595. }
  596. #else
  597. static int rtl_send(struct eth_device *dev, void *packet, int length)
  598. {
  599. return rtl_send_common((pci_dev_t)(unsigned long)dev->priv,
  600. dev->iobase, packet, length);
  601. }
  602. #endif
  603. static void rtl8169_set_rx_mode(void)
  604. {
  605. u32 mc_filter[2]; /* Multicast hash filter */
  606. int rx_mode;
  607. u32 tmp = 0;
  608. #ifdef DEBUG_RTL8169
  609. printf ("%s\n", __FUNCTION__);
  610. #endif
  611. /* IFF_ALLMULTI */
  612. /* Too many to filter perfectly -- accept all multicasts. */
  613. rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
  614. mc_filter[1] = mc_filter[0] = 0xffffffff;
  615. tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
  616. rtl_chip_info[tpc->chipset].RxConfigMask);
  617. RTL_W32(RxConfig, tmp);
  618. RTL_W32(MAR0 + 0, mc_filter[0]);
  619. RTL_W32(MAR0 + 4, mc_filter[1]);
  620. }
  621. #ifdef CONFIG_DM_ETH
  622. static void rtl8169_hw_start(struct udevice *dev)
  623. #else
  624. static void rtl8169_hw_start(pci_dev_t dev)
  625. #endif
  626. {
  627. u32 i;
  628. #ifdef DEBUG_RTL8169
  629. int stime = currticks();
  630. printf ("%s\n", __FUNCTION__);
  631. #endif
  632. #if 0
  633. /* Soft reset the chip. */
  634. RTL_W8(ChipCmd, CmdReset);
  635. /* Check that the chip has finished the reset. */
  636. for (i = 1000; i > 0; i--) {
  637. if ((RTL_R8(ChipCmd) & CmdReset) == 0)
  638. break;
  639. else
  640. udelay(10);
  641. }
  642. #endif
  643. RTL_W8(Cfg9346, Cfg9346_Unlock);
  644. /* RTL-8169sb/8110sb or previous version */
  645. if (tpc->chipset <= 5)
  646. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  647. RTL_W8(EarlyTxThres, EarlyTxThld);
  648. /* For gigabit rtl8169 */
  649. RTL_W16(RxMaxSize, RxPacketMaxSize);
  650. /* Set Rx Config register */
  651. i = rtl8169_rx_config | (RTL_R32(RxConfig) &
  652. rtl_chip_info[tpc->chipset].RxConfigMask);
  653. RTL_W32(RxConfig, i);
  654. /* Set DMA burst size and Interframe Gap Time */
  655. RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
  656. (InterFrameGap << TxInterFrameGapShift));
  657. tpc->cur_rx = 0;
  658. #ifdef CONFIG_DM_ETH
  659. RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
  660. (pci_addr_t)(unsigned long)tpc->TxDescArray));
  661. #else
  662. RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
  663. (pci_addr_t)(unsigned long)tpc->TxDescArray));
  664. #endif
  665. RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
  666. #ifdef CONFIG_DM_ETH
  667. RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
  668. dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
  669. #else
  670. RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
  671. dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
  672. #endif
  673. RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
  674. /* RTL-8169sc/8110sc or later version */
  675. if (tpc->chipset > 5)
  676. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  677. RTL_W8(Cfg9346, Cfg9346_Lock);
  678. udelay(10);
  679. RTL_W32(RxMissed, 0);
  680. rtl8169_set_rx_mode();
  681. /* no early-rx interrupts */
  682. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
  683. #ifdef DEBUG_RTL8169
  684. printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
  685. #endif
  686. }
  687. #ifdef CONFIG_DM_ETH
  688. static void rtl8169_init_ring(struct udevice *dev)
  689. #else
  690. static void rtl8169_init_ring(pci_dev_t dev)
  691. #endif
  692. {
  693. int i;
  694. #ifdef DEBUG_RTL8169
  695. int stime = currticks();
  696. printf ("%s\n", __FUNCTION__);
  697. #endif
  698. tpc->cur_rx = 0;
  699. tpc->cur_tx = 0;
  700. tpc->dirty_tx = 0;
  701. memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
  702. memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
  703. for (i = 0; i < NUM_TX_DESC; i++) {
  704. tpc->Tx_skbuff[i] = &txb[i];
  705. }
  706. for (i = 0; i < NUM_RX_DESC; i++) {
  707. if (i == (NUM_RX_DESC - 1))
  708. tpc->RxDescArray[i].status =
  709. cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
  710. else
  711. tpc->RxDescArray[i].status =
  712. cpu_to_le32(OWNbit + RX_BUF_SIZE);
  713. tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
  714. #ifdef CONFIG_DM_ETH
  715. tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
  716. dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
  717. #else
  718. tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
  719. dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
  720. #endif
  721. rtl_flush_rx_desc(&tpc->RxDescArray[i]);
  722. }
  723. #ifdef DEBUG_RTL8169
  724. printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
  725. #endif
  726. }
  727. #ifdef CONFIG_DM_ETH
  728. static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr,
  729. unsigned long dev_iobase)
  730. #else
  731. static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr,
  732. unsigned long dev_iobase)
  733. #endif
  734. {
  735. int i;
  736. #ifdef DEBUG_RTL8169
  737. int stime = currticks();
  738. printf ("%s\n", __FUNCTION__);
  739. #endif
  740. ioaddr = dev_iobase;
  741. rtl8169_init_ring(dev);
  742. rtl8169_hw_start(dev);
  743. /* Construct a perfect filter frame with the mac address as first match
  744. * and broadcast for all others */
  745. for (i = 0; i < 192; i++)
  746. txb[i] = 0xFF;
  747. txb[0] = enetaddr[0];
  748. txb[1] = enetaddr[1];
  749. txb[2] = enetaddr[2];
  750. txb[3] = enetaddr[3];
  751. txb[4] = enetaddr[4];
  752. txb[5] = enetaddr[5];
  753. #ifdef DEBUG_RTL8169
  754. printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
  755. #endif
  756. }
  757. #ifdef CONFIG_DM_ETH
  758. static int rtl8169_eth_start(struct udevice *dev)
  759. {
  760. struct eth_pdata *plat = dev_get_platdata(dev);
  761. struct rtl8169_private *priv = dev_get_priv(dev);
  762. rtl8169_common_start(dev, plat->enetaddr, priv->iobase);
  763. return 0;
  764. }
  765. #else
  766. /**************************************************************************
  767. RESET - Finish setting up the ethernet interface
  768. ***************************************************************************/
  769. static int rtl_reset(struct eth_device *dev, struct bd_info *bis)
  770. {
  771. rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv,
  772. dev->enetaddr, dev->iobase);
  773. return 0;
  774. }
  775. #endif /* nCONFIG_DM_ETH */
  776. static void rtl_halt_common(unsigned long dev_iobase)
  777. {
  778. int i;
  779. #ifdef DEBUG_RTL8169
  780. printf ("%s\n", __FUNCTION__);
  781. #endif
  782. ioaddr = dev_iobase;
  783. /* Stop the chip's Tx and Rx DMA processes. */
  784. RTL_W8(ChipCmd, 0x00);
  785. /* Disable interrupts by clearing the interrupt mask. */
  786. RTL_W16(IntrMask, 0x0000);
  787. RTL_W32(RxMissed, 0);
  788. for (i = 0; i < NUM_RX_DESC; i++) {
  789. tpc->RxBufferRing[i] = NULL;
  790. }
  791. }
  792. #ifdef CONFIG_DM_ETH
  793. void rtl8169_eth_stop(struct udevice *dev)
  794. {
  795. struct rtl8169_private *priv = dev_get_priv(dev);
  796. rtl_halt_common(priv->iobase);
  797. }
  798. #else
  799. /**************************************************************************
  800. HALT - Turn off ethernet interface
  801. ***************************************************************************/
  802. static void rtl_halt(struct eth_device *dev)
  803. {
  804. rtl_halt_common(dev->iobase);
  805. }
  806. #endif
  807. #ifdef CONFIG_DM_ETH
  808. static int rtl8169_write_hwaddr(struct udevice *dev)
  809. {
  810. struct eth_pdata *plat = dev_get_platdata(dev);
  811. unsigned int i;
  812. RTL_W8(Cfg9346, Cfg9346_Unlock);
  813. for (i = 0; i < MAC_ADDR_LEN; i++)
  814. RTL_W8(MAC0 + i, plat->enetaddr[i]);
  815. RTL_W8(Cfg9346, Cfg9346_Lock);
  816. return 0;
  817. }
  818. #endif
  819. /**************************************************************************
  820. INIT - Look for an adapter, this routine's visible to the outside
  821. ***************************************************************************/
  822. #define board_found 1
  823. #define valid_link 0
  824. static int rtl_init(unsigned long dev_ioaddr, const char *name,
  825. unsigned char *enetaddr)
  826. {
  827. static int board_idx = -1;
  828. int i, rc;
  829. int option = -1, Cap10_100 = 0, Cap1000 = 0;
  830. #ifdef DEBUG_RTL8169
  831. printf ("%s\n", __FUNCTION__);
  832. #endif
  833. ioaddr = dev_ioaddr;
  834. board_idx++;
  835. /* point to private storage */
  836. tpc = &tpx;
  837. rc = rtl8169_init_board(ioaddr, name);
  838. if (rc)
  839. return rc;
  840. /* Get MAC address. FIXME: read EEPROM */
  841. for (i = 0; i < MAC_ADDR_LEN; i++)
  842. enetaddr[i] = RTL_R8(MAC0 + i);
  843. #ifdef DEBUG_RTL8169
  844. printf("chipset = %d\n", tpc->chipset);
  845. printf("MAC Address");
  846. for (i = 0; i < MAC_ADDR_LEN; i++)
  847. printf(":%02x", enetaddr[i]);
  848. putc('\n');
  849. #endif
  850. #ifdef DEBUG_RTL8169
  851. /* Print out some hardware info */
  852. printf("%s: at ioaddr 0x%lx\n", name, ioaddr);
  853. #endif
  854. /* if TBI is not endbled */
  855. if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
  856. int val = mdio_read(PHY_AUTO_NEGO_REG);
  857. option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
  858. /* Force RTL8169 in 10/100/1000 Full/Half mode. */
  859. if (option > 0) {
  860. #ifdef DEBUG_RTL8169
  861. printf("%s: Force-mode Enabled.\n", name);
  862. #endif
  863. Cap10_100 = 0, Cap1000 = 0;
  864. switch (option) {
  865. case _10_Half:
  866. Cap10_100 = PHY_Cap_10_Half;
  867. Cap1000 = PHY_Cap_Null;
  868. break;
  869. case _10_Full:
  870. Cap10_100 = PHY_Cap_10_Full;
  871. Cap1000 = PHY_Cap_Null;
  872. break;
  873. case _100_Half:
  874. Cap10_100 = PHY_Cap_100_Half;
  875. Cap1000 = PHY_Cap_Null;
  876. break;
  877. case _100_Full:
  878. Cap10_100 = PHY_Cap_100_Full;
  879. Cap1000 = PHY_Cap_Null;
  880. break;
  881. case _1000_Full:
  882. Cap10_100 = PHY_Cap_Null;
  883. Cap1000 = PHY_Cap_1000_Full;
  884. break;
  885. default:
  886. break;
  887. }
  888. mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
  889. mdio_write(PHY_1000_CTRL_REG, Cap1000);
  890. } else {
  891. #ifdef DEBUG_RTL8169
  892. printf("%s: Auto-negotiation Enabled.\n",
  893. name);
  894. #endif
  895. /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
  896. mdio_write(PHY_AUTO_NEGO_REG,
  897. PHY_Cap_10_Half | PHY_Cap_10_Full |
  898. PHY_Cap_100_Half | PHY_Cap_100_Full |
  899. (val & 0x1F));
  900. /* enable 1000 Full Mode */
  901. mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
  902. }
  903. /* Enable auto-negotiation and restart auto-nigotiation */
  904. mdio_write(PHY_CTRL_REG,
  905. PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
  906. udelay(100);
  907. /* wait for auto-negotiation process */
  908. for (i = 10000; i > 0; i--) {
  909. /* check if auto-negotiation complete */
  910. if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
  911. udelay(100);
  912. option = RTL_R8(PHYstatus);
  913. if (option & _1000bpsF) {
  914. #ifdef DEBUG_RTL8169
  915. printf("%s: 1000Mbps Full-duplex operation.\n",
  916. name);
  917. #endif
  918. } else {
  919. #ifdef DEBUG_RTL8169
  920. printf("%s: %sMbps %s-duplex operation.\n",
  921. name,
  922. (option & _100bps) ? "100" :
  923. "10",
  924. (option & FullDup) ? "Full" :
  925. "Half");
  926. #endif
  927. }
  928. break;
  929. } else {
  930. udelay(100);
  931. }
  932. } /* end for-loop to wait for auto-negotiation process */
  933. } else {
  934. udelay(100);
  935. #ifdef DEBUG_RTL8169
  936. printf
  937. ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
  938. name,
  939. (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
  940. #endif
  941. }
  942. tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
  943. if (!tpc->RxDescArray)
  944. return -ENOMEM;
  945. tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
  946. if (!tpc->TxDescArray)
  947. return -ENOMEM;
  948. return 0;
  949. }
  950. #ifndef CONFIG_DM_ETH
  951. int rtl8169_initialize(struct bd_info *bis)
  952. {
  953. pci_dev_t devno;
  954. int card_number = 0;
  955. struct eth_device *dev;
  956. u32 iobase;
  957. int idx=0;
  958. while(1){
  959. unsigned int region;
  960. u16 device;
  961. int err;
  962. /* Find RTL8169 */
  963. if ((devno = pci_find_devices(supported, idx++)) < 0)
  964. break;
  965. pci_read_config_word(devno, PCI_DEVICE_ID, &device);
  966. switch (device) {
  967. case 0x8168:
  968. region = 2;
  969. break;
  970. default:
  971. region = 1;
  972. break;
  973. }
  974. pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
  975. iobase &= ~0xf;
  976. debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
  977. dev = (struct eth_device *)malloc(sizeof *dev);
  978. if (!dev) {
  979. printf("Can not allocate memory of rtl8169\n");
  980. break;
  981. }
  982. memset(dev, 0, sizeof(*dev));
  983. sprintf (dev->name, "RTL8169#%d", card_number);
  984. dev->priv = (void *)(unsigned long)devno;
  985. dev->iobase = (int)pci_mem_to_phys(devno, iobase);
  986. dev->init = rtl_reset;
  987. dev->halt = rtl_halt;
  988. dev->send = rtl_send;
  989. dev->recv = rtl_recv;
  990. err = rtl_init(dev->iobase, dev->name, dev->enetaddr);
  991. if (err < 0) {
  992. printf(pr_fmt("failed to initialize card: %d\n"), err);
  993. free(dev);
  994. continue;
  995. }
  996. eth_register (dev);
  997. card_number++;
  998. }
  999. return card_number;
  1000. }
  1001. #endif
  1002. #ifdef CONFIG_DM_ETH
  1003. static int rtl8169_eth_probe(struct udevice *dev)
  1004. {
  1005. struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  1006. struct rtl8169_private *priv = dev_get_priv(dev);
  1007. struct eth_pdata *plat = dev_get_platdata(dev);
  1008. u32 iobase;
  1009. int region;
  1010. int ret;
  1011. debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
  1012. switch (pplat->device) {
  1013. case 0x8168:
  1014. region = 2;
  1015. break;
  1016. default:
  1017. region = 1;
  1018. break;
  1019. }
  1020. dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase);
  1021. iobase &= ~0xf;
  1022. priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase);
  1023. ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
  1024. if (ret < 0) {
  1025. printf(pr_fmt("failed to initialize card: %d\n"), ret);
  1026. return ret;
  1027. }
  1028. /*
  1029. * WAR for DHCP failure after rebooting from kernel.
  1030. * Clear RxDv_Gated_En bit which was set by kernel driver.
  1031. * Without this, U-Boot can't get an IP via DHCP.
  1032. * Register (FuncEvent, aka MISC) and RXDV_GATED_EN bit are from
  1033. * the r8169.c kernel driver.
  1034. */
  1035. u32 val = RTL_R32(FuncEvent);
  1036. debug("%s: FuncEvent/Misc (0xF0) = 0x%08X\n", __func__, val);
  1037. val &= ~RxDv_Gated_En;
  1038. RTL_W32(FuncEvent, val);
  1039. return 0;
  1040. }
  1041. static const struct eth_ops rtl8169_eth_ops = {
  1042. .start = rtl8169_eth_start,
  1043. .send = rtl8169_eth_send,
  1044. .recv = rtl8169_eth_recv,
  1045. .stop = rtl8169_eth_stop,
  1046. .write_hwaddr = rtl8169_write_hwaddr,
  1047. };
  1048. static const struct udevice_id rtl8169_eth_ids[] = {
  1049. { .compatible = "realtek,rtl8169" },
  1050. { }
  1051. };
  1052. U_BOOT_DRIVER(eth_rtl8169) = {
  1053. .name = "eth_rtl8169",
  1054. .id = UCLASS_ETH,
  1055. .of_match = rtl8169_eth_ids,
  1056. .probe = rtl8169_eth_probe,
  1057. .ops = &rtl8169_eth_ops,
  1058. .priv_auto_alloc_size = sizeof(struct rtl8169_private),
  1059. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1060. };
  1061. U_BOOT_PCI_DEVICE(eth_rtl8169, supported);
  1062. #endif