rtl8139.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * rtl8139.c : U-Boot driver for the RealTek RTL8139
  4. *
  5. * Masami Komiya (mkomiya@sonare.it)
  6. *
  7. * Most part is taken from rtl8139.c of etherboot
  8. *
  9. */
  10. /* rtl8139.c - etherboot driver for the Realtek 8139 chipset
  11. *
  12. * ported from the linux driver written by Donald Becker
  13. * by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
  14. *
  15. * changes to the original driver:
  16. * - removed support for interrupts, switching to polling mode (yuck!)
  17. * - removed support for the 8129 chip (external MII)
  18. */
  19. /*********************************************************************/
  20. /* Revision History */
  21. /*********************************************************************/
  22. /*
  23. * 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
  24. * Put in virt_to_bus calls to allow Etherboot relocation.
  25. *
  26. * 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
  27. * Following email from Hyun-Joon Cha, added a disable routine, otherwise
  28. * NIC remains live and can crash the kernel later.
  29. *
  30. * 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
  31. * Shuffled things around, removed the leftovers from the 8129 support
  32. * that was in the Linux driver and added a bit more 8139 definitions.
  33. * Moved the 8K receive buffer to a fixed, available address outside the
  34. * 0x98000-0x9ffff range. This is a bit of a hack, but currently the only
  35. * way to make room for the Etherboot features that need substantial amounts
  36. * of code like the ANSI console support. Currently the buffer is just below
  37. * 0x10000, so this even conforms to the tagged boot image specification,
  38. * which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
  39. * interpretation of this "reserved" is that Etherboot may do whatever it
  40. * likes, as long as its environment is kept intact (like the BIOS
  41. * variables). Hopefully fixed rtl8139_recv() once and for all. The symptoms
  42. * were that if Etherboot was left at the boot menu for several minutes, the
  43. * first eth_poll failed. Seems like I am the only person who does this.
  44. * First of all I fixed the debugging code and then set out for a long bug
  45. * hunting session. It took me about a week full time work - poking around
  46. * various places in the driver, reading Don Becker's and Jeff Garzik's Linux
  47. * driver and even the FreeBSD driver (what a piece of crap!) - and
  48. * eventually spotted the nasty thing: the transmit routine was acknowledging
  49. * each and every interrupt pending, including the RxOverrun and RxFIFIOver
  50. * interrupts. This confused the RTL8139 thoroughly. It destroyed the
  51. * Rx ring contents by dumping the 2K FIFO contents right where we wanted to
  52. * get the next packet. Oh well, what fun.
  53. *
  54. * 18 Jan 2000 mdc@thinguin.org (Marty Connor)
  55. * Drastically simplified error handling. Basically, if any error
  56. * in transmission or reception occurs, the card is reset.
  57. * Also, pointed all transmit descriptors to the same buffer to
  58. * save buffer space. This should decrease driver size and avoid
  59. * corruption because of exceeding 32K during runtime.
  60. *
  61. * 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
  62. * rtl8139_recv was quite broken: it used the RxOK interrupt flag instead
  63. * of the RxBufferEmpty flag which often resulted in very bad
  64. * transmission performace - below 1kBytes/s.
  65. *
  66. */
  67. #include <common.h>
  68. #include <cpu_func.h>
  69. #include <dm.h>
  70. #include <log.h>
  71. #include <malloc.h>
  72. #include <net.h>
  73. #include <netdev.h>
  74. #include <asm/io.h>
  75. #include <pci.h>
  76. #include <linux/bitops.h>
  77. #include <linux/delay.h>
  78. #include <linux/types.h>
  79. #define RTL_TIMEOUT 100000
  80. /* PCI Tuning Parameters */
  81. /* Threshold is bytes transferred to chip before transmission starts. */
  82. #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
  83. #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
  84. #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
  85. #define TX_DMA_BURST 4 /* Calculate as 16<<val. */
  86. #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
  87. #define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
  88. #define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
  89. #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
  90. #define DEBUG_TX 0 /* set to 1 to enable debug code */
  91. #define DEBUG_RX 0 /* set to 1 to enable debug code */
  92. #ifdef CONFIG_DM_ETH
  93. #define bus_to_phys(devno, a) dm_pci_mem_to_phys((devno), (a))
  94. #define phys_to_bus(devno, a) dm_pci_phys_to_mem((devno), (a))
  95. #else
  96. #define bus_to_phys(devno, a) pci_mem_to_phys((pci_dev_t)(devno), (a))
  97. #define phys_to_bus(devno, a) pci_phys_to_mem((pci_dev_t)(devno), (a))
  98. #endif
  99. /* Symbolic offsets to registers. */
  100. /* Ethernet hardware address. */
  101. #define RTL_REG_MAC0 0x00
  102. /* Multicast filter. */
  103. #define RTL_REG_MAR0 0x08
  104. /* Transmit status (four 32bit registers). */
  105. #define RTL_REG_TXSTATUS0 0x10
  106. /* Tx descriptors (also four 32bit). */
  107. #define RTL_REG_TXADDR0 0x20
  108. #define RTL_REG_RXBUF 0x30
  109. #define RTL_REG_RXEARLYCNT 0x34
  110. #define RTL_REG_RXEARLYSTATUS 0x36
  111. #define RTL_REG_CHIPCMD 0x37
  112. #define RTL_REG_CHIPCMD_CMDRESET BIT(4)
  113. #define RTL_REG_CHIPCMD_CMDRXENB BIT(3)
  114. #define RTL_REG_CHIPCMD_CMDTXENB BIT(2)
  115. #define RTL_REG_CHIPCMD_RXBUFEMPTY BIT(0)
  116. #define RTL_REG_RXBUFPTR 0x38
  117. #define RTL_REG_RXBUFADDR 0x3A
  118. #define RTL_REG_INTRMASK 0x3C
  119. #define RTL_REG_INTRSTATUS 0x3E
  120. #define RTL_REG_INTRSTATUS_PCIERR BIT(15)
  121. #define RTL_REG_INTRSTATUS_PCSTIMEOUT BIT(14)
  122. #define RTL_REG_INTRSTATUS_CABLELENCHANGE BIT(13)
  123. #define RTL_REG_INTRSTATUS_RXFIFOOVER BIT(6)
  124. #define RTL_REG_INTRSTATUS_RXUNDERRUN BIT(5)
  125. #define RTL_REG_INTRSTATUS_RXOVERFLOW BIT(4)
  126. #define RTL_REG_INTRSTATUS_TXERR BIT(3)
  127. #define RTL_REG_INTRSTATUS_TXOK BIT(2)
  128. #define RTL_REG_INTRSTATUS_RXERR BIT(1)
  129. #define RTL_REG_INTRSTATUS_RXOK BIT(0)
  130. #define RTL_REG_TXCONFIG 0x40
  131. #define RTL_REG_RXCONFIG 0x44
  132. #define RTL_REG_RXCONFIG_RXCFGWRAP BIT(7)
  133. #define RTL_REG_RXCONFIG_ACCEPTERR BIT(5)
  134. #define RTL_REG_RXCONFIG_ACCEPTRUNT BIT(4)
  135. #define RTL_REG_RXCONFIG_ACCEPTBROADCAST BIT(3)
  136. #define RTL_REG_RXCONFIG_ACCEPTMULTICAST BIT(2)
  137. #define RTL_REG_RXCONFIG_ACCEPTMYPHYS BIT(1)
  138. #define RTL_REG_RXCONFIG_ACCEPTALLPHYS BIT(0)
  139. /* general-purpose counter. */
  140. #define RTL_REG_TIMER 0x48
  141. /* 24 bits valid, write clears. */
  142. #define RTL_REG_RXMISSED 0x4C
  143. #define RTL_REG_CFG9346 0x50
  144. #define RTL_REG_CONFIG0 0x51
  145. #define RTL_REG_CONFIG1 0x52
  146. /* intr if gp counter reaches this value */
  147. #define RTL_REG_TIMERINTRREG 0x54
  148. #define RTL_REG_MEDIASTATUS 0x58
  149. #define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE BIT(7)
  150. #define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE BIT(6)
  151. #define RTL_REG_MEDIASTATUS_MSRSPEED10 BIT(3)
  152. #define RTL_REG_MEDIASTATUS_MSRLINKFAIL BIT(2)
  153. #define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG BIT(1)
  154. #define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG BIT(0)
  155. #define RTL_REG_CONFIG3 0x59
  156. #define RTL_REG_MULTIINTR 0x5C
  157. /* revision of the RTL8139 chip */
  158. #define RTL_REG_REVISIONID 0x5E
  159. #define RTL_REG_TXSUMMARY 0x60
  160. #define RTL_REG_MII_BMCR 0x62
  161. #define RTL_REG_MII_BMSR 0x64
  162. #define RTL_REG_NWAYADVERT 0x66
  163. #define RTL_REG_NWAYLPAR 0x68
  164. #define RTL_REG_NWAYEXPANSION 0x6A
  165. #define RTL_REG_DISCONNECTCNT 0x6C
  166. #define RTL_REG_FALSECARRIERCNT 0x6E
  167. #define RTL_REG_NWAYTESTREG 0x70
  168. /* packet received counter */
  169. #define RTL_REG_RXCNT 0x72
  170. /* chip status and configuration register */
  171. #define RTL_REG_CSCR 0x74
  172. #define RTL_REG_PHYPARM1 0x78
  173. #define RTL_REG_TWISTERPARM 0x7c
  174. /* undocumented */
  175. #define RTL_REG_PHYPARM2 0x80
  176. /*
  177. * from 0x84 onwards are a number of power management/wakeup frame
  178. * definitions we will probably never need to know about.
  179. */
  180. #define RTL_STS_RXMULTICAST BIT(15)
  181. #define RTL_STS_RXPHYSICAL BIT(14)
  182. #define RTL_STS_RXBROADCAST BIT(13)
  183. #define RTL_STS_RXBADSYMBOL BIT(5)
  184. #define RTL_STS_RXRUNT BIT(4)
  185. #define RTL_STS_RXTOOLONG BIT(3)
  186. #define RTL_STS_RXCRCERR BIT(2)
  187. #define RTL_STS_RXBADALIGN BIT(1)
  188. #define RTL_STS_RXSTATUSOK BIT(0)
  189. struct rtl8139_priv {
  190. #ifndef CONFIG_DM_ETH
  191. struct eth_device dev;
  192. pci_dev_t devno;
  193. #else
  194. struct udevice *devno;
  195. #endif
  196. unsigned int rxstatus;
  197. unsigned int cur_rx;
  198. unsigned int cur_tx;
  199. unsigned long ioaddr;
  200. unsigned char enetaddr[6];
  201. };
  202. /* The RTL8139 can only transmit from a contiguous, aligned memory block. */
  203. static unsigned char tx_buffer[TX_BUF_SIZE] __aligned(4);
  204. static unsigned char rx_ring[RX_BUF_LEN + 16] __aligned(4);
  205. /* Serial EEPROM section. */
  206. /* EEPROM_Ctrl bits. */
  207. #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
  208. #define EE_CS 0x08 /* EEPROM chip select. */
  209. #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
  210. #define EE_WRITE_0 0x00
  211. #define EE_WRITE_1 0x02
  212. #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
  213. #define EE_ENB (0x80 | EE_CS)
  214. /* The EEPROM commands include the alway-set leading bit. */
  215. #define EE_WRITE_CMD 5
  216. #define EE_READ_CMD 6
  217. #define EE_ERASE_CMD 7
  218. static void rtl8139_eeprom_delay(struct rtl8139_priv *priv)
  219. {
  220. /*
  221. * Delay between EEPROM clock transitions.
  222. * No extra delay is needed with 33MHz PCI, but 66MHz may change this.
  223. */
  224. inl(priv->ioaddr + RTL_REG_CFG9346);
  225. }
  226. static int rtl8139_read_eeprom(struct rtl8139_priv *priv,
  227. unsigned int location, unsigned int addr_len)
  228. {
  229. unsigned int read_cmd = location | (EE_READ_CMD << addr_len);
  230. uintptr_t ee_addr = priv->ioaddr + RTL_REG_CFG9346;
  231. unsigned int retval = 0;
  232. u8 dataval;
  233. int i;
  234. outb(EE_ENB & ~EE_CS, ee_addr);
  235. outb(EE_ENB, ee_addr);
  236. rtl8139_eeprom_delay(priv);
  237. /* Shift the read command bits out. */
  238. for (i = 4 + addr_len; i >= 0; i--) {
  239. dataval = (read_cmd & BIT(i)) ? EE_DATA_WRITE : 0;
  240. outb(EE_ENB | dataval, ee_addr);
  241. rtl8139_eeprom_delay(priv);
  242. outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
  243. rtl8139_eeprom_delay(priv);
  244. }
  245. outb(EE_ENB, ee_addr);
  246. rtl8139_eeprom_delay(priv);
  247. for (i = 16; i > 0; i--) {
  248. outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
  249. rtl8139_eeprom_delay(priv);
  250. retval <<= 1;
  251. retval |= inb(ee_addr) & EE_DATA_READ;
  252. outb(EE_ENB, ee_addr);
  253. rtl8139_eeprom_delay(priv);
  254. }
  255. /* Terminate the EEPROM access. */
  256. outb(~EE_CS, ee_addr);
  257. rtl8139_eeprom_delay(priv);
  258. return retval;
  259. }
  260. static const unsigned int rtl8139_rx_config =
  261. (RX_BUF_LEN_IDX << 11) |
  262. (RX_FIFO_THRESH << 13) |
  263. (RX_DMA_BURST << 8);
  264. static void rtl8139_set_rx_mode(struct rtl8139_priv *priv)
  265. {
  266. /* !IFF_PROMISC */
  267. unsigned int rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST |
  268. RTL_REG_RXCONFIG_ACCEPTMULTICAST |
  269. RTL_REG_RXCONFIG_ACCEPTMYPHYS;
  270. outl(rtl8139_rx_config | rx_mode, priv->ioaddr + RTL_REG_RXCONFIG);
  271. outl(0xffffffff, priv->ioaddr + RTL_REG_MAR0 + 0);
  272. outl(0xffffffff, priv->ioaddr + RTL_REG_MAR0 + 4);
  273. }
  274. static void rtl8139_hw_reset(struct rtl8139_priv *priv)
  275. {
  276. u8 reg;
  277. int i;
  278. outb(RTL_REG_CHIPCMD_CMDRESET, priv->ioaddr + RTL_REG_CHIPCMD);
  279. /* Give the chip 10ms to finish the reset. */
  280. for (i = 0; i < 100; i++) {
  281. reg = inb(priv->ioaddr + RTL_REG_CHIPCMD);
  282. if (!(reg & RTL_REG_CHIPCMD_CMDRESET))
  283. break;
  284. udelay(100);
  285. }
  286. }
  287. static void rtl8139_reset(struct rtl8139_priv *priv)
  288. {
  289. int i;
  290. priv->cur_rx = 0;
  291. priv->cur_tx = 0;
  292. rtl8139_hw_reset(priv);
  293. for (i = 0; i < ETH_ALEN; i++)
  294. outb(priv->enetaddr[i], priv->ioaddr + RTL_REG_MAC0 + i);
  295. /* Must enable Tx/Rx before setting transfer thresholds! */
  296. outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
  297. priv->ioaddr + RTL_REG_CHIPCMD);
  298. /* accept no frames yet! */
  299. outl(rtl8139_rx_config, priv->ioaddr + RTL_REG_RXCONFIG);
  300. outl((TX_DMA_BURST << 8) | 0x03000000, priv->ioaddr + RTL_REG_TXCONFIG);
  301. /*
  302. * The Linux driver changes RTL_REG_CONFIG1 here to use a different
  303. * LED pattern for half duplex or full/autodetect duplex (for
  304. * full/autodetect, the outputs are TX/RX, Link10/100, FULL, while
  305. * for half duplex it uses TX/RX, Link100, Link10). This is messy,
  306. * because it doesn't match the inscription on the mounting bracket.
  307. * It should not be changed from the configuration EEPROM default,
  308. * because the card manufacturer should have set that to match the
  309. * card.
  310. */
  311. debug_cond(DEBUG_RX, "rx ring address is %p\n", rx_ring);
  312. flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
  313. outl(phys_to_bus(priv->devno, (int)rx_ring), priv->ioaddr + RTL_REG_RXBUF);
  314. /*
  315. * If we add multicast support, the RTL_REG_MAR0 register would have
  316. * to be initialized to 0xffffffffffffffff (two 32 bit accesses).
  317. * Etherboot only needs broadcast (for ARP/RARP/BOOTP/DHCP) and
  318. * unicast.
  319. */
  320. outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
  321. priv->ioaddr + RTL_REG_CHIPCMD);
  322. outl(rtl8139_rx_config, priv->ioaddr + RTL_REG_RXCONFIG);
  323. /* Start the chip's Tx and Rx process. */
  324. outl(0, priv->ioaddr + RTL_REG_RXMISSED);
  325. rtl8139_set_rx_mode(priv);
  326. /* Disable all known interrupts by setting the interrupt mask. */
  327. outw(0, priv->ioaddr + RTL_REG_INTRMASK);
  328. }
  329. static int rtl8139_send_common(struct rtl8139_priv *priv,
  330. void *packet, int length)
  331. {
  332. unsigned int len = length;
  333. unsigned long txstatus;
  334. unsigned int status;
  335. int i = 0;
  336. memcpy(tx_buffer, packet, length);
  337. debug_cond(DEBUG_TX, "sending %d bytes\n", len);
  338. /*
  339. * Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
  340. * bytes are sent automatically for the FCS, totalling to 64 bytes).
  341. */
  342. while (len < ETH_ZLEN)
  343. tx_buffer[len++] = '\0';
  344. flush_cache((unsigned long)tx_buffer, length);
  345. outl(phys_to_bus(priv->devno, (unsigned long)tx_buffer),
  346. priv->ioaddr + RTL_REG_TXADDR0 + priv->cur_tx * 4);
  347. outl(((TX_FIFO_THRESH << 11) & 0x003f0000) | len,
  348. priv->ioaddr + RTL_REG_TXSTATUS0 + priv->cur_tx * 4);
  349. do {
  350. status = inw(priv->ioaddr + RTL_REG_INTRSTATUS);
  351. /*
  352. * Only acknlowledge interrupt sources we can properly
  353. * handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/
  354. * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the
  355. * rtl8139_recv() function.
  356. */
  357. status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR |
  358. RTL_REG_INTRSTATUS_PCIERR;
  359. outw(status, priv->ioaddr + RTL_REG_INTRSTATUS);
  360. if (status)
  361. break;
  362. udelay(10);
  363. } while (i++ < RTL_TIMEOUT);
  364. txstatus = inl(priv->ioaddr + RTL_REG_TXSTATUS0 + priv->cur_tx * 4);
  365. if (!(status & RTL_REG_INTRSTATUS_TXOK)) {
  366. debug_cond(DEBUG_TX,
  367. "tx timeout/error (%d usecs), status %hX txstatus %lX\n",
  368. 10 * i, status, txstatus);
  369. rtl8139_reset(priv);
  370. return 0;
  371. }
  372. priv->cur_tx = (priv->cur_tx + 1) % NUM_TX_DESC;
  373. debug_cond(DEBUG_TX, "tx done, status %hX txstatus %lX\n",
  374. status, txstatus);
  375. return length;
  376. }
  377. static int rtl8139_recv_common(struct rtl8139_priv *priv, unsigned char *rxdata,
  378. uchar **packetp)
  379. {
  380. const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
  381. RTL_REG_INTRSTATUS_RXOVERFLOW |
  382. RTL_REG_INTRSTATUS_RXOK;
  383. unsigned int rx_size, rx_status;
  384. unsigned int ring_offs;
  385. int length = 0;
  386. if (inb(priv->ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
  387. return 0;
  388. priv->rxstatus = inw(priv->ioaddr + RTL_REG_INTRSTATUS);
  389. /* See below for the rest of the interrupt acknowledges. */
  390. outw(priv->rxstatus & ~rxstat, priv->ioaddr + RTL_REG_INTRSTATUS);
  391. debug_cond(DEBUG_RX, "%s: int %hX ", __func__, priv->rxstatus);
  392. ring_offs = priv->cur_rx % RX_BUF_LEN;
  393. /* ring_offs is guaranteed being 4-byte aligned */
  394. rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
  395. rx_size = rx_status >> 16;
  396. rx_status &= 0xffff;
  397. if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT |
  398. RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR |
  399. RTL_STS_RXBADALIGN)) ||
  400. (rx_size < ETH_ZLEN) ||
  401. (rx_size > ETH_FRAME_LEN + 4)) {
  402. printf("rx error %hX\n", rx_status);
  403. /* this clears all interrupts still pending */
  404. rtl8139_reset(priv);
  405. return 0;
  406. }
  407. /* Received a good packet */
  408. length = rx_size - 4; /* no one cares about the FCS */
  409. if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN) {
  410. int semi_count = RX_BUF_LEN - ring_offs - 4;
  411. memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
  412. memcpy(&rxdata[semi_count], rx_ring,
  413. rx_size - 4 - semi_count);
  414. *packetp = rxdata;
  415. debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
  416. semi_count, rx_size - 4 - semi_count);
  417. } else {
  418. *packetp = rx_ring + ring_offs + 4;
  419. debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size - 4);
  420. }
  421. return length;
  422. }
  423. static int rtl8139_free_pkt_common(struct rtl8139_priv *priv, unsigned int len)
  424. {
  425. const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
  426. RTL_REG_INTRSTATUS_RXOVERFLOW |
  427. RTL_REG_INTRSTATUS_RXOK;
  428. unsigned int rx_size = len + 4;
  429. flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
  430. priv->cur_rx = ROUND(priv->cur_rx + rx_size + 4, 4);
  431. outw(priv->cur_rx - 16, priv->ioaddr + RTL_REG_RXBUFPTR);
  432. /*
  433. * See RTL8139 Programming Guide V0.1 for the official handling of
  434. * Rx overflow situations. The document itself contains basically
  435. * no usable information, except for a few exception handling rules.
  436. */
  437. outw(priv->rxstatus & rxstat, priv->ioaddr + RTL_REG_INTRSTATUS);
  438. return 0;
  439. }
  440. static int rtl8139_init_common(struct rtl8139_priv *priv)
  441. {
  442. u8 reg;
  443. /* Bring the chip out of low-power mode. */
  444. outb(0x00, priv->ioaddr + RTL_REG_CONFIG1);
  445. rtl8139_reset(priv);
  446. reg = inb(priv->ioaddr + RTL_REG_MEDIASTATUS);
  447. if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) {
  448. printf("Cable not connected or other link failure\n");
  449. return -1;
  450. }
  451. return 0;
  452. }
  453. static void rtl8139_stop_common(struct rtl8139_priv *priv)
  454. {
  455. rtl8139_hw_reset(priv);
  456. }
  457. static void rtl8139_get_hwaddr(struct rtl8139_priv *priv)
  458. {
  459. unsigned short *ap = (unsigned short *)priv->enetaddr;
  460. int i, addr_len;
  461. /* Bring the chip out of low-power mode. */
  462. outb(0x00, priv->ioaddr + RTL_REG_CONFIG1);
  463. addr_len = rtl8139_read_eeprom(priv, 0, 8) == 0x8129 ? 8 : 6;
  464. for (i = 0; i < 3; i++)
  465. *ap++ = le16_to_cpu(rtl8139_read_eeprom(priv, i + 7, addr_len));
  466. }
  467. static void rtl8139_name(char *str, int card_number)
  468. {
  469. sprintf(str, "RTL8139#%u", card_number);
  470. }
  471. static struct pci_device_id supported[] = {
  472. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139) },
  473. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139) },
  474. { }
  475. };
  476. #ifndef CONFIG_DM_ETH
  477. static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac,
  478. int join)
  479. {
  480. return 0;
  481. }
  482. static int rtl8139_init(struct eth_device *dev, struct bd_info *bis)
  483. {
  484. struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
  485. return rtl8139_init_common(priv);
  486. }
  487. static void rtl8139_stop(struct eth_device *dev)
  488. {
  489. struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
  490. return rtl8139_stop_common(priv);
  491. }
  492. static int rtl8139_send(struct eth_device *dev, void *packet, int length)
  493. {
  494. struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
  495. return rtl8139_send_common(priv, packet, length);
  496. }
  497. static int rtl8139_recv(struct eth_device *dev)
  498. {
  499. struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
  500. unsigned char rxdata[RX_BUF_LEN];
  501. uchar *packet;
  502. int ret;
  503. ret = rtl8139_recv_common(priv, rxdata, &packet);
  504. if (ret) {
  505. net_process_received_packet(packet, ret);
  506. rtl8139_free_pkt_common(priv, ret);
  507. }
  508. return ret;
  509. }
  510. int rtl8139_initialize(struct bd_info *bis)
  511. {
  512. struct rtl8139_priv *priv;
  513. struct eth_device *dev;
  514. int card_number = 0;
  515. pci_dev_t devno;
  516. int idx = 0;
  517. u32 iobase;
  518. while (1) {
  519. /* Find RTL8139 */
  520. devno = pci_find_devices(supported, idx++);
  521. if (devno < 0)
  522. break;
  523. pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
  524. iobase &= ~0xf;
  525. debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
  526. priv = calloc(1, sizeof(*priv));
  527. if (!priv) {
  528. printf("Can not allocate memory of rtl8139\n");
  529. break;
  530. }
  531. priv->devno = devno;
  532. priv->ioaddr = (unsigned long)bus_to_phys(devno, iobase);
  533. dev = &priv->dev;
  534. rtl8139_name(dev->name, card_number);
  535. dev->iobase = priv->ioaddr; /* Non-DM compatibility */
  536. dev->init = rtl8139_init;
  537. dev->halt = rtl8139_stop;
  538. dev->send = rtl8139_send;
  539. dev->recv = rtl8139_recv;
  540. dev->mcast = rtl8139_bcast_addr;
  541. rtl8139_get_hwaddr(priv);
  542. /* Non-DM compatibility */
  543. memcpy(priv->dev.enetaddr, priv->enetaddr, 6);
  544. eth_register(dev);
  545. card_number++;
  546. pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
  547. udelay(10 * 1000);
  548. }
  549. return card_number;
  550. }
  551. #else /* DM_ETH */
  552. static int rtl8139_start(struct udevice *dev)
  553. {
  554. struct eth_pdata *plat = dev_get_platdata(dev);
  555. struct rtl8139_priv *priv = dev_get_priv(dev);
  556. memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
  557. return rtl8139_init_common(priv);
  558. }
  559. static void rtl8139_stop(struct udevice *dev)
  560. {
  561. struct rtl8139_priv *priv = dev_get_priv(dev);
  562. rtl8139_stop_common(priv);
  563. }
  564. static int rtl8139_send(struct udevice *dev, void *packet, int length)
  565. {
  566. struct rtl8139_priv *priv = dev_get_priv(dev);
  567. int ret;
  568. ret = rtl8139_send_common(priv, packet, length);
  569. return ret ? 0 : -ETIMEDOUT;
  570. }
  571. static int rtl8139_recv(struct udevice *dev, int flags, uchar **packetp)
  572. {
  573. struct rtl8139_priv *priv = dev_get_priv(dev);
  574. static unsigned char rxdata[RX_BUF_LEN];
  575. return rtl8139_recv_common(priv, rxdata, packetp);
  576. }
  577. static int rtl8139_free_pkt(struct udevice *dev, uchar *packet, int length)
  578. {
  579. struct rtl8139_priv *priv = dev_get_priv(dev);
  580. rtl8139_free_pkt_common(priv, length);
  581. return 0;
  582. }
  583. static int rtl8139_write_hwaddr(struct udevice *dev)
  584. {
  585. struct eth_pdata *plat = dev_get_platdata(dev);
  586. struct rtl8139_priv *priv = dev_get_priv(dev);
  587. memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
  588. rtl8139_reset(priv);
  589. return 0;
  590. }
  591. static int rtl8139_read_rom_hwaddr(struct udevice *dev)
  592. {
  593. struct rtl8139_priv *priv = dev_get_priv(dev);
  594. rtl8139_get_hwaddr(priv);
  595. return 0;
  596. }
  597. static int rtl8139_bind(struct udevice *dev)
  598. {
  599. static int card_number;
  600. char name[16];
  601. rtl8139_name(name, card_number++);
  602. return device_set_name(dev, name);
  603. }
  604. static int rtl8139_probe(struct udevice *dev)
  605. {
  606. struct eth_pdata *plat = dev_get_platdata(dev);
  607. struct rtl8139_priv *priv = dev_get_priv(dev);
  608. u32 iobase;
  609. dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
  610. iobase &= ~0xf;
  611. debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
  612. priv->devno = dev;
  613. priv->ioaddr = (unsigned long)bus_to_phys(dev, iobase);
  614. rtl8139_get_hwaddr(priv);
  615. memcpy(plat->enetaddr, priv->enetaddr, sizeof(priv->enetaddr));
  616. dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
  617. return 0;
  618. }
  619. static const struct eth_ops rtl8139_ops = {
  620. .start = rtl8139_start,
  621. .send = rtl8139_send,
  622. .recv = rtl8139_recv,
  623. .stop = rtl8139_stop,
  624. .free_pkt = rtl8139_free_pkt,
  625. .write_hwaddr = rtl8139_write_hwaddr,
  626. .read_rom_hwaddr = rtl8139_read_rom_hwaddr,
  627. };
  628. U_BOOT_DRIVER(eth_rtl8139) = {
  629. .name = "eth_rtl8139",
  630. .id = UCLASS_ETH,
  631. .bind = rtl8139_bind,
  632. .probe = rtl8139_probe,
  633. .ops = &rtl8139_ops,
  634. .priv_auto_alloc_size = sizeof(struct rtl8139_priv),
  635. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  636. };
  637. U_BOOT_PCI_DEVICE(eth_rtl8139, supported);
  638. #endif