pic32_eth.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <errno.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <net.h>
  13. #include <miiphy.h>
  14. #include <console.h>
  15. #include <time.h>
  16. #include <wait_bit.h>
  17. #include <asm/gpio.h>
  18. #include <linux/delay.h>
  19. #include <linux/mii.h>
  20. #include "pic32_eth.h"
  21. #define MAX_RX_BUF_SIZE 1536
  22. #define MAX_RX_DESCR PKTBUFSRX
  23. #define MAX_TX_DESCR 2
  24. DECLARE_GLOBAL_DATA_PTR;
  25. struct pic32eth_dev {
  26. struct eth_dma_desc rxd_ring[MAX_RX_DESCR];
  27. struct eth_dma_desc txd_ring[MAX_TX_DESCR];
  28. u32 rxd_idx; /* index of RX desc to read */
  29. /* regs */
  30. struct pic32_ectl_regs *ectl_regs;
  31. struct pic32_emac_regs *emac_regs;
  32. /* Phy */
  33. struct phy_device *phydev;
  34. phy_interface_t phyif;
  35. u32 phy_addr;
  36. struct gpio_desc rst_gpio;
  37. };
  38. void __weak board_netphy_reset(void *dev)
  39. {
  40. struct pic32eth_dev *priv = dev;
  41. if (!dm_gpio_is_valid(&priv->rst_gpio))
  42. return;
  43. /* phy reset */
  44. dm_gpio_set_value(&priv->rst_gpio, 0);
  45. udelay(300);
  46. dm_gpio_set_value(&priv->rst_gpio, 1);
  47. udelay(300);
  48. }
  49. /* Initialize mii(MDIO) interface, discover which PHY is
  50. * attached to the device, and configure it properly.
  51. */
  52. static int pic32_mii_init(struct pic32eth_dev *priv)
  53. {
  54. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  55. struct pic32_emac_regs *emac_p = priv->emac_regs;
  56. /* board phy reset */
  57. board_netphy_reset(priv);
  58. /* disable RX, TX & all transactions */
  59. writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
  60. /* wait till busy */
  61. wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
  62. CONFIG_SYS_HZ, false);
  63. /* turn controller ON to access PHY over MII */
  64. writel(ETHCON_ON, &ectl_p->con1.set);
  65. mdelay(10);
  66. /* reset MAC */
  67. writel(EMAC_SOFTRESET, &emac_p->cfg1.set); /* reset assert */
  68. mdelay(10);
  69. writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */
  70. /* initialize MDIO/MII */
  71. if (priv->phyif == PHY_INTERFACE_MODE_RMII) {
  72. writel(EMAC_RMII_RESET, &emac_p->supp.set);
  73. mdelay(10);
  74. writel(EMAC_RMII_RESET, &emac_p->supp.clr);
  75. }
  76. return pic32_mdio_init(PIC32_MDIO_NAME, (ulong)&emac_p->mii);
  77. }
  78. static int pic32_phy_init(struct pic32eth_dev *priv, struct udevice *dev)
  79. {
  80. struct mii_dev *mii;
  81. mii = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
  82. /* find & connect PHY */
  83. priv->phydev = phy_connect(mii, priv->phy_addr,
  84. dev, priv->phyif);
  85. if (!priv->phydev) {
  86. printf("%s: %s: Error, PHY connect\n", __FILE__, __func__);
  87. return 0;
  88. }
  89. /* Wait for phy to complete reset */
  90. mdelay(10);
  91. /* configure supported modes */
  92. priv->phydev->supported = SUPPORTED_10baseT_Half |
  93. SUPPORTED_10baseT_Full |
  94. SUPPORTED_100baseT_Half |
  95. SUPPORTED_100baseT_Full |
  96. SUPPORTED_Autoneg;
  97. priv->phydev->advertising = ADVERTISED_10baseT_Half |
  98. ADVERTISED_10baseT_Full |
  99. ADVERTISED_100baseT_Half |
  100. ADVERTISED_100baseT_Full |
  101. ADVERTISED_Autoneg;
  102. priv->phydev->autoneg = AUTONEG_ENABLE;
  103. return 0;
  104. }
  105. /* Configure MAC based on negotiated speed and duplex
  106. * reported by PHY.
  107. */
  108. static int pic32_mac_adjust_link(struct pic32eth_dev *priv)
  109. {
  110. struct phy_device *phydev = priv->phydev;
  111. struct pic32_emac_regs *emac_p = priv->emac_regs;
  112. if (!phydev->link) {
  113. printf("%s: No link.\n", phydev->dev->name);
  114. return -EINVAL;
  115. }
  116. if (phydev->duplex) {
  117. writel(EMAC_FULLDUP, &emac_p->cfg2.set);
  118. writel(FULLDUP_GAP_TIME, &emac_p->ipgt.raw);
  119. } else {
  120. writel(EMAC_FULLDUP, &emac_p->cfg2.clr);
  121. writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
  122. }
  123. switch (phydev->speed) {
  124. case SPEED_100:
  125. writel(EMAC_RMII_SPD100, &emac_p->supp.set);
  126. break;
  127. case SPEED_10:
  128. writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
  129. break;
  130. default:
  131. printf("%s: Speed was bad\n", phydev->dev->name);
  132. return -EINVAL;
  133. }
  134. printf("pic32eth: PHY is %s with %dbase%s, %s\n",
  135. phydev->drv->name, phydev->speed,
  136. (phydev->port == PORT_TP) ? "T" : "X",
  137. (phydev->duplex) ? "full" : "half");
  138. return 0;
  139. }
  140. static void pic32_mac_init(struct pic32eth_dev *priv, u8 *macaddr)
  141. {
  142. struct pic32_emac_regs *emac_p = priv->emac_regs;
  143. u32 stat = 0, v;
  144. u64 expire;
  145. v = EMAC_TXPAUSE | EMAC_RXPAUSE | EMAC_RXENABLE;
  146. writel(v, &emac_p->cfg1.raw);
  147. v = EMAC_EXCESS | EMAC_AUTOPAD | EMAC_PADENABLE |
  148. EMAC_CRCENABLE | EMAC_LENGTHCK | EMAC_FULLDUP;
  149. writel(v, &emac_p->cfg2.raw);
  150. /* recommended back-to-back inter-packet gap for 10 Mbps half duplex */
  151. writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
  152. /* recommended non-back-to-back interpacket gap is 0xc12 */
  153. writel(0xc12, &emac_p->ipgr.raw);
  154. /* recommended collision window retry limit is 0x370F */
  155. writel(0x370f, &emac_p->clrt.raw);
  156. /* set maximum frame length: allow VLAN tagged frame */
  157. writel(0x600, &emac_p->maxf.raw);
  158. /* set the mac address */
  159. writel(macaddr[0] | (macaddr[1] << 8), &emac_p->sa2.raw);
  160. writel(macaddr[2] | (macaddr[3] << 8), &emac_p->sa1.raw);
  161. writel(macaddr[4] | (macaddr[5] << 8), &emac_p->sa0.raw);
  162. /* default, enable 10 Mbps operation */
  163. writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
  164. /* wait until link status UP or deadline elapsed */
  165. expire = get_ticks() + get_tbclk() * 2;
  166. for (; get_ticks() < expire;) {
  167. stat = phy_read(priv->phydev, priv->phy_addr, MII_BMSR);
  168. if (stat & BMSR_LSTATUS)
  169. break;
  170. }
  171. if (!(stat & BMSR_LSTATUS))
  172. printf("MAC: Link is DOWN!\n");
  173. /* delay to stabilize before any tx/rx */
  174. mdelay(10);
  175. }
  176. static void pic32_mac_reset(struct pic32eth_dev *priv)
  177. {
  178. struct pic32_emac_regs *emac_p = priv->emac_regs;
  179. struct mii_dev *mii;
  180. /* Reset MAC */
  181. writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
  182. mdelay(10);
  183. /* clear reset */
  184. writel(0, &emac_p->cfg1.raw);
  185. /* Reset MII */
  186. mii = priv->phydev->bus;
  187. if (mii && mii->reset)
  188. mii->reset(mii);
  189. }
  190. /* initializes the MAC and PHY, then establishes a link */
  191. static void pic32_ctrl_reset(struct pic32eth_dev *priv)
  192. {
  193. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  194. u32 v;
  195. /* disable RX, TX & any other transactions */
  196. writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
  197. /* wait till busy */
  198. wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
  199. CONFIG_SYS_HZ, false);
  200. /* decrement received buffcnt to zero. */
  201. while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
  202. writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
  203. /* clear any existing interrupt event */
  204. writel(0xffffffff, &ectl_p->irq.clr);
  205. /* clear RX/TX start address */
  206. writel(0xffffffff, &ectl_p->txst.clr);
  207. writel(0xffffffff, &ectl_p->rxst.clr);
  208. /* clear the receive filters */
  209. writel(0x00ff, &ectl_p->rxfc.clr);
  210. /* set the receive filters
  211. * ETH_FILT_CRC_ERR_REJECT
  212. * ETH_FILT_RUNT_REJECT
  213. * ETH_FILT_UCAST_ACCEPT
  214. * ETH_FILT_MCAST_ACCEPT
  215. * ETH_FILT_BCAST_ACCEPT
  216. */
  217. v = ETHRXFC_BCEN | ETHRXFC_MCEN | ETHRXFC_UCEN |
  218. ETHRXFC_RUNTEN | ETHRXFC_CRCOKEN;
  219. writel(v, &ectl_p->rxfc.set);
  220. /* turn controller ON to access PHY over MII */
  221. writel(ETHCON_ON, &ectl_p->con1.set);
  222. }
  223. static void pic32_rx_desc_init(struct pic32eth_dev *priv)
  224. {
  225. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  226. struct eth_dma_desc *rxd;
  227. u32 idx, bufsz;
  228. priv->rxd_idx = 0;
  229. for (idx = 0; idx < MAX_RX_DESCR; idx++) {
  230. rxd = &priv->rxd_ring[idx];
  231. /* hw owned */
  232. rxd->hdr = EDH_NPV | EDH_EOWN | EDH_STICKY;
  233. /* packet buffer address */
  234. rxd->data_buff = virt_to_phys(net_rx_packets[idx]);
  235. /* link to next desc */
  236. rxd->next_ed = virt_to_phys(rxd + 1);
  237. /* reset status */
  238. rxd->stat1 = 0;
  239. rxd->stat2 = 0;
  240. /* decrement bufcnt */
  241. writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
  242. }
  243. /* link last descr to beginning of list */
  244. rxd->next_ed = virt_to_phys(&priv->rxd_ring[0]);
  245. /* flush rx ring */
  246. flush_dcache_range((ulong)priv->rxd_ring,
  247. (ulong)priv->rxd_ring + sizeof(priv->rxd_ring));
  248. /* set rx desc-ring start address */
  249. writel((ulong)virt_to_phys(&priv->rxd_ring[0]), &ectl_p->rxst.raw);
  250. /* RX Buffer size */
  251. bufsz = readl(&ectl_p->con2.raw);
  252. bufsz &= ~(ETHCON_RXBUFSZ << ETHCON_RXBUFSZ_SHFT);
  253. bufsz |= ((MAX_RX_BUF_SIZE / 16) << ETHCON_RXBUFSZ_SHFT);
  254. writel(bufsz, &ectl_p->con2.raw);
  255. /* enable the receiver in hardware which allows hardware
  256. * to DMA received pkts to the descriptor pointer address.
  257. */
  258. writel(ETHCON_RXEN, &ectl_p->con1.set);
  259. }
  260. static int pic32_eth_start(struct udevice *dev)
  261. {
  262. struct eth_pdata *pdata = dev_get_platdata(dev);
  263. struct pic32eth_dev *priv = dev_get_priv(dev);
  264. /* controller */
  265. pic32_ctrl_reset(priv);
  266. /* reset MAC */
  267. pic32_mac_reset(priv);
  268. /* configure PHY */
  269. phy_config(priv->phydev);
  270. /* initialize MAC */
  271. pic32_mac_init(priv, &pdata->enetaddr[0]);
  272. /* init RX descriptor; TX descriptors are handled in xmit */
  273. pic32_rx_desc_init(priv);
  274. /* Start up & update link status of PHY */
  275. phy_startup(priv->phydev);
  276. /* adjust mac with phy link status */
  277. return pic32_mac_adjust_link(priv);
  278. }
  279. static void pic32_eth_stop(struct udevice *dev)
  280. {
  281. struct pic32eth_dev *priv = dev_get_priv(dev);
  282. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  283. struct pic32_emac_regs *emac_p = priv->emac_regs;
  284. /* Reset the phy if the controller is enabled */
  285. if (readl(&ectl_p->con1.raw) & ETHCON_ON)
  286. phy_reset(priv->phydev);
  287. /* Shut down the PHY */
  288. phy_shutdown(priv->phydev);
  289. /* Stop rx/tx */
  290. writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
  291. mdelay(10);
  292. /* reset MAC */
  293. writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
  294. /* clear reset */
  295. writel(0, &emac_p->cfg1.raw);
  296. mdelay(10);
  297. /* disable controller */
  298. writel(ETHCON_ON, &ectl_p->con1.clr);
  299. mdelay(10);
  300. /* wait until everything is down */
  301. wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
  302. 2 * CONFIG_SYS_HZ, false);
  303. /* clear any existing interrupt event */
  304. writel(0xffffffff, &ectl_p->irq.clr);
  305. }
  306. static int pic32_eth_send(struct udevice *dev, void *packet, int length)
  307. {
  308. struct pic32eth_dev *priv = dev_get_priv(dev);
  309. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  310. struct eth_dma_desc *txd;
  311. u64 deadline;
  312. txd = &priv->txd_ring[0];
  313. /* set proper flags & length in descriptor header */
  314. txd->hdr = EDH_SOP | EDH_EOP | EDH_EOWN | EDH_BCOUNT(length);
  315. /* pass buffer address to hardware */
  316. txd->data_buff = virt_to_phys(packet);
  317. debug("%s: %d / .hdr %x, .data_buff %x, .stat %x, .nexted %x\n",
  318. __func__, __LINE__, txd->hdr, txd->data_buff, txd->stat2,
  319. txd->next_ed);
  320. /* cache flush (packet) */
  321. flush_dcache_range((ulong)packet, (ulong)packet + length);
  322. /* cache flush (txd) */
  323. flush_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
  324. /* pass descriptor table base to h/w */
  325. writel(virt_to_phys(txd), &ectl_p->txst.raw);
  326. /* ready to send enabled, hardware can now send the packet(s) */
  327. writel(ETHCON_TXRTS | ETHCON_ON, &ectl_p->con1.set);
  328. /* wait until tx has completed and h/w has released ownership
  329. * of the tx descriptor or timeout elapsed.
  330. */
  331. deadline = get_ticks() + get_tbclk();
  332. for (;;) {
  333. /* check timeout */
  334. if (get_ticks() > deadline)
  335. return -ETIMEDOUT;
  336. if (ctrlc())
  337. return -EINTR;
  338. /* tx completed ? */
  339. if (readl(&ectl_p->con1.raw) & ETHCON_TXRTS) {
  340. udelay(1);
  341. continue;
  342. }
  343. /* h/w not released ownership yet? */
  344. invalidate_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
  345. if (!(txd->hdr & EDH_EOWN))
  346. break;
  347. }
  348. return 0;
  349. }
  350. static int pic32_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  351. {
  352. struct pic32eth_dev *priv = dev_get_priv(dev);
  353. struct eth_dma_desc *rxd;
  354. u32 idx = priv->rxd_idx;
  355. u32 rx_count;
  356. /* find the next ready to receive */
  357. rxd = &priv->rxd_ring[idx];
  358. invalidate_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
  359. /* check if owned by MAC */
  360. if (rxd->hdr & EDH_EOWN)
  361. return -EAGAIN;
  362. /* Sanity check on header: SOP and EOP */
  363. if ((rxd->hdr & (EDH_SOP | EDH_EOP)) != (EDH_SOP | EDH_EOP)) {
  364. printf("%s: %s, rx pkt across multiple descr\n",
  365. __FILE__, __func__);
  366. return 0;
  367. }
  368. debug("%s: %d /idx %i, hdr=%x, data_buff %x, stat %x, nexted %x\n",
  369. __func__, __LINE__, idx, rxd->hdr,
  370. rxd->data_buff, rxd->stat2, rxd->next_ed);
  371. /* Sanity check on rx_stat: OK, CRC */
  372. if (!RSV_RX_OK(rxd->stat2) || RSV_CRC_ERR(rxd->stat2)) {
  373. debug("%s: %s: Error, rx problem detected\n",
  374. __FILE__, __func__);
  375. return 0;
  376. }
  377. /* invalidate dcache */
  378. rx_count = RSV_RX_COUNT(rxd->stat2);
  379. invalidate_dcache_range((ulong)net_rx_packets[idx],
  380. (ulong)net_rx_packets[idx] + rx_count);
  381. /* Pass the packet to protocol layer */
  382. *packetp = net_rx_packets[idx];
  383. /* increment number of bytes rcvd (ignore CRC) */
  384. return rx_count - 4;
  385. }
  386. static int pic32_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  387. {
  388. struct pic32eth_dev *priv = dev_get_priv(dev);
  389. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  390. struct eth_dma_desc *rxd;
  391. int idx = priv->rxd_idx;
  392. /* sanity check */
  393. if (packet != net_rx_packets[idx]) {
  394. printf("rxd_id %d: packet is not matched,\n", idx);
  395. return -EAGAIN;
  396. }
  397. /* prepare for receive */
  398. rxd = &priv->rxd_ring[idx];
  399. rxd->hdr = EDH_STICKY | EDH_NPV | EDH_EOWN;
  400. flush_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
  401. /* decrement rx pkt count */
  402. writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
  403. debug("%s: %d / idx %i, hdr %x, data_buff %x, stat %x, nexted %x\n",
  404. __func__, __LINE__, idx, rxd->hdr, rxd->data_buff,
  405. rxd->stat2, rxd->next_ed);
  406. priv->rxd_idx = (priv->rxd_idx + 1) % MAX_RX_DESCR;
  407. return 0;
  408. }
  409. static const struct eth_ops pic32_eth_ops = {
  410. .start = pic32_eth_start,
  411. .send = pic32_eth_send,
  412. .recv = pic32_eth_recv,
  413. .free_pkt = pic32_eth_free_pkt,
  414. .stop = pic32_eth_stop,
  415. };
  416. static int pic32_eth_probe(struct udevice *dev)
  417. {
  418. struct eth_pdata *pdata = dev_get_platdata(dev);
  419. struct pic32eth_dev *priv = dev_get_priv(dev);
  420. const char *phy_mode;
  421. void __iomem *iobase;
  422. fdt_addr_t addr;
  423. fdt_size_t size;
  424. int offset = 0;
  425. int phy_addr = -1;
  426. addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
  427. &size);
  428. if (addr == FDT_ADDR_T_NONE)
  429. return -EINVAL;
  430. iobase = ioremap(addr, size);
  431. pdata->iobase = (phys_addr_t)addr;
  432. /* get phy mode */
  433. pdata->phy_interface = -1;
  434. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  435. NULL);
  436. if (phy_mode)
  437. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  438. if (pdata->phy_interface == -1) {
  439. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  440. return -EINVAL;
  441. }
  442. /* get phy addr */
  443. offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
  444. "phy-handle");
  445. if (offset > 0)
  446. phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
  447. /* phy reset gpio */
  448. gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
  449. &priv->rst_gpio, GPIOD_IS_OUT);
  450. priv->phyif = pdata->phy_interface;
  451. priv->phy_addr = phy_addr;
  452. priv->ectl_regs = iobase;
  453. priv->emac_regs = iobase + PIC32_EMAC1CFG1;
  454. pic32_mii_init(priv);
  455. return pic32_phy_init(priv, dev);
  456. }
  457. static int pic32_eth_remove(struct udevice *dev)
  458. {
  459. struct pic32eth_dev *priv = dev_get_priv(dev);
  460. struct mii_dev *bus;
  461. dm_gpio_free(dev, &priv->rst_gpio);
  462. phy_shutdown(priv->phydev);
  463. free(priv->phydev);
  464. bus = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
  465. mdio_unregister(bus);
  466. mdio_free(bus);
  467. iounmap(priv->ectl_regs);
  468. return 0;
  469. }
  470. static const struct udevice_id pic32_eth_ids[] = {
  471. { .compatible = "microchip,pic32mzda-eth" },
  472. { }
  473. };
  474. U_BOOT_DRIVER(pic32_ethernet) = {
  475. .name = "pic32_ethernet",
  476. .id = UCLASS_ETH,
  477. .of_match = pic32_eth_ids,
  478. .probe = pic32_eth_probe,
  479. .remove = pic32_eth_remove,
  480. .ops = &pic32_eth_ops,
  481. .priv_auto_alloc_size = sizeof(struct pic32eth_dev),
  482. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  483. };