pfe_mdio.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015-2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017 NXP
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <log.h>
  9. #include <malloc.h>
  10. #include <dm/platform_data/pfe_dm_eth.h>
  11. #include <net.h>
  12. #include <linux/delay.h>
  13. #include <net/pfe_eth/pfe_eth.h>
  14. extern struct gemac_s gem_info[];
  15. #if defined(CONFIG_PHYLIB)
  16. #define MDIO_TIMEOUT 5000
  17. static int pfe_write_addr(struct mii_dev *bus, int phy_addr, int dev_addr,
  18. int reg_addr)
  19. {
  20. void *reg_base = bus->priv;
  21. u32 devadr;
  22. u32 phy;
  23. u32 reg_data;
  24. int timeout = MDIO_TIMEOUT;
  25. devadr = ((dev_addr & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT);
  26. phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
  27. reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr);
  28. writel(reg_data, reg_base + EMAC_MII_DATA_REG);
  29. /*
  30. * wait for the MII interrupt
  31. */
  32. while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
  33. if (timeout-- <= 0) {
  34. printf("Phy MDIO read/write timeout\n");
  35. return -1;
  36. }
  37. }
  38. /*
  39. * clear MII interrupt
  40. */
  41. writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
  42. return 0;
  43. }
  44. static int pfe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
  45. int reg_addr)
  46. {
  47. void *reg_base = bus->priv;
  48. u32 reg;
  49. u32 phy;
  50. u32 reg_data;
  51. u16 val;
  52. int timeout = MDIO_TIMEOUT;
  53. if (dev_addr == MDIO_DEVAD_NONE) {
  54. reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
  55. EMAC_MII_DATA_RA_SHIFT);
  56. } else {
  57. pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
  58. reg = ((dev_addr & EMAC_MII_DATA_RA_MASK) <<
  59. EMAC_MII_DATA_RA_SHIFT);
  60. }
  61. phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
  62. if (dev_addr == MDIO_DEVAD_NONE)
  63. reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD |
  64. EMAC_MII_DATA_TA | phy | reg);
  65. else
  66. reg_data = (EMAC_MII_DATA_OP_CL45_RD | EMAC_MII_DATA_TA |
  67. phy | reg);
  68. writel(reg_data, reg_base + EMAC_MII_DATA_REG);
  69. /*
  70. * wait for the MII interrupt
  71. */
  72. while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
  73. if (timeout-- <= 0) {
  74. printf("Phy MDIO read/write timeout\n");
  75. return -1;
  76. }
  77. }
  78. /*
  79. * clear MII interrupt
  80. */
  81. writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
  82. /*
  83. * it's now safe to read the PHY's register
  84. */
  85. val = (u16)readl(reg_base + EMAC_MII_DATA_REG);
  86. debug("%s: %p phy: 0x%x reg:0x%08x val:%#x\n", __func__, reg_base,
  87. phy_addr, reg_addr, val);
  88. return val;
  89. }
  90. static int pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
  91. int reg_addr, u16 data)
  92. {
  93. void *reg_base = bus->priv;
  94. u32 reg;
  95. u32 phy;
  96. u32 reg_data;
  97. int timeout = MDIO_TIMEOUT;
  98. if (dev_addr == MDIO_DEVAD_NONE) {
  99. reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
  100. EMAC_MII_DATA_RA_SHIFT);
  101. } else {
  102. pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
  103. reg = ((dev_addr & EMAC_MII_DATA_RA_MASK) <<
  104. EMAC_MII_DATA_RA_SHIFT);
  105. }
  106. phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
  107. if (dev_addr == MDIO_DEVAD_NONE)
  108. reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR |
  109. EMAC_MII_DATA_TA | phy | reg | data);
  110. else
  111. reg_data = (EMAC_MII_DATA_OP_CL45_WR | EMAC_MII_DATA_TA |
  112. phy | reg | data);
  113. writel(reg_data, reg_base + EMAC_MII_DATA_REG);
  114. /*
  115. * wait for the MII interrupt
  116. */
  117. while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
  118. if (timeout-- <= 0) {
  119. printf("Phy MDIO read/write timeout\n");
  120. return -1;
  121. }
  122. }
  123. /*
  124. * clear MII interrupt
  125. */
  126. writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
  127. debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr,
  128. reg_addr, data);
  129. return 0;
  130. }
  131. static void pfe_configure_serdes(struct pfe_eth_dev *priv)
  132. {
  133. struct mii_dev bus;
  134. int value, sgmii_2500 = 0;
  135. struct gemac_s *gem = priv->gem;
  136. if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
  137. sgmii_2500 = 1;
  138. /* PCS configuration done with corresponding GEMAC */
  139. bus.priv = gem_info[priv->gemac_port].gemac_base;
  140. pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0);
  141. pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
  142. pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x2);
  143. pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x3);
  144. /* Reset serdes */
  145. pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000);
  146. /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
  147. value = PHY_SGMII_IF_MODE_SGMII;
  148. if (!sgmii_2500)
  149. value |= PHY_SGMII_IF_MODE_AN;
  150. else
  151. value |= PHY_SGMII_IF_MODE_SGMII_GBT;
  152. pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
  153. /* Dev ability according to SGMII specification */
  154. value = PHY_SGMII_DEV_ABILITY_SGMII;
  155. pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
  156. /* These values taken from validation team */
  157. if (!sgmii_2500) {
  158. pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x0);
  159. pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0x400);
  160. } else {
  161. pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x7);
  162. pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xa120);
  163. }
  164. /* Restart AN */
  165. value = PHY_SGMII_CR_DEF_VAL;
  166. if (!sgmii_2500)
  167. value |= PHY_SGMII_CR_RESET_AN;
  168. /* Disable Auto neg for 2.5G SGMII as it doesn't support auto neg*/
  169. if (sgmii_2500)
  170. value &= ~PHY_SGMII_ENABLE_AN;
  171. pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
  172. }
  173. int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id)
  174. {
  175. struct phy_device *phydev = NULL;
  176. struct udevice *dev = priv->dev;
  177. struct gemac_s *gem = priv->gem;
  178. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  179. if (!gem->bus)
  180. return -1;
  181. /* Configure SGMII PCS */
  182. if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII ||
  183. gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) {
  184. out_be32(&scfg->mdioselcr, 0x00000000);
  185. pfe_configure_serdes(priv);
  186. }
  187. mdelay(100);
  188. /* By this time on-chip SGMII initialization is done
  189. * we can switch mdio interface to external PHYs
  190. */
  191. out_be32(&scfg->mdioselcr, 0x80000000);
  192. phydev = phy_connect(gem->bus, phy_id, dev, gem->phy_mode);
  193. if (!phydev) {
  194. printf("phy_connect failed\n");
  195. return -ENODEV;
  196. }
  197. phy_config(phydev);
  198. priv->phydev = phydev;
  199. return 0;
  200. }
  201. #endif
  202. struct mii_dev *pfe_mdio_init(struct pfe_mdio_info *mdio_info)
  203. {
  204. struct mii_dev *bus;
  205. int ret;
  206. u32 mdio_speed;
  207. u32 pclk = 250000000;
  208. bus = mdio_alloc();
  209. if (!bus) {
  210. printf("mdio_alloc failed\n");
  211. return NULL;
  212. }
  213. bus->read = pfe_phy_read;
  214. bus->write = pfe_phy_write;
  215. /* MAC1 MDIO used to communicate with external PHYS */
  216. bus->priv = mdio_info->reg_base;
  217. sprintf(bus->name, mdio_info->name);
  218. /* configure mdio speed */
  219. mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT);
  220. mdio_speed |= EMAC_HOLDTIME(0x5);
  221. writel(mdio_speed, mdio_info->reg_base + EMAC_MII_CTRL_REG);
  222. ret = mdio_register(bus);
  223. if (ret) {
  224. printf("mdio_register failed\n");
  225. free(bus);
  226. return NULL;
  227. }
  228. return bus;
  229. }
  230. void pfe_set_mdio(int dev_id, struct mii_dev *bus)
  231. {
  232. gem_info[dev_id].bus = bus;
  233. }
  234. void pfe_set_phy_address_mode(int dev_id, int phy_id, int phy_mode)
  235. {
  236. gem_info[dev_id].phy_address = phy_id;
  237. gem_info[dev_id].phy_mode = phy_mode;
  238. }