pch_gbe.h 8.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. *
  5. * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
  6. * Adapted from linux drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
  7. */
  8. #ifndef _PCH_GBE_H_
  9. #define _PCH_GBE_H_
  10. #define PCH_GBE_TIMEOUT (3 * CONFIG_SYS_HZ)
  11. #define PCH_GBE_DESC_NUM 4
  12. #define PCH_GBE_ALIGN_SIZE 64
  13. /*
  14. * Topcliff GBE MAC supports receiving ethernet frames with normal frame size
  15. * (64-1518 bytes) as well as up to 10318 bytes, however it does not have a
  16. * register bit to turn off receiving 'jumbo frame', so we have to allocate
  17. * our own buffer to store the received frames instead of using U-Boot's own.
  18. */
  19. #define PCH_GBE_RX_FRAME_LEN ROUND(10318, PCH_GBE_ALIGN_SIZE)
  20. /* Interrupt Status */
  21. /* Interrupt Status Hold */
  22. /* Interrupt Enable */
  23. #define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001
  24. #define PCH_GBE_INT_RX_VALID 0x00000002
  25. #define PCH_GBE_INT_RX_FRAME_ERR 0x00000004
  26. #define PCH_GBE_INT_RX_FIFO_ERR 0x00000008
  27. #define PCH_GBE_INT_RX_DMA_ERR 0x00000010
  28. #define PCH_GBE_INT_RX_DSC_EMP 0x00000020
  29. #define PCH_GBE_INT_TX_CMPLT 0x00000100
  30. #define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200
  31. #define PCH_GBE_INT_TX_FIFO_ERR 0x00000400
  32. #define PCH_GBE_INT_TX_DMA_ERR 0x00000800
  33. #define PCH_GBE_INT_PAUSE_CMPLT 0x00001000
  34. #define PCH_GBE_INT_MIIM_CMPLT 0x00010000
  35. #define PCH_GBE_INT_PHY_INT 0x00100000
  36. #define PCH_GBE_INT_WOL_DET 0x01000000
  37. #define PCH_GBE_INT_TCPIP_ERR 0x10000000
  38. /* Mode */
  39. #define PCH_GBE_MODE_MII_ETHER 0x00000000
  40. #define PCH_GBE_MODE_GMII_ETHER 0x80000000
  41. #define PCH_GBE_MODE_HALF_DUPLEX 0x00000000
  42. #define PCH_GBE_MODE_FULL_DUPLEX 0x40000000
  43. #define PCH_GBE_MODE_FR_BST 0x04000000
  44. /* Reset */
  45. #define PCH_GBE_ALL_RST 0x80000000
  46. #define PCH_GBE_TX_RST 0x00008000
  47. #define PCH_GBE_RX_RST 0x00004000
  48. /* TCP/IP Accelerator Control */
  49. #define PCH_GBE_EX_LIST_EN 0x00000008
  50. #define PCH_GBE_RX_TCPIPACC_OFF 0x00000004
  51. #define PCH_GBE_TX_TCPIPACC_EN 0x00000002
  52. #define PCH_GBE_RX_TCPIPACC_EN 0x00000001
  53. /* MAC RX Enable */
  54. #define PCH_GBE_MRE_MAC_RX_EN 0x00000001
  55. /* RX Flow Control */
  56. #define PCH_GBE_FL_CTRL_EN 0x80000000
  57. /* RX Mode */
  58. #define PCH_GBE_ADD_FIL_EN 0x80000000
  59. #define PCH_GBE_MLT_FIL_EN 0x40000000
  60. #define PCH_GBE_RH_ALM_EMP_4 0x00000000
  61. #define PCH_GBE_RH_ALM_EMP_8 0x00004000
  62. #define PCH_GBE_RH_ALM_EMP_16 0x00008000
  63. #define PCH_GBE_RH_ALM_EMP_32 0x0000c000
  64. #define PCH_GBE_RH_ALM_FULL_4 0x00000000
  65. #define PCH_GBE_RH_ALM_FULL_8 0x00001000
  66. #define PCH_GBE_RH_ALM_FULL_16 0x00002000
  67. #define PCH_GBE_RH_ALM_FULL_32 0x00003000
  68. #define PCH_GBE_RH_RD_TRG_4 0x00000000
  69. #define PCH_GBE_RH_RD_TRG_8 0x00000200
  70. #define PCH_GBE_RH_RD_TRG_16 0x00000400
  71. #define PCH_GBE_RH_RD_TRG_32 0x00000600
  72. #define PCH_GBE_RH_RD_TRG_64 0x00000800
  73. #define PCH_GBE_RH_RD_TRG_128 0x00000a00
  74. #define PCH_GBE_RH_RD_TRG_256 0x00000c00
  75. #define PCH_GBE_RH_RD_TRG_512 0x00000e00
  76. /* TX Mode */
  77. #define PCH_GBE_TM_NO_RTRY 0x80000000
  78. #define PCH_GBE_TM_LONG_PKT 0x40000000
  79. #define PCH_GBE_TM_ST_AND_FD 0x20000000
  80. #define PCH_GBE_TM_SHORT_PKT 0x10000000
  81. #define PCH_GBE_TM_LTCOL_RETX 0x08000000
  82. #define PCH_GBE_TM_TH_TX_STRT_4 0x00000000
  83. #define PCH_GBE_TM_TH_TX_STRT_8 0x00004000
  84. #define PCH_GBE_TM_TH_TX_STRT_16 0x00008000
  85. #define PCH_GBE_TM_TH_TX_STRT_32 0x0000c000
  86. #define PCH_GBE_TM_TH_ALM_EMP_4 0x00000000
  87. #define PCH_GBE_TM_TH_ALM_EMP_8 0x00000800
  88. #define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000
  89. #define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800
  90. #define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000
  91. #define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800
  92. #define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000
  93. #define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800
  94. #define PCH_GBE_TM_TH_ALM_FULL_4 0x00000000
  95. #define PCH_GBE_TM_TH_ALM_FULL_8 0x00000200
  96. #define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400
  97. #define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600
  98. /* MAC Address Mask */
  99. #define PCH_GBE_BUSY 0x80000000
  100. /* MIIM */
  101. #define PCH_GBE_MIIM_OPER_WRITE 0x04000000
  102. #define PCH_GBE_MIIM_OPER_READ 0x00000000
  103. #define PCH_GBE_MIIM_OPER_READY 0x04000000
  104. #define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21
  105. #define PCH_GBE_MIIM_REG_ADDR_SHIFT 16
  106. /* RGMII Control */
  107. #define PCH_GBE_CRS_SEL 0x00000010
  108. #define PCH_GBE_RGMII_RATE_125M 0x00000000
  109. #define PCH_GBE_RGMII_RATE_25M 0x00000008
  110. #define PCH_GBE_RGMII_RATE_2_5M 0x0000000c
  111. #define PCH_GBE_RGMII_MODE_GMII 0x00000000
  112. #define PCH_GBE_RGMII_MODE_RGMII 0x00000002
  113. #define PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000
  114. #define PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001
  115. /* DMA Control */
  116. #define PCH_GBE_RX_DMA_EN 0x00000002
  117. #define PCH_GBE_TX_DMA_EN 0x00000001
  118. /* Receive Descriptor bit definitions */
  119. #define PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400
  120. #define PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200
  121. #define PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100
  122. #define PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000c0
  123. #define PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080
  124. #define PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040
  125. #define PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020
  126. #define PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010
  127. #define PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008
  128. #define PCH_GBE_RXD_ACC_STAT_MACL 0x00000004
  129. #define PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002
  130. #define PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001
  131. #define PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200
  132. #define PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100
  133. #define PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080
  134. #define PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040
  135. #define PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020
  136. #define PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010
  137. #define PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008
  138. #define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004
  139. #define PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002
  140. #define PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001
  141. /* Transmit Descriptor bit definitions */
  142. #define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008
  143. #define PCH_GBE_TXD_CTRL_ITAG 0x0004
  144. #define PCH_GBE_TXD_CTRL_ICRC 0x0002
  145. #define PCH_GBE_TXD_CTRL_APAD 0x0001
  146. #define PCH_GBE_TXD_WORDS_SHIFT 2
  147. #define PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000
  148. #define PCH_GBE_TXD_GMAC_STAT_ABT 0x1000
  149. #define PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800
  150. #define PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400
  151. #define PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200
  152. #define PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100
  153. #define PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080
  154. #define PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040
  155. #define PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020
  156. #define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010
  157. /**
  158. * struct pch_gbe_rx_desc - Receive Descriptor
  159. * @buffer_addr: RX Frame Buffer Address
  160. * @tcp_ip_status: TCP/IP Accelerator Status
  161. * @rx_words_eob: RX word count and Byte position
  162. * @gbec_status: GMAC Status
  163. * @dma_status: DMA Status
  164. * @reserved1: Reserved
  165. * @reserved2: Reserved
  166. */
  167. struct pch_gbe_rx_desc {
  168. u32 buffer_addr;
  169. u32 tcp_ip_status;
  170. u16 rx_words_eob;
  171. u16 gbec_status;
  172. u8 dma_status;
  173. u8 reserved1;
  174. u16 reserved2;
  175. };
  176. /**
  177. * struct pch_gbe_tx_desc - Transmit Descriptor
  178. * @buffer_addr: TX Frame Buffer Address
  179. * @length: Data buffer length
  180. * @reserved1: Reserved
  181. * @tx_words_eob: TX word count and Byte position
  182. * @tx_frame_ctrl: TX Frame Control
  183. * @dma_status: DMA Status
  184. * @reserved2: Reserved
  185. * @gbec_status: GMAC Status
  186. */
  187. struct pch_gbe_tx_desc {
  188. u32 buffer_addr;
  189. u16 length;
  190. u16 reserved1;
  191. u16 tx_words_eob;
  192. u16 tx_frame_ctrl;
  193. u8 dma_status;
  194. u8 reserved2;
  195. u16 gbec_status;
  196. };
  197. /**
  198. * pch_gbe_regs_mac_adr - structure holding values of mac address registers
  199. *
  200. * @high Denotes the 1st to 4th byte from the initial of MAC address
  201. * @low Denotes the 5th to 6th byte from the initial of MAC address
  202. */
  203. struct pch_gbe_regs_mac_adr {
  204. u32 high;
  205. u32 low;
  206. };
  207. /**
  208. * pch_gbe_regs - structure holding values of MAC registers
  209. */
  210. struct pch_gbe_regs {
  211. u32 int_st;
  212. u32 int_en;
  213. u32 mode;
  214. u32 reset;
  215. u32 tcpip_acc;
  216. u32 ex_list;
  217. u32 int_st_hold;
  218. u32 phy_int_ctrl;
  219. u32 mac_rx_en;
  220. u32 rx_fctrl;
  221. u32 pause_req;
  222. u32 rx_mode;
  223. u32 tx_mode;
  224. u32 rx_fifo_st;
  225. u32 tx_fifo_st;
  226. u32 tx_fid;
  227. u32 tx_result;
  228. u32 pause_pkt1;
  229. u32 pause_pkt2;
  230. u32 pause_pkt3;
  231. u32 pause_pkt4;
  232. u32 pause_pkt5;
  233. u32 reserve[2];
  234. struct pch_gbe_regs_mac_adr mac_adr[16];
  235. u32 addr_mask;
  236. u32 miim;
  237. u32 mac_addr_load;
  238. u32 rgmii_st;
  239. u32 rgmii_ctrl;
  240. u32 reserve3[3];
  241. u32 dma_ctrl;
  242. u32 reserve4[3];
  243. u32 rx_dsc_base;
  244. u32 rx_dsc_size;
  245. u32 rx_dsc_hw_p;
  246. u32 rx_dsc_hw_p_hld;
  247. u32 rx_dsc_sw_p;
  248. u32 reserve5[3];
  249. u32 tx_dsc_base;
  250. u32 tx_dsc_size;
  251. u32 tx_dsc_hw_p;
  252. u32 tx_dsc_hw_p_hld;
  253. u32 tx_dsc_sw_p;
  254. u32 reserve6[3];
  255. u32 rx_dma_st;
  256. u32 tx_dma_st;
  257. u32 reserve7[2];
  258. u32 wol_st;
  259. u32 wol_ctrl;
  260. u32 wol_addr_mask;
  261. };
  262. struct pch_gbe_priv {
  263. struct pch_gbe_rx_desc rx_desc[PCH_GBE_DESC_NUM];
  264. struct pch_gbe_tx_desc tx_desc[PCH_GBE_DESC_NUM];
  265. char rx_buff[PCH_GBE_DESC_NUM][PCH_GBE_RX_FRAME_LEN];
  266. struct phy_device *phydev;
  267. struct mii_dev *bus;
  268. struct pch_gbe_regs *mac_regs;
  269. struct udevice *dev;
  270. int rx_idx;
  271. int tx_idx;
  272. };
  273. #endif /* _PCH_GBE_H_ */