natsemi.c 23 KB

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  1. /*
  2. natsemi.c: A U-Boot driver for the NatSemi DP8381x series.
  3. Author: Mark A. Rakes (mark_rakes@vivato.net)
  4. Adapted from an Etherboot driver written by:
  5. Copyright (C) 2001 Entity Cyber, Inc.
  6. This development of this Etherboot driver was funded by
  7. Sicom Systems: http://www.sicompos.com/
  8. Author: Marty Connor (mdc@thinguin.org)
  9. Adapted from a Linux driver which was written by Donald Becker
  10. This software may be used and distributed according to the terms
  11. of the GNU Public License (GPL), incorporated herein by reference.
  12. Original Copyright Notice:
  13. Written/copyright 1999-2001 by Donald Becker.
  14. This software may be used and distributed according to the terms of
  15. the GNU General Public License (GPL), incorporated herein by reference.
  16. Drivers based on or derived from this code fall under the GPL and must
  17. retain the authorship, copyright and license notice. This file is not
  18. a complete program and may only be used when the entire operating
  19. system is licensed under the GPL. License for under other terms may be
  20. available. Contact the original author for details.
  21. The original author may be reached as becker@scyld.com, or at
  22. Scyld Computing Corporation
  23. 410 Severn Ave., Suite 210
  24. Annapolis MD 21403
  25. Support information and updates available at
  26. http://www.scyld.com/network/netsemi.html
  27. References:
  28. http://www.scyld.com/expert/100mbps.html
  29. http://www.scyld.com/expert/NWay.html
  30. Datasheet is available from:
  31. http://www.national.com/pf/DP/DP83815.html
  32. */
  33. /* Revision History
  34. * October 2002 mar 1.0
  35. * Initial U-Boot Release. Tested with Netgear FA311 board
  36. * and dp83815 chipset on custom board
  37. */
  38. /* Includes */
  39. #include <common.h>
  40. #include <malloc.h>
  41. #include <net.h>
  42. #include <netdev.h>
  43. #include <asm/io.h>
  44. #include <pci.h>
  45. #include <linux/delay.h>
  46. /* defines */
  47. #define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/
  48. #define DSIZE 0x00000FFF
  49. #define CRC_SIZE 4
  50. #define TOUT_LOOP 500000
  51. #define TX_BUF_SIZE 1536
  52. #define RX_BUF_SIZE 1536
  53. #define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
  54. /* Offsets to the device registers.
  55. Unlike software-only systems, device drivers interact with complex hardware.
  56. It's not useful to define symbolic names for every register bit in the
  57. device. */
  58. enum register_offsets {
  59. ChipCmd = 0x00,
  60. ChipConfig = 0x04,
  61. EECtrl = 0x08,
  62. IntrMask = 0x14,
  63. IntrEnable = 0x18,
  64. TxRingPtr = 0x20,
  65. TxConfig = 0x24,
  66. RxRingPtr = 0x30,
  67. RxConfig = 0x34,
  68. ClkRun = 0x3C,
  69. RxFilterAddr = 0x48,
  70. RxFilterData = 0x4C,
  71. SiliconRev = 0x58,
  72. PCIPM = 0x44,
  73. BasicControl = 0x80,
  74. BasicStatus = 0x84,
  75. /* These are from the spec, around page 78... on a separate table. */
  76. PGSEL = 0xCC,
  77. PMDCSR = 0xE4,
  78. TSTDAT = 0xFC,
  79. DSPCFG = 0xF4,
  80. SDCFG = 0x8C
  81. };
  82. /* Bit in ChipCmd. */
  83. enum ChipCmdBits {
  84. ChipReset = 0x100,
  85. RxReset = 0x20,
  86. TxReset = 0x10,
  87. RxOff = 0x08,
  88. RxOn = 0x04,
  89. TxOff = 0x02,
  90. TxOn = 0x01
  91. };
  92. enum ChipConfigBits {
  93. LinkSts = 0x80000000,
  94. HundSpeed = 0x40000000,
  95. FullDuplex = 0x20000000,
  96. TenPolarity = 0x10000000,
  97. AnegDone = 0x08000000,
  98. AnegEnBothBoth = 0x0000E000,
  99. AnegDis100Full = 0x0000C000,
  100. AnegEn100Both = 0x0000A000,
  101. AnegDis100Half = 0x00008000,
  102. AnegEnBothHalf = 0x00006000,
  103. AnegDis10Full = 0x00004000,
  104. AnegEn10Both = 0x00002000,
  105. DuplexMask = 0x00008000,
  106. SpeedMask = 0x00004000,
  107. AnegMask = 0x00002000,
  108. AnegDis10Half = 0x00000000,
  109. ExtPhy = 0x00001000,
  110. PhyRst = 0x00000400,
  111. PhyDis = 0x00000200,
  112. BootRomDisable = 0x00000004,
  113. BEMode = 0x00000001,
  114. };
  115. enum TxConfig_bits {
  116. TxDrthMask = 0x3f,
  117. TxFlthMask = 0x3f00,
  118. TxMxdmaMask = 0x700000,
  119. TxMxdma_512 = 0x0,
  120. TxMxdma_4 = 0x100000,
  121. TxMxdma_8 = 0x200000,
  122. TxMxdma_16 = 0x300000,
  123. TxMxdma_32 = 0x400000,
  124. TxMxdma_64 = 0x500000,
  125. TxMxdma_128 = 0x600000,
  126. TxMxdma_256 = 0x700000,
  127. TxCollRetry = 0x800000,
  128. TxAutoPad = 0x10000000,
  129. TxMacLoop = 0x20000000,
  130. TxHeartIgn = 0x40000000,
  131. TxCarrierIgn = 0x80000000
  132. };
  133. enum RxConfig_bits {
  134. RxDrthMask = 0x3e,
  135. RxMxdmaMask = 0x700000,
  136. RxMxdma_512 = 0x0,
  137. RxMxdma_4 = 0x100000,
  138. RxMxdma_8 = 0x200000,
  139. RxMxdma_16 = 0x300000,
  140. RxMxdma_32 = 0x400000,
  141. RxMxdma_64 = 0x500000,
  142. RxMxdma_128 = 0x600000,
  143. RxMxdma_256 = 0x700000,
  144. RxAcceptLong = 0x8000000,
  145. RxAcceptTx = 0x10000000,
  146. RxAcceptRunt = 0x40000000,
  147. RxAcceptErr = 0x80000000
  148. };
  149. /* Bits in the RxMode register. */
  150. enum rx_mode_bits {
  151. AcceptErr = 0x20,
  152. AcceptRunt = 0x10,
  153. AcceptBroadcast = 0xC0000000,
  154. AcceptMulticast = 0x00200000,
  155. AcceptAllMulticast = 0x20000000,
  156. AcceptAllPhys = 0x10000000,
  157. AcceptMyPhys = 0x08000000
  158. };
  159. typedef struct _BufferDesc {
  160. u32 link;
  161. vu_long cmdsts;
  162. u32 bufptr;
  163. u32 software_use;
  164. } BufferDesc;
  165. /* Bits in network_desc.status */
  166. enum desc_status_bits {
  167. DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
  168. DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
  169. DescSizeMask = 0xfff,
  170. DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
  171. DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
  172. DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
  173. DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
  174. DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
  175. DescRxDest = 0x01800000, DescRxLong = 0x00400000,
  176. DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
  177. DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
  178. DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
  179. };
  180. /* Globals */
  181. #ifdef NATSEMI_DEBUG
  182. static int natsemi_debug = 0; /* 1 verbose debugging, 0 normal */
  183. #endif
  184. static u32 SavedClkRun;
  185. static unsigned int cur_rx;
  186. static unsigned int advertising;
  187. static unsigned int rx_config;
  188. static unsigned int tx_config;
  189. /* Note: transmit and receive buffers and descriptors must be
  190. longword aligned */
  191. static BufferDesc txd __attribute__ ((aligned(4)));
  192. static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(4)));
  193. static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(4)));
  194. static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
  195. __attribute__ ((aligned(4)));
  196. /* Function Prototypes */
  197. #if 0
  198. static void write_eeprom(struct eth_device *dev, long addr, int location,
  199. short value);
  200. #endif
  201. static int read_eeprom(struct eth_device *dev, long addr, int location);
  202. static int mdio_read(struct eth_device *dev, int phy_id, int location);
  203. static int natsemi_init(struct eth_device *dev, struct bd_info * bis);
  204. static void natsemi_reset(struct eth_device *dev);
  205. static void natsemi_init_rxfilter(struct eth_device *dev);
  206. static void natsemi_init_txd(struct eth_device *dev);
  207. static void natsemi_init_rxd(struct eth_device *dev);
  208. static void natsemi_set_rx_mode(struct eth_device *dev);
  209. static void natsemi_check_duplex(struct eth_device *dev);
  210. static int natsemi_send(struct eth_device *dev, void *packet, int length);
  211. static int natsemi_poll(struct eth_device *dev);
  212. static void natsemi_disable(struct eth_device *dev);
  213. static struct pci_device_id supported[] = {
  214. {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815},
  215. {}
  216. };
  217. #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
  218. #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
  219. static inline int
  220. INW(struct eth_device *dev, u_long addr)
  221. {
  222. return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
  223. }
  224. static int
  225. INL(struct eth_device *dev, u_long addr)
  226. {
  227. return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
  228. }
  229. static inline void
  230. OUTW(struct eth_device *dev, int command, u_long addr)
  231. {
  232. *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
  233. }
  234. static inline void
  235. OUTL(struct eth_device *dev, int command, u_long addr)
  236. {
  237. *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
  238. }
  239. /*
  240. * Function: natsemi_initialize
  241. *
  242. * Description: Retrieves the MAC address of the card, and sets up some
  243. * globals required by other routines, and initializes the NIC, making it
  244. * ready to send and receive packets.
  245. *
  246. * Side effects:
  247. * leaves the natsemi initialized, and ready to receive packets.
  248. *
  249. * Returns: struct eth_device *: pointer to NIC data structure
  250. */
  251. int
  252. natsemi_initialize(struct bd_info * bis)
  253. {
  254. pci_dev_t devno;
  255. int card_number = 0;
  256. struct eth_device *dev;
  257. u32 iobase, status, chip_config;
  258. int i, idx = 0;
  259. int prev_eedata;
  260. u32 tmp;
  261. while (1) {
  262. /* Find PCI device(s) */
  263. if ((devno = pci_find_devices(supported, idx++)) < 0) {
  264. break;
  265. }
  266. pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
  267. iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */
  268. pci_write_config_dword(devno, PCI_COMMAND,
  269. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  270. /* Check if I/O accesses and Bus Mastering are enabled. */
  271. pci_read_config_dword(devno, PCI_COMMAND, &status);
  272. if (!(status & PCI_COMMAND_MEMORY)) {
  273. printf("Error: Can not enable MEM access.\n");
  274. continue;
  275. } else if (!(status & PCI_COMMAND_MASTER)) {
  276. printf("Error: Can not enable Bus Mastering.\n");
  277. continue;
  278. }
  279. dev = (struct eth_device *) malloc(sizeof *dev);
  280. if (!dev) {
  281. printf("natsemi: Can not allocate memory\n");
  282. break;
  283. }
  284. memset(dev, 0, sizeof(*dev));
  285. sprintf(dev->name, "dp83815#%d", card_number);
  286. dev->iobase = bus_to_phys(iobase);
  287. #ifdef NATSEMI_DEBUG
  288. printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase);
  289. #endif
  290. dev->priv = (void *) devno;
  291. dev->init = natsemi_init;
  292. dev->halt = natsemi_disable;
  293. dev->send = natsemi_send;
  294. dev->recv = natsemi_poll;
  295. eth_register(dev);
  296. card_number++;
  297. /* Set the latency timer for value. */
  298. pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
  299. udelay(10 * 1000);
  300. /* natsemi has a non-standard PM control register
  301. * in PCI config space. Some boards apparently need
  302. * to be brought to D0 in this manner. */
  303. pci_read_config_dword(devno, PCIPM, &tmp);
  304. if (tmp & (0x03 | 0x100)) {
  305. /* D0 state, disable PME assertion */
  306. u32 newtmp = tmp & ~(0x03 | 0x100);
  307. pci_write_config_dword(devno, PCIPM, newtmp);
  308. }
  309. printf("natsemi: EEPROM contents:\n");
  310. for (i = 0; i <= EEPROM_SIZE; i++) {
  311. short eedata = read_eeprom(dev, EECtrl, i);
  312. printf(" %04hx", eedata);
  313. }
  314. printf("\n");
  315. /* get MAC address */
  316. prev_eedata = read_eeprom(dev, EECtrl, 6);
  317. for (i = 0; i < 3; i++) {
  318. int eedata = read_eeprom(dev, EECtrl, i + 7);
  319. dev->enetaddr[i*2] = (eedata << 1) + (prev_eedata >> 15);
  320. dev->enetaddr[i*2+1] = eedata >> 7;
  321. prev_eedata = eedata;
  322. }
  323. /* Reset the chip to erase any previous misconfiguration. */
  324. OUTL(dev, ChipReset, ChipCmd);
  325. advertising = mdio_read(dev, 1, 4);
  326. chip_config = INL(dev, ChipConfig);
  327. #ifdef NATSEMI_DEBUG
  328. printf("%s: Transceiver status %#08X advertising %#08X\n",
  329. dev->name, (int) INL(dev, BasicStatus), advertising);
  330. printf("%s: Transceiver default autoneg. %s 10%s %s duplex.\n",
  331. dev->name, chip_config & AnegMask ? "enabled, advertise" :
  332. "disabled, force", chip_config & SpeedMask ? "0" : "",
  333. chip_config & DuplexMask ? "full" : "half");
  334. #endif
  335. chip_config |= AnegEnBothBoth;
  336. #ifdef NATSEMI_DEBUG
  337. printf("%s: changed to autoneg. %s 10%s %s duplex.\n",
  338. dev->name, chip_config & AnegMask ? "enabled, advertise" :
  339. "disabled, force", chip_config & SpeedMask ? "0" : "",
  340. chip_config & DuplexMask ? "full" : "half");
  341. #endif
  342. /*write new autoneg bits, reset phy*/
  343. OUTL(dev, (chip_config | PhyRst), ChipConfig);
  344. /*un-reset phy*/
  345. OUTL(dev, chip_config, ChipConfig);
  346. /* Disable PME:
  347. * The PME bit is initialized from the EEPROM contents.
  348. * PCI cards probably have PME disabled, but motherboard
  349. * implementations may have PME set to enable WakeOnLan.
  350. * With PME set the chip will scan incoming packets but
  351. * nothing will be written to memory. */
  352. SavedClkRun = INL(dev, ClkRun);
  353. OUTL(dev, SavedClkRun & ~0x100, ClkRun);
  354. }
  355. return card_number;
  356. }
  357. /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
  358. The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */
  359. /* Delay between EEPROM clock transitions.
  360. No extra delay is needed with 33MHz PCI, but future 66MHz
  361. access may need a delay. */
  362. #define eeprom_delay(ee_addr) INL(dev, ee_addr)
  363. enum EEPROM_Ctrl_Bits {
  364. EE_ShiftClk = 0x04,
  365. EE_DataIn = 0x01,
  366. EE_ChipSelect = 0x08,
  367. EE_DataOut = 0x02
  368. };
  369. #define EE_Write0 (EE_ChipSelect)
  370. #define EE_Write1 (EE_ChipSelect | EE_DataIn)
  371. /* The EEPROM commands include the alway-set leading bit. */
  372. enum EEPROM_Cmds {
  373. EE_WrEnCmd = (4 << 6), EE_WriteCmd = (5 << 6),
  374. EE_ReadCmd = (6 << 6), EE_EraseCmd = (7 << 6),
  375. };
  376. #if 0
  377. static void
  378. write_eeprom(struct eth_device *dev, long addr, int location, short value)
  379. {
  380. int i;
  381. int ee_addr = (typeof(ee_addr))addr;
  382. short wren_cmd = EE_WrEnCmd | 0x30; /*wren is 100 + 11XXXX*/
  383. short write_cmd = location | EE_WriteCmd;
  384. #ifdef NATSEMI_DEBUG
  385. printf("write_eeprom: %08x, %04hx, %04hx\n",
  386. dev->iobase + ee_addr, write_cmd, value);
  387. #endif
  388. /* Shift the write enable command bits out. */
  389. for (i = 9; i >= 0; i--) {
  390. short cmdval = (wren_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
  391. OUTL(dev, cmdval, ee_addr);
  392. eeprom_delay(ee_addr);
  393. OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
  394. eeprom_delay(ee_addr);
  395. }
  396. OUTL(dev, 0, ee_addr); /*bring chip select low*/
  397. OUTL(dev, EE_ShiftClk, ee_addr);
  398. eeprom_delay(ee_addr);
  399. /* Shift the write command bits out. */
  400. for (i = 9; i >= 0; i--) {
  401. short cmdval = (write_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
  402. OUTL(dev, cmdval, ee_addr);
  403. eeprom_delay(ee_addr);
  404. OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
  405. eeprom_delay(ee_addr);
  406. }
  407. for (i = 0; i < 16; i++) {
  408. short cmdval = (value & (1 << i)) ? EE_Write1 : EE_Write0;
  409. OUTL(dev, cmdval, ee_addr);
  410. eeprom_delay(ee_addr);
  411. OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
  412. eeprom_delay(ee_addr);
  413. }
  414. OUTL(dev, 0, ee_addr); /*bring chip select low*/
  415. OUTL(dev, EE_ShiftClk, ee_addr);
  416. for (i = 0; i < 200000; i++) {
  417. OUTL(dev, EE_Write0, ee_addr); /*poll for done*/
  418. if (INL(dev, ee_addr) & EE_DataOut) {
  419. break; /*finished*/
  420. }
  421. }
  422. eeprom_delay(ee_addr);
  423. /* Terminate the EEPROM access. */
  424. OUTL(dev, EE_Write0, ee_addr);
  425. OUTL(dev, 0, ee_addr);
  426. return;
  427. }
  428. #endif
  429. static int
  430. read_eeprom(struct eth_device *dev, long addr, int location)
  431. {
  432. int i;
  433. int retval = 0;
  434. int ee_addr = (typeof(ee_addr))addr;
  435. int read_cmd = location | EE_ReadCmd;
  436. OUTL(dev, EE_Write0, ee_addr);
  437. /* Shift the read command bits out. */
  438. for (i = 10; i >= 0; i--) {
  439. short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
  440. OUTL(dev, dataval, ee_addr);
  441. eeprom_delay(ee_addr);
  442. OUTL(dev, dataval | EE_ShiftClk, ee_addr);
  443. eeprom_delay(ee_addr);
  444. }
  445. OUTL(dev, EE_ChipSelect, ee_addr);
  446. eeprom_delay(ee_addr);
  447. for (i = 0; i < 16; i++) {
  448. OUTL(dev, EE_ChipSelect | EE_ShiftClk, ee_addr);
  449. eeprom_delay(ee_addr);
  450. retval |= (INL(dev, ee_addr) & EE_DataOut) ? 1 << i : 0;
  451. OUTL(dev, EE_ChipSelect, ee_addr);
  452. eeprom_delay(ee_addr);
  453. }
  454. /* Terminate the EEPROM access. */
  455. OUTL(dev, EE_Write0, ee_addr);
  456. OUTL(dev, 0, ee_addr);
  457. #ifdef NATSEMI_DEBUG
  458. if (natsemi_debug)
  459. printf("read_eeprom: %08x, %08x, retval %08x\n",
  460. dev->iobase + ee_addr, read_cmd, retval);
  461. #endif
  462. return retval;
  463. }
  464. /* MII transceiver control section.
  465. The 83815 series has an internal transceiver, and we present the
  466. management registers as if they were MII connected. */
  467. static int
  468. mdio_read(struct eth_device *dev, int phy_id, int location)
  469. {
  470. if (phy_id == 1 && location < 32)
  471. return INL(dev, BasicControl+(location<<2))&0xffff;
  472. else
  473. return 0xffff;
  474. }
  475. /* Function: natsemi_init
  476. *
  477. * Description: resets the ethernet controller chip and configures
  478. * registers and data structures required for sending and receiving packets.
  479. *
  480. * Arguments: struct eth_device *dev: NIC data structure
  481. *
  482. * returns: int.
  483. */
  484. static int
  485. natsemi_init(struct eth_device *dev, struct bd_info * bis)
  486. {
  487. natsemi_reset(dev);
  488. /* Disable PME:
  489. * The PME bit is initialized from the EEPROM contents.
  490. * PCI cards probably have PME disabled, but motherboard
  491. * implementations may have PME set to enable WakeOnLan.
  492. * With PME set the chip will scan incoming packets but
  493. * nothing will be written to memory. */
  494. OUTL(dev, SavedClkRun & ~0x100, ClkRun);
  495. natsemi_init_rxfilter(dev);
  496. natsemi_init_txd(dev);
  497. natsemi_init_rxd(dev);
  498. /* Configure the PCI bus bursts and FIFO thresholds. */
  499. tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | (0x1002);
  500. rx_config = RxMxdma_256 | 0x20;
  501. #ifdef NATSEMI_DEBUG
  502. printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
  503. printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
  504. #endif
  505. OUTL(dev, tx_config, TxConfig);
  506. OUTL(dev, rx_config, RxConfig);
  507. natsemi_check_duplex(dev);
  508. natsemi_set_rx_mode(dev);
  509. OUTL(dev, (RxOn | TxOn), ChipCmd);
  510. return 1;
  511. }
  512. /*
  513. * Function: natsemi_reset
  514. *
  515. * Description: soft resets the controller chip
  516. *
  517. * Arguments: struct eth_device *dev: NIC data structure
  518. *
  519. * Returns: void.
  520. */
  521. static void
  522. natsemi_reset(struct eth_device *dev)
  523. {
  524. OUTL(dev, ChipReset, ChipCmd);
  525. /* On page 78 of the spec, they recommend some settings for "optimum
  526. performance" to be done in sequence. These settings optimize some
  527. of the 100Mbit autodetection circuitry. Also, we only want to do
  528. this for rev C of the chip. */
  529. if (INL(dev, SiliconRev) == 0x302) {
  530. OUTW(dev, 0x0001, PGSEL);
  531. OUTW(dev, 0x189C, PMDCSR);
  532. OUTW(dev, 0x0000, TSTDAT);
  533. OUTW(dev, 0x5040, DSPCFG);
  534. OUTW(dev, 0x008C, SDCFG);
  535. }
  536. /* Disable interrupts using the mask. */
  537. OUTL(dev, 0, IntrMask);
  538. OUTL(dev, 0, IntrEnable);
  539. }
  540. /* Function: natsemi_init_rxfilter
  541. *
  542. * Description: sets receive filter address to our MAC address
  543. *
  544. * Arguments: struct eth_device *dev: NIC data structure
  545. *
  546. * returns: void.
  547. */
  548. static void
  549. natsemi_init_rxfilter(struct eth_device *dev)
  550. {
  551. int i;
  552. for (i = 0; i < ETH_ALEN; i += 2) {
  553. OUTL(dev, i, RxFilterAddr);
  554. OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
  555. RxFilterData);
  556. }
  557. }
  558. /*
  559. * Function: natsemi_init_txd
  560. *
  561. * Description: initializes the Tx descriptor
  562. *
  563. * Arguments: struct eth_device *dev: NIC data structure
  564. *
  565. * returns: void.
  566. */
  567. static void
  568. natsemi_init_txd(struct eth_device *dev)
  569. {
  570. txd.link = (u32) 0;
  571. txd.cmdsts = (u32) 0;
  572. txd.bufptr = (u32) & txb[0];
  573. /* load Transmit Descriptor Register */
  574. OUTL(dev, (u32) & txd, TxRingPtr);
  575. #ifdef NATSEMI_DEBUG
  576. printf("natsemi_init_txd: TX descriptor reg loaded with: %#08X\n",
  577. INL(dev, TxRingPtr));
  578. #endif
  579. }
  580. /* Function: natsemi_init_rxd
  581. *
  582. * Description: initializes the Rx descriptor ring
  583. *
  584. * Arguments: struct eth_device *dev: NIC data structure
  585. *
  586. * Returns: void.
  587. */
  588. static void
  589. natsemi_init_rxd(struct eth_device *dev)
  590. {
  591. int i;
  592. cur_rx = 0;
  593. /* init RX descriptor */
  594. for (i = 0; i < NUM_RX_DESC; i++) {
  595. rxd[i].link =
  596. cpu_to_le32((i + 1 <
  597. NUM_RX_DESC) ? (u32) & rxd[i +
  598. 1] : (u32) &
  599. rxd[0]);
  600. rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
  601. rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
  602. #ifdef NATSEMI_DEBUG
  603. printf
  604. ("natsemi_init_rxd: rxd[%d]=%p link=%X cmdsts=%lX bufptr=%X\n",
  605. i, &rxd[i], le32_to_cpu(rxd[i].link),
  606. rxd[i].cmdsts, rxd[i].bufptr);
  607. #endif
  608. }
  609. /* load Receive Descriptor Register */
  610. OUTL(dev, (u32) & rxd[0], RxRingPtr);
  611. #ifdef NATSEMI_DEBUG
  612. printf("natsemi_init_rxd: RX descriptor register loaded with: %X\n",
  613. INL(dev, RxRingPtr));
  614. #endif
  615. }
  616. /* Function: natsemi_set_rx_mode
  617. *
  618. * Description:
  619. * sets the receive mode to accept all broadcast packets and packets
  620. * with our MAC address, and reject all multicast packets.
  621. *
  622. * Arguments: struct eth_device *dev: NIC data structure
  623. *
  624. * Returns: void.
  625. */
  626. static void
  627. natsemi_set_rx_mode(struct eth_device *dev)
  628. {
  629. u32 rx_mode = AcceptBroadcast | AcceptMyPhys;
  630. OUTL(dev, rx_mode, RxFilterAddr);
  631. }
  632. static void
  633. natsemi_check_duplex(struct eth_device *dev)
  634. {
  635. int duplex = INL(dev, ChipConfig) & FullDuplex ? 1 : 0;
  636. #ifdef NATSEMI_DEBUG
  637. printf("%s: Setting %s-duplex based on negotiated link"
  638. " capability.\n", dev->name, duplex ? "full" : "half");
  639. #endif
  640. if (duplex) {
  641. rx_config |= RxAcceptTx;
  642. tx_config |= (TxCarrierIgn | TxHeartIgn);
  643. } else {
  644. rx_config &= ~RxAcceptTx;
  645. tx_config &= ~(TxCarrierIgn | TxHeartIgn);
  646. }
  647. OUTL(dev, tx_config, TxConfig);
  648. OUTL(dev, rx_config, RxConfig);
  649. }
  650. /* Function: natsemi_send
  651. *
  652. * Description: transmits a packet and waits for completion or timeout.
  653. *
  654. * Returns: void. */
  655. static int natsemi_send(struct eth_device *dev, void *packet, int length)
  656. {
  657. u32 i, status = 0;
  658. u32 tx_status = 0;
  659. u32 *tx_ptr = &tx_status;
  660. vu_long *res = (vu_long *)tx_ptr;
  661. /* Stop the transmitter */
  662. OUTL(dev, TxOff, ChipCmd);
  663. #ifdef NATSEMI_DEBUG
  664. if (natsemi_debug)
  665. printf("natsemi_send: sending %d bytes\n", (int) length);
  666. #endif
  667. /* set the transmit buffer descriptor and enable Transmit State Machine */
  668. txd.link = cpu_to_le32(0);
  669. txd.bufptr = cpu_to_le32(phys_to_bus((u32) packet));
  670. txd.cmdsts = cpu_to_le32(DescOwn | length);
  671. /* load Transmit Descriptor Register */
  672. OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
  673. #ifdef NATSEMI_DEBUG
  674. if (natsemi_debug)
  675. printf("natsemi_send: TX descriptor register loaded with: %#08X\n",
  676. INL(dev, TxRingPtr));
  677. #endif
  678. /* restart the transmitter */
  679. OUTL(dev, TxOn, ChipCmd);
  680. for (i = 0;
  681. (*res = le32_to_cpu(txd.cmdsts)) & DescOwn;
  682. i++) {
  683. if (i >= TOUT_LOOP) {
  684. printf
  685. ("%s: tx error buffer not ready: txd.cmdsts == %#X\n",
  686. dev->name, tx_status);
  687. goto Done;
  688. }
  689. }
  690. if (!(tx_status & DescPktOK)) {
  691. printf("natsemi_send: Transmit error, Tx status %X.\n",
  692. tx_status);
  693. goto Done;
  694. }
  695. status = 1;
  696. Done:
  697. return status;
  698. }
  699. /* Function: natsemi_poll
  700. *
  701. * Description: checks for a received packet and returns it if found.
  702. *
  703. * Arguments: struct eth_device *dev: NIC data structure
  704. *
  705. * Returns: 1 if packet was received.
  706. * 0 if no packet was received.
  707. *
  708. * Side effects:
  709. * Returns (copies) the packet to the array dev->packet.
  710. * Returns the length of the packet.
  711. */
  712. static int
  713. natsemi_poll(struct eth_device *dev)
  714. {
  715. int retstat = 0;
  716. int length = 0;
  717. u32 rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
  718. if (!(rx_status & (u32) DescOwn))
  719. return retstat;
  720. #ifdef NATSEMI_DEBUG
  721. if (natsemi_debug)
  722. printf("natsemi_poll: got a packet: cur_rx:%d, status:%X\n",
  723. cur_rx, rx_status);
  724. #endif
  725. length = (rx_status & DSIZE) - CRC_SIZE;
  726. if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
  727. printf
  728. ("natsemi_poll: Corrupted packet received, buffer status = %X\n",
  729. rx_status);
  730. retstat = 0;
  731. } else { /* give packet to higher level routine */
  732. net_process_received_packet((rxb + cur_rx * RX_BUF_SIZE),
  733. length);
  734. retstat = 1;
  735. }
  736. /* return the descriptor and buffer to receive ring */
  737. rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
  738. rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
  739. if (++cur_rx == NUM_RX_DESC)
  740. cur_rx = 0;
  741. /* re-enable the potentially idle receive state machine */
  742. OUTL(dev, RxOn, ChipCmd);
  743. return retstat;
  744. }
  745. /* Function: natsemi_disable
  746. *
  747. * Description: Turns off interrupts and stops Tx and Rx engines
  748. *
  749. * Arguments: struct eth_device *dev: NIC data structure
  750. *
  751. * Returns: void.
  752. */
  753. static void
  754. natsemi_disable(struct eth_device *dev)
  755. {
  756. /* Disable interrupts using the mask. */
  757. OUTL(dev, 0, IntrMask);
  758. OUTL(dev, 0, IntrEnable);
  759. /* Stop the chip's Tx and Rx processes. */
  760. OUTL(dev, RxOff | TxOff, ChipCmd);
  761. /* Restore PME enable bit */
  762. OUTL(dev, SavedClkRun, ClkRun);
  763. }