mvgbe.h 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. *
  7. * based on - Driver for MV64360X ethernet ports
  8. * Copyright (C) 2002 rabeeh@galileo.co.il
  9. */
  10. #ifndef __MVGBE_H__
  11. #define __MVGBE_H__
  12. /* PHY_BASE_ADR is board specific and can be configured */
  13. #if defined (CONFIG_PHY_BASE_ADR)
  14. #define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
  15. #else
  16. #define PHY_BASE_ADR 0x08 /* default phy base addr */
  17. #endif
  18. /* Constants */
  19. #define INT_CAUSE_UNMASK_ALL 0x0007ffff
  20. #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
  21. #define MRU_MASK 0xfff1ffff
  22. #define PHYADR_MASK 0x0000001f
  23. #define PHYREG_MASK 0x0000001f
  24. #define QTKNBKT_DEF_VAL 0x3fffffff
  25. #define QMTBS_DEF_VAL 0x000003ff
  26. #define QTKNRT_DEF_VAL 0x0000fcff
  27. #define RXUQ 0 /* Used Rx queue */
  28. #define TXUQ 0 /* Used Rx queue */
  29. #ifndef CONFIG_DM_ETH
  30. #define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
  31. #endif
  32. #define MVGBE_REG_WR(adr, val) writel(val, &adr)
  33. #define MVGBE_REG_RD(adr) readl(&adr)
  34. #define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
  35. #define MVGBE_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
  36. /* Default port configuration value */
  37. #define PRT_CFG_VAL ( \
  38. MVGBE_UCAST_MOD_NRML | \
  39. MVGBE_DFLT_RXQ(RXUQ) | \
  40. MVGBE_DFLT_RX_ARPQ(RXUQ) | \
  41. MVGBE_RX_BC_IF_NOT_IP_OR_ARP | \
  42. MVGBE_RX_BC_IF_IP | \
  43. MVGBE_RX_BC_IF_ARP | \
  44. MVGBE_CPTR_TCP_FRMS_DIS | \
  45. MVGBE_CPTR_UDP_FRMS_DIS | \
  46. MVGBE_DFLT_RX_TCPQ(RXUQ) | \
  47. MVGBE_DFLT_RX_UDPQ(RXUQ) | \
  48. MVGBE_DFLT_RX_BPDUQ(RXUQ))
  49. /* Default port extend configuration value */
  50. #define PORT_CFG_EXTEND_VALUE \
  51. MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
  52. MVGBE_PARTITION_DIS | \
  53. MVGBE_TX_CRC_GENERATION_EN
  54. #define GT_MVGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
  55. /* Default sdma control value */
  56. #define PORT_SDMA_CFG_VALUE ( \
  57. MVGBE_RX_BURST_SIZE_16_64BIT | \
  58. MVGBE_BLM_RX_NO_SWAP | \
  59. MVGBE_BLM_TX_NO_SWAP | \
  60. GT_MVGBE_IPG_INT_RX(RXUQ) | \
  61. MVGBE_TX_BURST_SIZE_16_64BIT)
  62. /* Default port serial control value */
  63. #ifndef PORT_SERIAL_CONTROL_VALUE
  64. #define PORT_SERIAL_CONTROL_VALUE ( \
  65. MVGBE_FORCE_LINK_PASS | \
  66. MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
  67. MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
  68. MVGBE_ADV_NO_FLOW_CTRL | \
  69. MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
  70. MVGBE_FORCE_BP_MODE_NO_JAM | \
  71. (1 << 9) /* Reserved bit has to be 1 */ | \
  72. MVGBE_DO_NOT_FORCE_LINK_FAIL | \
  73. MVGBE_EN_AUTO_NEG_SPEED_GMII | \
  74. MVGBE_DTE_ADV_0 | \
  75. MVGBE_MIIPHY_MAC_MODE | \
  76. MVGBE_AUTO_NEG_NO_CHANGE | \
  77. MVGBE_MAX_RX_PACKET_1552BYTE | \
  78. MVGBE_CLR_EXT_LOOPBACK | \
  79. MVGBE_SET_FULL_DUPLEX_MODE | \
  80. MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
  81. #endif
  82. /* Tx WRR confoguration macros */
  83. #define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
  84. #define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */
  85. #define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */
  86. /* MAC accepet/reject macros */
  87. #define ACCEPT_MAC_ADDR 0
  88. #define REJECT_MAC_ADDR 1
  89. /* Size of a Tx/Rx descriptor used in chain list data structure */
  90. #define MV_RXQ_DESC_ALIGNED_SIZE \
  91. (((sizeof(struct mvgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
  92. /* Buffer offset from buffer pointer */
  93. #define RX_BUF_OFFSET 0x2
  94. /* Port serial status reg (PSR) */
  95. #define MVGBE_INTERFACE_GMII_MII 0
  96. #define MVGBE_INTERFACE_PCM 1
  97. #define MVGBE_LINK_IS_DOWN 0
  98. #define MVGBE_LINK_IS_UP (1 << 1)
  99. #define MVGBE_PORT_AT_HALF_DUPLEX 0
  100. #define MVGBE_PORT_AT_FULL_DUPLEX (1 << 2)
  101. #define MVGBE_RX_FLOW_CTRL_DISD 0
  102. #define MVGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
  103. #define MVGBE_GMII_SPEED_100_10 0
  104. #define MVGBE_GMII_SPEED_1000 (1 << 4)
  105. #define MVGBE_MII_SPEED_10 0
  106. #define MVGBE_MII_SPEED_100 (1 << 5)
  107. #define MVGBE_NO_TX 0
  108. #define MVGBE_TX_IN_PROGRESS (1 << 7)
  109. #define MVGBE_BYPASS_NO_ACTIVE 0
  110. #define MVGBE_BYPASS_ACTIVE (1 << 8)
  111. #define MVGBE_PORT_NOT_AT_PARTN_STT 0
  112. #define MVGBE_PORT_AT_PARTN_STT (1 << 9)
  113. #define MVGBE_PORT_TX_FIFO_NOT_EMPTY 0
  114. #define MVGBE_PORT_TX_FIFO_EMPTY (1 << 10)
  115. /* These macros describes the Port configuration reg (Px_cR) bits */
  116. #define MVGBE_UCAST_MOD_NRML 0
  117. #define MVGBE_UNICAST_PROMISCUOUS_MODE 1
  118. #define MVGBE_DFLT_RXQ(_x) (_x << 1)
  119. #define MVGBE_DFLT_RX_ARPQ(_x) (_x << 4)
  120. #define MVGBE_RX_BC_IF_NOT_IP_OR_ARP 0
  121. #define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
  122. #define MVGBE_RX_BC_IF_IP 0
  123. #define MVGBE_REJECT_BC_IF_IP (1 << 8)
  124. #define MVGBE_RX_BC_IF_ARP 0
  125. #define MVGBE_REJECT_BC_IF_ARP (1 << 9)
  126. #define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
  127. #define MVGBE_CPTR_TCP_FRMS_DIS 0
  128. #define MVGBE_CPTR_TCP_FRMS_EN (1 << 14)
  129. #define MVGBE_CPTR_UDP_FRMS_DIS 0
  130. #define MVGBE_CPTR_UDP_FRMS_EN (1 << 15)
  131. #define MVGBE_DFLT_RX_TCPQ(_x) (_x << 16)
  132. #define MVGBE_DFLT_RX_UDPQ(_x) (_x << 19)
  133. #define MVGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
  134. #define MVGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
  135. /* These macros describes the Port configuration extend reg (Px_cXR) bits*/
  136. #define MVGBE_CLASSIFY_EN 1
  137. #define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
  138. #define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
  139. #define MVGBE_PARTITION_DIS 0
  140. #define MVGBE_PARTITION_EN (1 << 2)
  141. #define MVGBE_TX_CRC_GENERATION_EN 0
  142. #define MVGBE_TX_CRC_GENERATION_DIS (1 << 3)
  143. /* These macros describes the Port Sdma configuration reg (SDCR) bits */
  144. #define MVGBE_RIFB 1
  145. #define MVGBE_RX_BURST_SIZE_1_64BIT 0
  146. #define MVGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
  147. #define MVGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
  148. #define MVGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
  149. #define MVGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
  150. #define MVGBE_BLM_RX_NO_SWAP (1 << 4)
  151. #define MVGBE_BLM_RX_BYTE_SWAP 0
  152. #define MVGBE_BLM_TX_NO_SWAP (1 << 5)
  153. #define MVGBE_BLM_TX_BYTE_SWAP 0
  154. #define MVGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
  155. #define MVGBE_DESCRIPTORS_NO_SWAP 0
  156. #define MVGBE_TX_BURST_SIZE_1_64BIT 0
  157. #define MVGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
  158. #define MVGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
  159. #define MVGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
  160. #define MVGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
  161. /* These macros describes the Port serial control reg (PSCR) bits */
  162. #define MVGBE_SERIAL_PORT_DIS 0
  163. #define MVGBE_SERIAL_PORT_EN 1
  164. #define MVGBE_FORCE_LINK_PASS (1 << 1)
  165. #define MVGBE_DO_NOT_FORCE_LINK_PASS 0
  166. #define MVGBE_EN_AUTO_NEG_FOR_DUPLX 0
  167. #define MVGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
  168. #define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
  169. #define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
  170. #define MVGBE_ADV_NO_FLOW_CTRL 0
  171. #define MVGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
  172. #define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
  173. #define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
  174. #define MVGBE_FORCE_BP_MODE_NO_JAM 0
  175. #define MVGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
  176. #define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
  177. #define MVGBE_FORCE_LINK_FAIL 0
  178. #define MVGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
  179. #define MVGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
  180. #define MVGBE_EN_AUTO_NEG_SPEED_GMII 0
  181. #define MVGBE_DTE_ADV_0 0
  182. #define MVGBE_DTE_ADV_1 (1 << 14)
  183. #define MVGBE_MIIPHY_MAC_MODE 0
  184. #define MVGBE_MIIPHY_PHY_MODE (1 << 15)
  185. #define MVGBE_AUTO_NEG_NO_CHANGE 0
  186. #define MVGBE_RESTART_AUTO_NEG (1 << 16)
  187. #define MVGBE_MAX_RX_PACKET_1518BYTE 0
  188. #define MVGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
  189. #define MVGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
  190. #define MVGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
  191. #define MVGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
  192. #define MVGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
  193. #define MVGBE_SET_EXT_LOOPBACK (1 << 20)
  194. #define MVGBE_CLR_EXT_LOOPBACK 0
  195. #define MVGBE_SET_FULL_DUPLEX_MODE (1 << 21)
  196. #define MVGBE_SET_HALF_DUPLEX_MODE 0
  197. #define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
  198. #define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
  199. #define MVGBE_SET_GMII_SPEED_TO_10_100 0
  200. #define MVGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
  201. #define MVGBE_SET_MII_SPEED_TO_10 0
  202. #define MVGBE_SET_MII_SPEED_TO_100 (1 << 24)
  203. /* SMI register fields */
  204. #define MVGBE_PHY_SMI_TIMEOUT 10000
  205. #define MVGBE_PHY_SMI_TIMEOUT_MS 1000
  206. #define MVGBE_PHY_SMI_DATA_OFFS 0 /* Data */
  207. #define MVGBE_PHY_SMI_DATA_MASK (0xffff << MVGBE_PHY_SMI_DATA_OFFS)
  208. #define MVGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
  209. #define MVGBE_PHY_SMI_DEV_ADDR_MASK \
  210. (PHYADR_MASK << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
  211. #define MVGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
  212. #define MVGBE_SMI_REG_ADDR_MASK \
  213. (PHYADR_MASK << MVGBE_SMI_REG_ADDR_OFFS)
  214. #define MVGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
  215. #define MVGBE_PHY_SMI_OPCODE_MASK (3 << MVGBE_PHY_SMI_OPCODE_OFFS)
  216. #define MVGBE_PHY_SMI_OPCODE_WRITE (0 << MVGBE_PHY_SMI_OPCODE_OFFS)
  217. #define MVGBE_PHY_SMI_OPCODE_READ (1 << MVGBE_PHY_SMI_OPCODE_OFFS)
  218. #define MVGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
  219. #define MVGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
  220. /* SDMA command status fields macros */
  221. /* Tx & Rx descriptors status */
  222. #define MVGBE_ERROR_SUMMARY 1
  223. /* Tx & Rx descriptors command */
  224. #define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31)
  225. /* Tx descriptors status */
  226. #define MVGBE_LC_ERROR 0
  227. #define MVGBE_UR_ERROR (1 << 1)
  228. #define MVGBE_RL_ERROR (1 << 2)
  229. #define MVGBE_LLC_SNAP_FORMAT (1 << 9)
  230. #define MVGBE_TX_LAST_FRAME (1 << 20)
  231. /* Rx descriptors status */
  232. #define MVGBE_CRC_ERROR 0
  233. #define MVGBE_OVERRUN_ERROR (1 << 1)
  234. #define MVGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
  235. #define MVGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
  236. #define MVGBE_VLAN_TAGGED (1 << 19)
  237. #define MVGBE_BPDU_FRAME (1 << 20)
  238. #define MVGBE_TCP_FRAME_OVER_IP_V_4 0
  239. #define MVGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
  240. #define MVGBE_OTHER_FRAME_TYPE (1 << 22)
  241. #define MVGBE_LAYER_2_IS_MVGBE_V_2 (1 << 23)
  242. #define MVGBE_FRAME_TYPE_IP_V_4 (1 << 24)
  243. #define MVGBE_FRAME_HEADER_OK (1 << 25)
  244. #define MVGBE_RX_LAST_DESC (1 << 26)
  245. #define MVGBE_RX_FIRST_DESC (1 << 27)
  246. #define MVGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
  247. #define MVGBE_RX_EN_INTERRUPT (1 << 29)
  248. #define MVGBE_LAYER_4_CHECKSUM_OK (1 << 30)
  249. /* Rx descriptors byte count */
  250. #define MVGBE_FRAME_FRAGMENTED (1 << 2)
  251. /* Tx descriptors command */
  252. #define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
  253. #define MVGBE_FRAME_SET_TO_VLAN (1 << 15)
  254. #define MVGBE_TCP_FRAME 0
  255. #define MVGBE_UDP_FRAME (1 << 16)
  256. #define MVGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
  257. #define MVGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
  258. #define MVGBE_ZERO_PADDING (1 << 19)
  259. #define MVGBE_TX_LAST_DESC (1 << 20)
  260. #define MVGBE_TX_FIRST_DESC (1 << 21)
  261. #define MVGBE_GEN_CRC (1 << 22)
  262. #define MVGBE_TX_EN_INTERRUPT (1 << 23)
  263. #define MVGBE_AUTO_MODE (1 << 30)
  264. /* Address decode parameters */
  265. /* Ethernet Base Address Register bits */
  266. #define EBAR_TARGET_DRAM 0x00000000
  267. #define EBAR_TARGET_DEVICE 0x00000001
  268. #define EBAR_TARGET_CBS 0x00000002
  269. #define EBAR_TARGET_PCI0 0x00000003
  270. #define EBAR_TARGET_PCI1 0x00000004
  271. #define EBAR_TARGET_CUNIT 0x00000005
  272. #define EBAR_TARGET_AUNIT 0x00000006
  273. #define EBAR_TARGET_GUNIT 0x00000007
  274. /* Window attrib */
  275. #define EBAR_DRAM_CS0 0x00000E00
  276. #define EBAR_DRAM_CS1 0x00000D00
  277. #define EBAR_DRAM_CS2 0x00000B00
  278. #define EBAR_DRAM_CS3 0x00000700
  279. /* DRAM Target interface */
  280. #define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000
  281. #define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000
  282. #define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000
  283. /* Device Bus Target interface */
  284. #define EBAR_DEVICE_DEVCS0 0x00001E00
  285. #define EBAR_DEVICE_DEVCS1 0x00001D00
  286. #define EBAR_DEVICE_DEVCS2 0x00001B00
  287. #define EBAR_DEVICE_DEVCS3 0x00001700
  288. #define EBAR_DEVICE_BOOTCS3 0x00000F00
  289. /* PCI Target interface */
  290. #define EBAR_PCI_BYTE_SWAP 0x00000000
  291. #define EBAR_PCI_NO_SWAP 0x00000100
  292. #define EBAR_PCI_BYTE_WORD_SWAP 0x00000200
  293. #define EBAR_PCI_WORD_SWAP 0x00000300
  294. #define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
  295. #define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400
  296. #define EBAR_PCI_IO_SPACE 0x00000000
  297. #define EBAR_PCI_MEMORY_SPACE 0x00000800
  298. #define EBAR_PCI_REQ64_FORCE 0x00000000
  299. #define EBAR_PCI_REQ64_SIZE 0x00001000
  300. /* Window access control */
  301. #define EWIN_ACCESS_NOT_ALLOWED 0
  302. #define EWIN_ACCESS_READ_ONLY 1
  303. #define EWIN_ACCESS_FULL ((1 << 1) | 1)
  304. /* structures represents Controller registers */
  305. struct mvgbe_barsz {
  306. u32 bar;
  307. u32 size;
  308. };
  309. struct mvgbe_rxcdp {
  310. struct mvgbe_rxdesc *rxcdp;
  311. u32 rxcdp_pad[3];
  312. };
  313. struct mvgbe_tqx {
  314. u32 qxttbc;
  315. u32 tqxtbc;
  316. u32 tqxac;
  317. u32 tqxpad;
  318. };
  319. struct mvgbe_registers {
  320. u32 phyadr;
  321. u32 smi;
  322. u32 euda;
  323. u32 eudid;
  324. u8 pad1[0x080 - 0x00c - 4];
  325. u32 euic;
  326. u32 euim;
  327. u8 pad2[0x094 - 0x084 - 4];
  328. u32 euea;
  329. u32 euiae;
  330. u8 pad3[0x0b0 - 0x098 - 4];
  331. u32 euc;
  332. u8 pad3a[0x200 - 0x0b0 - 4];
  333. struct mvgbe_barsz barsz[6];
  334. u8 pad4[0x280 - 0x22c - 4];
  335. u32 ha_remap[4];
  336. u32 bare;
  337. u32 epap;
  338. u8 pad5[0x400 - 0x294 - 4];
  339. u32 pxc;
  340. u32 pxcx;
  341. u32 mii_ser_params;
  342. u8 pad6[0x410 - 0x408 - 4];
  343. u32 evlane;
  344. u32 macal;
  345. u32 macah;
  346. u32 sdc;
  347. u32 dscp[7];
  348. u32 psc0;
  349. u32 vpt2p;
  350. u32 ps0;
  351. u32 tqc;
  352. u32 psc1;
  353. u32 ps1;
  354. u32 mrvl_header;
  355. u8 pad7[0x460 - 0x454 - 4];
  356. u32 ic;
  357. u32 ice;
  358. u32 pim;
  359. u32 peim;
  360. u8 pad8[0x474 - 0x46c - 4];
  361. u32 pxtfut;
  362. u32 pad9;
  363. u32 pxmfs;
  364. u32 pad10;
  365. u32 pxdfc;
  366. u32 pxofc;
  367. u8 pad11[0x494 - 0x488 - 4];
  368. u32 peuiae;
  369. u8 pad12[0x4bc - 0x494 - 4];
  370. u32 eth_type_prio;
  371. u8 pad13[0x4dc - 0x4bc - 4];
  372. u32 tqfpc;
  373. u32 pttbrc;
  374. u32 tqc1;
  375. u32 pmtu;
  376. u32 pmtbs;
  377. u8 pad14[0x60c - 0x4ec - 4];
  378. struct mvgbe_rxcdp rxcdp[7];
  379. struct mvgbe_rxdesc *rxcdp7;
  380. u32 rqc;
  381. struct mvgbe_txdesc *tcsdp;
  382. u8 pad15[0x6c0 - 0x684 - 4];
  383. struct mvgbe_txdesc *tcqdp[8];
  384. u8 pad16[0x700 - 0x6dc - 4];
  385. struct mvgbe_tqx tqx[8];
  386. u32 pttbc;
  387. u8 pad17[0x7a8 - 0x780 - 4];
  388. u32 tqxipg0;
  389. u32 pad18[3];
  390. u32 tqxipg1;
  391. u8 pad19[0x7c0 - 0x7b8 - 4];
  392. u32 hitkninlopkt;
  393. u32 hitkninasyncpkt;
  394. u32 lotkninasyncpkt;
  395. u32 pad20;
  396. u32 ts;
  397. u8 pad21[0x3000 - 0x27d0 - 4];
  398. u32 pad20_1[32]; /* mib counter registes */
  399. u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
  400. u32 dfsmt[64];
  401. u32 dfomt[64];
  402. u32 dfut[4];
  403. u8 pad23[0xe20c0 - 0x7360c - 4];
  404. u32 pmbus_top_arbiter;
  405. };
  406. /* structures/enums needed by driver */
  407. enum mvgbe_adrwin {
  408. MVGBE_WIN0,
  409. MVGBE_WIN1,
  410. MVGBE_WIN2,
  411. MVGBE_WIN3,
  412. MVGBE_WIN4,
  413. MVGBE_WIN5
  414. };
  415. enum mvgbe_target {
  416. MVGBE_TARGET_DRAM,
  417. MVGBE_TARGET_DEV,
  418. MVGBE_TARGET_CBS,
  419. MVGBE_TARGET_PCI0,
  420. MVGBE_TARGET_PCI1
  421. };
  422. struct mvgbe_winparam {
  423. enum mvgbe_adrwin win; /* Window number */
  424. enum mvgbe_target target; /* System targets */
  425. u16 attrib; /* BAR attrib. See above macros */
  426. u32 base_addr; /* Window base address in u32 form */
  427. u32 high_addr; /* Window high address in u32 form */
  428. u32 size; /* Size in MBytes. Must be % 64Kbyte. */
  429. int enable; /* Enable/disable access to the window. */
  430. u16 access_ctrl; /*Access ctrl register. see above macros */
  431. };
  432. struct mvgbe_rxdesc {
  433. u32 cmd_sts; /* Descriptor command status */
  434. u16 buf_size; /* Buffer size */
  435. u16 byte_cnt; /* Descriptor buffer byte count */
  436. u8 *buf_ptr; /* Descriptor buffer pointer */
  437. struct mvgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
  438. };
  439. struct mvgbe_txdesc {
  440. u32 cmd_sts; /* Descriptor command status */
  441. u16 l4i_chk; /* CPU provided TCP Checksum */
  442. u16 byte_cnt; /* Descriptor buffer byte count */
  443. u8 *buf_ptr; /* Descriptor buffer ptr */
  444. struct mvgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
  445. };
  446. /* port device data struct */
  447. struct mvgbe_device {
  448. #ifndef CONFIG_DM_ETH
  449. struct eth_device dev;
  450. #endif
  451. struct mvgbe_registers *regs;
  452. struct mvgbe_txdesc *p_txdesc;
  453. struct mvgbe_rxdesc *p_rxdesc;
  454. struct mvgbe_rxdesc *p_rxdesc_curr;
  455. u8 *p_rxbuf;
  456. u8 *p_aligned_txbuf;
  457. #ifdef CONFIG_DM_ETH
  458. phy_interface_t phy_interface;
  459. unsigned int link;
  460. unsigned int duplex;
  461. unsigned int speed;
  462. int init;
  463. int phyaddr;
  464. struct phy_device *phydev;
  465. struct mii_dev *bus;
  466. #endif
  467. };
  468. #endif /* __MVGBE_H__ */