mtk_eth.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 MediaTek Inc.
  4. *
  5. * Author: Weijie Gao <weijie.gao@mediatek.com>
  6. * Author: Mark Lee <mark-mc.lee@mediatek.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <miiphy.h>
  14. #include <net.h>
  15. #include <regmap.h>
  16. #include <reset.h>
  17. #include <syscon.h>
  18. #include <wait_bit.h>
  19. #include <asm/cache.h>
  20. #include <asm/gpio.h>
  21. #include <asm/io.h>
  22. #include <dm/device_compat.h>
  23. #include <linux/delay.h>
  24. #include <linux/err.h>
  25. #include <linux/ioport.h>
  26. #include <linux/mdio.h>
  27. #include <linux/mii.h>
  28. #include "mtk_eth.h"
  29. #define NUM_TX_DESC 24
  30. #define NUM_RX_DESC 24
  31. #define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN)
  32. #define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN)
  33. #define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE)
  34. #define MT753X_NUM_PHYS 5
  35. #define MT753X_NUM_PORTS 7
  36. #define MT753X_DFL_SMI_ADDR 31
  37. #define MT753X_SMI_ADDR_MASK 0x1f
  38. #define MT753X_PHY_ADDR(base, addr) \
  39. (((base) + (addr)) & 0x1f)
  40. #define GDMA_FWD_TO_CPU \
  41. (0x20000000 | \
  42. GDM_ICS_EN | \
  43. GDM_TCS_EN | \
  44. GDM_UCS_EN | \
  45. STRP_CRC | \
  46. (DP_PDMA << MYMAC_DP_S) | \
  47. (DP_PDMA << BC_DP_S) | \
  48. (DP_PDMA << MC_DP_S) | \
  49. (DP_PDMA << UN_DP_S))
  50. #define GDMA_FWD_DISCARD \
  51. (0x20000000 | \
  52. GDM_ICS_EN | \
  53. GDM_TCS_EN | \
  54. GDM_UCS_EN | \
  55. STRP_CRC | \
  56. (DP_DISCARD << MYMAC_DP_S) | \
  57. (DP_DISCARD << BC_DP_S) | \
  58. (DP_DISCARD << MC_DP_S) | \
  59. (DP_DISCARD << UN_DP_S))
  60. struct pdma_rxd_info1 {
  61. u32 PDP0;
  62. };
  63. struct pdma_rxd_info2 {
  64. u32 PLEN1 : 14;
  65. u32 LS1 : 1;
  66. u32 UN_USED : 1;
  67. u32 PLEN0 : 14;
  68. u32 LS0 : 1;
  69. u32 DDONE : 1;
  70. };
  71. struct pdma_rxd_info3 {
  72. u32 PDP1;
  73. };
  74. struct pdma_rxd_info4 {
  75. u32 FOE_ENTRY : 14;
  76. u32 CRSN : 5;
  77. u32 SP : 3;
  78. u32 L4F : 1;
  79. u32 L4VLD : 1;
  80. u32 TACK : 1;
  81. u32 IP4F : 1;
  82. u32 IP4 : 1;
  83. u32 IP6 : 1;
  84. u32 UN_USED : 4;
  85. };
  86. struct pdma_rxdesc {
  87. struct pdma_rxd_info1 rxd_info1;
  88. struct pdma_rxd_info2 rxd_info2;
  89. struct pdma_rxd_info3 rxd_info3;
  90. struct pdma_rxd_info4 rxd_info4;
  91. };
  92. struct pdma_txd_info1 {
  93. u32 SDP0;
  94. };
  95. struct pdma_txd_info2 {
  96. u32 SDL1 : 14;
  97. u32 LS1 : 1;
  98. u32 BURST : 1;
  99. u32 SDL0 : 14;
  100. u32 LS0 : 1;
  101. u32 DDONE : 1;
  102. };
  103. struct pdma_txd_info3 {
  104. u32 SDP1;
  105. };
  106. struct pdma_txd_info4 {
  107. u32 VLAN_TAG : 16;
  108. u32 INS : 1;
  109. u32 RESV : 2;
  110. u32 UDF : 6;
  111. u32 FPORT : 3;
  112. u32 TSO : 1;
  113. u32 TUI_CO : 3;
  114. };
  115. struct pdma_txdesc {
  116. struct pdma_txd_info1 txd_info1;
  117. struct pdma_txd_info2 txd_info2;
  118. struct pdma_txd_info3 txd_info3;
  119. struct pdma_txd_info4 txd_info4;
  120. };
  121. enum mtk_switch {
  122. SW_NONE,
  123. SW_MT7530,
  124. SW_MT7531
  125. };
  126. enum mtk_soc {
  127. SOC_MT7623,
  128. SOC_MT7629,
  129. SOC_MT7622
  130. };
  131. struct mtk_eth_priv {
  132. char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  133. struct pdma_txdesc *tx_ring_noc;
  134. struct pdma_rxdesc *rx_ring_noc;
  135. int rx_dma_owner_idx0;
  136. int tx_cpu_owner_idx0;
  137. void __iomem *fe_base;
  138. void __iomem *gmac_base;
  139. void __iomem *ethsys_base;
  140. void __iomem *sgmii_base;
  141. struct mii_dev *mdio_bus;
  142. int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
  143. int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
  144. int (*mmd_read)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg);
  145. int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
  146. u16 val);
  147. enum mtk_soc soc;
  148. int gmac_id;
  149. int force_mode;
  150. int speed;
  151. int duplex;
  152. struct phy_device *phydev;
  153. int phy_interface;
  154. int phy_addr;
  155. enum mtk_switch sw;
  156. int (*switch_init)(struct mtk_eth_priv *priv);
  157. u32 mt753x_smi_addr;
  158. u32 mt753x_phy_base;
  159. struct gpio_desc rst_gpio;
  160. int mcm;
  161. struct reset_ctl rst_fe;
  162. struct reset_ctl rst_mcm;
  163. };
  164. static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
  165. {
  166. writel(val, priv->fe_base + PDMA_BASE + reg);
  167. }
  168. static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
  169. u32 set)
  170. {
  171. clrsetbits_le32(priv->fe_base + PDMA_BASE + reg, clr, set);
  172. }
  173. static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg,
  174. u32 val)
  175. {
  176. u32 gdma_base;
  177. if (no == 1)
  178. gdma_base = GDMA2_BASE;
  179. else
  180. gdma_base = GDMA1_BASE;
  181. writel(val, priv->fe_base + gdma_base + reg);
  182. }
  183. static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
  184. {
  185. return readl(priv->gmac_base + reg);
  186. }
  187. static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
  188. {
  189. writel(val, priv->gmac_base + reg);
  190. }
  191. static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
  192. {
  193. clrsetbits_le32(priv->gmac_base + reg, clr, set);
  194. }
  195. static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
  196. u32 set)
  197. {
  198. clrsetbits_le32(priv->ethsys_base + reg, clr, set);
  199. }
  200. /* Direct MDIO clause 22/45 access via SoC */
  201. static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
  202. u32 cmd, u32 st)
  203. {
  204. int ret;
  205. u32 val;
  206. val = (st << MDIO_ST_S) |
  207. ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
  208. (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
  209. (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
  210. if (cmd == MDIO_CMD_WRITE)
  211. val |= data & MDIO_RW_DATA_M;
  212. mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
  213. ret = wait_for_bit_le32(priv->gmac_base + GMAC_PIAC_REG,
  214. PHY_ACS_ST, 0, 5000, 0);
  215. if (ret) {
  216. pr_warn("MDIO access timeout\n");
  217. return ret;
  218. }
  219. if (cmd == MDIO_CMD_READ) {
  220. val = mtk_gmac_read(priv, GMAC_PIAC_REG);
  221. return val & MDIO_RW_DATA_M;
  222. }
  223. return 0;
  224. }
  225. /* Direct MDIO clause 22 read via SoC */
  226. static int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg)
  227. {
  228. return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22);
  229. }
  230. /* Direct MDIO clause 22 write via SoC */
  231. static int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data)
  232. {
  233. return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22);
  234. }
  235. /* Direct MDIO clause 45 read via SoC */
  236. static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
  237. {
  238. int ret;
  239. ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
  240. if (ret)
  241. return ret;
  242. return mtk_mii_rw(priv, addr, devad, 0, MDIO_CMD_READ_C45,
  243. MDIO_ST_C45);
  244. }
  245. /* Direct MDIO clause 45 write via SoC */
  246. static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
  247. u16 reg, u16 val)
  248. {
  249. int ret;
  250. ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
  251. if (ret)
  252. return ret;
  253. return mtk_mii_rw(priv, addr, devad, val, MDIO_CMD_WRITE,
  254. MDIO_ST_C45);
  255. }
  256. /* Indirect MDIO clause 45 read via MII registers */
  257. static int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad,
  258. u16 reg)
  259. {
  260. int ret;
  261. ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
  262. (MMD_ADDR << MMD_CMD_S) |
  263. ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
  264. if (ret)
  265. return ret;
  266. ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
  267. if (ret)
  268. return ret;
  269. ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
  270. (MMD_DATA << MMD_CMD_S) |
  271. ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
  272. if (ret)
  273. return ret;
  274. return priv->mii_read(priv, addr, MII_MMD_ADDR_DATA_REG);
  275. }
  276. /* Indirect MDIO clause 45 write via MII registers */
  277. static int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
  278. u16 reg, u16 val)
  279. {
  280. int ret;
  281. ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
  282. (MMD_ADDR << MMD_CMD_S) |
  283. ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
  284. if (ret)
  285. return ret;
  286. ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
  287. if (ret)
  288. return ret;
  289. ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
  290. (MMD_DATA << MMD_CMD_S) |
  291. ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
  292. if (ret)
  293. return ret;
  294. return priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val);
  295. }
  296. /*
  297. * MT7530 Internal Register Address Bits
  298. * -------------------------------------------------------------------
  299. * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 |
  300. * |----------------------------------------|---------------|--------|
  301. * | Page Address | Reg Address | Unused |
  302. * -------------------------------------------------------------------
  303. */
  304. static int mt753x_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data)
  305. {
  306. int ret, low_word, high_word;
  307. /* Write page address */
  308. ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
  309. if (ret)
  310. return ret;
  311. /* Read low word */
  312. low_word = mtk_mii_read(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf);
  313. if (low_word < 0)
  314. return low_word;
  315. /* Read high word */
  316. high_word = mtk_mii_read(priv, priv->mt753x_smi_addr, 0x10);
  317. if (high_word < 0)
  318. return high_word;
  319. if (data)
  320. *data = ((u32)high_word << 16) | (low_word & 0xffff);
  321. return 0;
  322. }
  323. static int mt753x_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data)
  324. {
  325. int ret;
  326. /* Write page address */
  327. ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
  328. if (ret)
  329. return ret;
  330. /* Write low word */
  331. ret = mtk_mii_write(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf,
  332. data & 0xffff);
  333. if (ret)
  334. return ret;
  335. /* Write high word */
  336. return mtk_mii_write(priv, priv->mt753x_smi_addr, 0x10, data >> 16);
  337. }
  338. static void mt753x_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
  339. u32 set)
  340. {
  341. u32 val;
  342. mt753x_reg_read(priv, reg, &val);
  343. val &= ~clr;
  344. val |= set;
  345. mt753x_reg_write(priv, reg, val);
  346. }
  347. /* Indirect MDIO clause 22/45 access */
  348. static int mt7531_mii_rw(struct mtk_eth_priv *priv, int phy, int reg, u16 data,
  349. u32 cmd, u32 st)
  350. {
  351. ulong timeout;
  352. u32 val, timeout_ms;
  353. int ret = 0;
  354. val = (st << MDIO_ST_S) |
  355. ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
  356. ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
  357. ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
  358. if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
  359. val |= data & MDIO_RW_DATA_M;
  360. mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST);
  361. timeout_ms = 100;
  362. timeout = get_timer(0);
  363. while (1) {
  364. mt753x_reg_read(priv, MT7531_PHY_IAC, &val);
  365. if ((val & PHY_ACS_ST) == 0)
  366. break;
  367. if (get_timer(timeout) > timeout_ms)
  368. return -ETIMEDOUT;
  369. }
  370. if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
  371. mt753x_reg_read(priv, MT7531_PHY_IAC, &val);
  372. ret = val & MDIO_RW_DATA_M;
  373. }
  374. return ret;
  375. }
  376. static int mt7531_mii_ind_read(struct mtk_eth_priv *priv, u8 phy, u8 reg)
  377. {
  378. u8 phy_addr;
  379. if (phy >= MT753X_NUM_PHYS)
  380. return -EINVAL;
  381. phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy);
  382. return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ,
  383. MDIO_ST_C22);
  384. }
  385. static int mt7531_mii_ind_write(struct mtk_eth_priv *priv, u8 phy, u8 reg,
  386. u16 val)
  387. {
  388. u8 phy_addr;
  389. if (phy >= MT753X_NUM_PHYS)
  390. return -EINVAL;
  391. phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy);
  392. return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE,
  393. MDIO_ST_C22);
  394. }
  395. int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
  396. {
  397. u8 phy_addr;
  398. int ret;
  399. if (addr >= MT753X_NUM_PHYS)
  400. return -EINVAL;
  401. phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr);
  402. ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR,
  403. MDIO_ST_C45);
  404. if (ret)
  405. return ret;
  406. return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45,
  407. MDIO_ST_C45);
  408. }
  409. static int mt7531_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
  410. u16 reg, u16 val)
  411. {
  412. u8 phy_addr;
  413. int ret;
  414. if (addr >= MT753X_NUM_PHYS)
  415. return 0;
  416. phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr);
  417. ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR,
  418. MDIO_ST_C45);
  419. if (ret)
  420. return ret;
  421. return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE,
  422. MDIO_ST_C45);
  423. }
  424. static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  425. {
  426. struct mtk_eth_priv *priv = bus->priv;
  427. if (devad < 0)
  428. return priv->mii_read(priv, addr, reg);
  429. else
  430. return priv->mmd_read(priv, addr, devad, reg);
  431. }
  432. static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  433. u16 val)
  434. {
  435. struct mtk_eth_priv *priv = bus->priv;
  436. if (devad < 0)
  437. return priv->mii_write(priv, addr, reg, val);
  438. else
  439. return priv->mmd_write(priv, addr, devad, reg, val);
  440. }
  441. static int mtk_mdio_register(struct udevice *dev)
  442. {
  443. struct mtk_eth_priv *priv = dev_get_priv(dev);
  444. struct mii_dev *mdio_bus = mdio_alloc();
  445. int ret;
  446. if (!mdio_bus)
  447. return -ENOMEM;
  448. /* Assign MDIO access APIs according to the switch/phy */
  449. switch (priv->sw) {
  450. case SW_MT7530:
  451. priv->mii_read = mtk_mii_read;
  452. priv->mii_write = mtk_mii_write;
  453. priv->mmd_read = mtk_mmd_ind_read;
  454. priv->mmd_write = mtk_mmd_ind_write;
  455. break;
  456. case SW_MT7531:
  457. priv->mii_read = mt7531_mii_ind_read;
  458. priv->mii_write = mt7531_mii_ind_write;
  459. priv->mmd_read = mt7531_mmd_ind_read;
  460. priv->mmd_write = mt7531_mmd_ind_write;
  461. break;
  462. default:
  463. priv->mii_read = mtk_mii_read;
  464. priv->mii_write = mtk_mii_write;
  465. priv->mmd_read = mtk_mmd_read;
  466. priv->mmd_write = mtk_mmd_write;
  467. }
  468. mdio_bus->read = mtk_mdio_read;
  469. mdio_bus->write = mtk_mdio_write;
  470. snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name);
  471. mdio_bus->priv = (void *)priv;
  472. ret = mdio_register(mdio_bus);
  473. if (ret)
  474. return ret;
  475. priv->mdio_bus = mdio_bus;
  476. return 0;
  477. }
  478. static int mt753x_core_reg_read(struct mtk_eth_priv *priv, u32 reg)
  479. {
  480. u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0);
  481. return priv->mmd_read(priv, phy_addr, 0x1f, reg);
  482. }
  483. static void mt753x_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
  484. {
  485. u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0);
  486. priv->mmd_write(priv, phy_addr, 0x1f, reg, val);
  487. }
  488. static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode)
  489. {
  490. u32 ncpo1, ssc_delta;
  491. switch (mode) {
  492. case PHY_INTERFACE_MODE_RGMII:
  493. ncpo1 = 0x0c80;
  494. ssc_delta = 0x87;
  495. break;
  496. default:
  497. printf("error: xMII mode %d not supported\n", mode);
  498. return -EINVAL;
  499. }
  500. /* Disable MT7530 core clock */
  501. mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0);
  502. /* Disable MT7530 PLL */
  503. mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1,
  504. (2 << RG_GSWPLL_POSDIV_200M_S) |
  505. (32 << RG_GSWPLL_FBKDIV_200M_S));
  506. /* For MT7530 core clock = 500Mhz */
  507. mt753x_core_reg_write(priv, CORE_GSWPLL_GRP2,
  508. (1 << RG_GSWPLL_POSDIV_500M_S) |
  509. (25 << RG_GSWPLL_FBKDIV_500M_S));
  510. /* Enable MT7530 PLL */
  511. mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1,
  512. (2 << RG_GSWPLL_POSDIV_200M_S) |
  513. (32 << RG_GSWPLL_FBKDIV_200M_S) |
  514. RG_GSWPLL_EN_PRE);
  515. udelay(20);
  516. mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
  517. /* Setup the MT7530 TRGMII Tx Clock */
  518. mt753x_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1);
  519. mt753x_core_reg_write(priv, CORE_PLL_GROUP6, 0);
  520. mt753x_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta);
  521. mt753x_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta);
  522. mt753x_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
  523. RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
  524. mt753x_core_reg_write(priv, CORE_PLL_GROUP2,
  525. RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
  526. (1 << RG_SYSPLL_POSDIV_S));
  527. mt753x_core_reg_write(priv, CORE_PLL_GROUP7,
  528. RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) |
  529. RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
  530. /* Enable MT7530 core clock */
  531. mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG,
  532. REG_GSWCK_EN | REG_TRGMIICK_EN);
  533. return 0;
  534. }
  535. static int mt7530_setup(struct mtk_eth_priv *priv)
  536. {
  537. u16 phy_addr, phy_val;
  538. u32 val;
  539. int i;
  540. /* Select 250MHz clk for RGMII mode */
  541. mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
  542. ETHSYS_TRGMII_CLK_SEL362_5, 0);
  543. /* Modify HWTRAP first to allow direct access to internal PHYs */
  544. mt753x_reg_read(priv, HWTRAP_REG, &val);
  545. val |= CHG_TRAP;
  546. val &= ~C_MDIO_BPS;
  547. mt753x_reg_write(priv, MHWTRAP_REG, val);
  548. /* Calculate the phy base address */
  549. val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3;
  550. priv->mt753x_phy_base = (val | 0x7) + 1;
  551. /* Turn off PHYs */
  552. for (i = 0; i < MT753X_NUM_PHYS; i++) {
  553. phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
  554. phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
  555. phy_val |= BMCR_PDOWN;
  556. priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
  557. }
  558. /* Force MAC link down before reset */
  559. mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
  560. mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE);
  561. /* MT7530 reset */
  562. mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
  563. udelay(100);
  564. val = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
  565. MAC_MODE | FORCE_MODE |
  566. MAC_TX_EN | MAC_RX_EN |
  567. BKOFF_EN | BACKPR_EN |
  568. (SPEED_1000M << FORCE_SPD_S) |
  569. FORCE_DPX | FORCE_LINK;
  570. /* MT7530 Port6: Forced 1000M/FD, FC disabled */
  571. mt753x_reg_write(priv, PMCR_REG(6), val);
  572. /* MT7530 Port5: Forced link down */
  573. mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
  574. /* MT7530 Port6: Set to RGMII */
  575. mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
  576. /* Hardware Trap: Enable Port6, Disable Port5 */
  577. mt753x_reg_read(priv, HWTRAP_REG, &val);
  578. val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS |
  579. (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) |
  580. (P5_INTF_MODE_RGMII << P5_INTF_MODE_S);
  581. val &= ~(C_MDIO_BPS | P6_INTF_DIS);
  582. mt753x_reg_write(priv, MHWTRAP_REG, val);
  583. /* Setup switch core pll */
  584. mt7530_pad_clk_setup(priv, priv->phy_interface);
  585. /* Lower Tx Driving for TRGMII path */
  586. for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
  587. mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i),
  588. (8 << TD_DM_DRVP_S) | (8 << TD_DM_DRVN_S));
  589. for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
  590. mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16);
  591. /* Turn on PHYs */
  592. for (i = 0; i < MT753X_NUM_PHYS; i++) {
  593. phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
  594. phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
  595. phy_val &= ~BMCR_PDOWN;
  596. priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
  597. }
  598. return 0;
  599. }
  600. static void mt7531_core_pll_setup(struct mtk_eth_priv *priv, int mcm)
  601. {
  602. /* Step 1 : Disable MT7531 COREPLL */
  603. mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0);
  604. /* Step 2: switch to XTAL output */
  605. mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW);
  606. mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0);
  607. /* Step 3: disable PLLGP and enable program PLLGP */
  608. mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP);
  609. /* Step 4: program COREPLL output frequency to 500MHz */
  610. mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M,
  611. 2 << RG_COREPLL_POSDIV_S);
  612. udelay(25);
  613. /* Currently, support XTAL 25Mhz only */
  614. mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M,
  615. 0x140000 << RG_COREPLL_SDM_PCW_S);
  616. /* Set feedback divide ratio update signal to high */
  617. mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG,
  618. RG_COREPLL_SDM_PCW_CHG);
  619. /* Wait for at least 16 XTAL clocks */
  620. udelay(10);
  621. /* Step 5: set feedback divide ratio update signal to low */
  622. mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0);
  623. /* add enable 325M clock for SGMII */
  624. mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
  625. /* add enable 250SSC clock for RGMII */
  626. mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
  627. /*Step 6: Enable MT7531 PLL */
  628. mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN);
  629. mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL);
  630. udelay(25);
  631. }
  632. static int mt7531_port_sgmii_init(struct mtk_eth_priv *priv,
  633. u32 port)
  634. {
  635. if (port != 5 && port != 6) {
  636. printf("mt7531: port %d is not a SGMII port\n", port);
  637. return -EINVAL;
  638. }
  639. /* Set SGMII GEN2 speed(2.5G) */
  640. mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
  641. SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
  642. /* Disable SGMII AN */
  643. mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port),
  644. SGMII_AN_ENABLE, 0);
  645. /* SGMII force mode setting */
  646. mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE);
  647. /* Release PHYA power down state */
  648. mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
  649. SGMII_PHYA_PWD, 0);
  650. return 0;
  651. }
  652. static int mt7531_port_rgmii_init(struct mtk_eth_priv *priv, u32 port)
  653. {
  654. u32 val;
  655. if (port != 5) {
  656. printf("error: RGMII mode is not available for port %d\n",
  657. port);
  658. return -EINVAL;
  659. }
  660. mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val);
  661. val |= GP_CLK_EN;
  662. val &= ~GP_MODE_M;
  663. val |= GP_MODE_RGMII << GP_MODE_S;
  664. val |= TXCLK_NO_REVERSE;
  665. val |= RXCLK_NO_DELAY;
  666. val &= ~CLK_SKEW_IN_M;
  667. val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S;
  668. val &= ~CLK_SKEW_OUT_M;
  669. val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S;
  670. mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val);
  671. return 0;
  672. }
  673. static void mt7531_phy_setting(struct mtk_eth_priv *priv)
  674. {
  675. int i;
  676. u32 val;
  677. for (i = 0; i < MT753X_NUM_PHYS; i++) {
  678. /* Enable HW auto downshift */
  679. priv->mii_write(priv, i, 0x1f, 0x1);
  680. val = priv->mii_read(priv, i, PHY_EXT_REG_14);
  681. val |= PHY_EN_DOWN_SHFIT;
  682. priv->mii_write(priv, i, PHY_EXT_REG_14, val);
  683. /* PHY link down power saving enable */
  684. val = priv->mii_read(priv, i, PHY_EXT_REG_17);
  685. val |= PHY_LINKDOWN_POWER_SAVING_EN;
  686. priv->mii_write(priv, i, PHY_EXT_REG_17, val);
  687. val = priv->mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6);
  688. val &= ~PHY_POWER_SAVING_M;
  689. val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S;
  690. priv->mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val);
  691. }
  692. }
  693. static int mt7531_setup(struct mtk_eth_priv *priv)
  694. {
  695. u16 phy_addr, phy_val;
  696. u32 val;
  697. u32 pmcr;
  698. u32 port5_sgmii;
  699. int i;
  700. priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) &
  701. MT753X_SMI_ADDR_MASK;
  702. /* Turn off PHYs */
  703. for (i = 0; i < MT753X_NUM_PHYS; i++) {
  704. phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
  705. phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
  706. phy_val |= BMCR_PDOWN;
  707. priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
  708. }
  709. /* Force MAC link down before reset */
  710. mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK);
  711. mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
  712. /* Switch soft reset */
  713. mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
  714. udelay(100);
  715. /* Enable MDC input Schmitt Trigger */
  716. mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN,
  717. SMT_IOLB_5_SMI_MDC_EN);
  718. mt7531_core_pll_setup(priv, priv->mcm);
  719. mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val);
  720. port5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
  721. /* port5 support either RGMII or SGMII, port6 only support SGMII. */
  722. switch (priv->phy_interface) {
  723. case PHY_INTERFACE_MODE_RGMII:
  724. if (!port5_sgmii)
  725. mt7531_port_rgmii_init(priv, 5);
  726. break;
  727. case PHY_INTERFACE_MODE_SGMII:
  728. mt7531_port_sgmii_init(priv, 6);
  729. if (port5_sgmii)
  730. mt7531_port_sgmii_init(priv, 5);
  731. break;
  732. default:
  733. break;
  734. }
  735. pmcr = MT7531_FORCE_MODE |
  736. (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
  737. MAC_MODE | MAC_TX_EN | MAC_RX_EN |
  738. BKOFF_EN | BACKPR_EN |
  739. FORCE_RX_FC | FORCE_TX_FC |
  740. (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
  741. FORCE_LINK;
  742. mt753x_reg_write(priv, PMCR_REG(5), pmcr);
  743. mt753x_reg_write(priv, PMCR_REG(6), pmcr);
  744. /* Turn on PHYs */
  745. for (i = 0; i < MT753X_NUM_PHYS; i++) {
  746. phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
  747. phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
  748. phy_val &= ~BMCR_PDOWN;
  749. priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
  750. }
  751. mt7531_phy_setting(priv);
  752. /* Enable Internal PHYs */
  753. val = mt753x_core_reg_read(priv, CORE_PLL_GROUP4);
  754. val |= MT7531_BYPASS_MODE;
  755. val &= ~MT7531_POWER_ON_OFF;
  756. mt753x_core_reg_write(priv, CORE_PLL_GROUP4, val);
  757. return 0;
  758. }
  759. int mt753x_switch_init(struct mtk_eth_priv *priv)
  760. {
  761. int ret;
  762. int i;
  763. /* Global reset switch */
  764. if (priv->mcm) {
  765. reset_assert(&priv->rst_mcm);
  766. udelay(1000);
  767. reset_deassert(&priv->rst_mcm);
  768. mdelay(1000);
  769. } else if (dm_gpio_is_valid(&priv->rst_gpio)) {
  770. dm_gpio_set_value(&priv->rst_gpio, 0);
  771. udelay(1000);
  772. dm_gpio_set_value(&priv->rst_gpio, 1);
  773. mdelay(1000);
  774. }
  775. ret = priv->switch_init(priv);
  776. if (ret)
  777. return ret;
  778. /* Set port isolation */
  779. for (i = 0; i < MT753X_NUM_PORTS; i++) {
  780. /* Set port matrix mode */
  781. if (i != 6)
  782. mt753x_reg_write(priv, PCR_REG(i),
  783. (0x40 << PORT_MATRIX_S));
  784. else
  785. mt753x_reg_write(priv, PCR_REG(i),
  786. (0x3f << PORT_MATRIX_S));
  787. /* Set port mode to user port */
  788. mt753x_reg_write(priv, PVC_REG(i),
  789. (0x8100 << STAG_VPID_S) |
  790. (VLAN_ATTR_USER << VLAN_ATTR_S));
  791. }
  792. return 0;
  793. }
  794. static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
  795. {
  796. u16 lcl_adv = 0, rmt_adv = 0;
  797. u8 flowctrl;
  798. u32 mcr;
  799. mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
  800. (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
  801. MAC_MODE | FORCE_MODE |
  802. MAC_TX_EN | MAC_RX_EN |
  803. BKOFF_EN | BACKPR_EN;
  804. switch (priv->phydev->speed) {
  805. case SPEED_10:
  806. mcr |= (SPEED_10M << FORCE_SPD_S);
  807. break;
  808. case SPEED_100:
  809. mcr |= (SPEED_100M << FORCE_SPD_S);
  810. break;
  811. case SPEED_1000:
  812. mcr |= (SPEED_1000M << FORCE_SPD_S);
  813. break;
  814. };
  815. if (priv->phydev->link)
  816. mcr |= FORCE_LINK;
  817. if (priv->phydev->duplex) {
  818. mcr |= FORCE_DPX;
  819. if (priv->phydev->pause)
  820. rmt_adv = LPA_PAUSE_CAP;
  821. if (priv->phydev->asym_pause)
  822. rmt_adv |= LPA_PAUSE_ASYM;
  823. if (priv->phydev->advertising & ADVERTISED_Pause)
  824. lcl_adv |= ADVERTISE_PAUSE_CAP;
  825. if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
  826. lcl_adv |= ADVERTISE_PAUSE_ASYM;
  827. flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
  828. if (flowctrl & FLOW_CTRL_TX)
  829. mcr |= FORCE_TX_FC;
  830. if (flowctrl & FLOW_CTRL_RX)
  831. mcr |= FORCE_RX_FC;
  832. debug("rx pause %s, tx pause %s\n",
  833. flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
  834. flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
  835. }
  836. mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
  837. }
  838. static int mtk_phy_start(struct mtk_eth_priv *priv)
  839. {
  840. struct phy_device *phydev = priv->phydev;
  841. int ret;
  842. ret = phy_startup(phydev);
  843. if (ret) {
  844. debug("Could not initialize PHY %s\n", phydev->dev->name);
  845. return ret;
  846. }
  847. if (!phydev->link) {
  848. debug("%s: link down.\n", phydev->dev->name);
  849. return 0;
  850. }
  851. mtk_phy_link_adjust(priv);
  852. debug("Speed: %d, %s duplex%s\n", phydev->speed,
  853. (phydev->duplex) ? "full" : "half",
  854. (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
  855. return 0;
  856. }
  857. static int mtk_phy_probe(struct udevice *dev)
  858. {
  859. struct mtk_eth_priv *priv = dev_get_priv(dev);
  860. struct phy_device *phydev;
  861. phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev,
  862. priv->phy_interface);
  863. if (!phydev)
  864. return -ENODEV;
  865. phydev->supported &= PHY_GBIT_FEATURES;
  866. phydev->advertising = phydev->supported;
  867. priv->phydev = phydev;
  868. phy_config(phydev);
  869. return 0;
  870. }
  871. static void mtk_sgmii_init(struct mtk_eth_priv *priv)
  872. {
  873. /* Set SGMII GEN2 speed(2.5G) */
  874. clrsetbits_le32(priv->sgmii_base + ((priv->soc == SOC_MT7622) ?
  875. SGMSYS_GEN2_SPEED : SGMSYS_GEN2_SPEED_V2),
  876. SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
  877. /* Disable SGMII AN */
  878. clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
  879. SGMII_AN_ENABLE, 0);
  880. /* SGMII force mode setting */
  881. writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
  882. /* Release PHYA power down state */
  883. clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
  884. SGMII_PHYA_PWD, 0);
  885. }
  886. static void mtk_mac_init(struct mtk_eth_priv *priv)
  887. {
  888. int i, ge_mode = 0;
  889. u32 mcr;
  890. switch (priv->phy_interface) {
  891. case PHY_INTERFACE_MODE_RGMII_RXID:
  892. case PHY_INTERFACE_MODE_RGMII:
  893. ge_mode = GE_MODE_RGMII;
  894. break;
  895. case PHY_INTERFACE_MODE_SGMII:
  896. ge_mode = GE_MODE_RGMII;
  897. mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
  898. SYSCFG0_SGMII_SEL(priv->gmac_id));
  899. mtk_sgmii_init(priv);
  900. break;
  901. case PHY_INTERFACE_MODE_MII:
  902. case PHY_INTERFACE_MODE_GMII:
  903. ge_mode = GE_MODE_MII;
  904. break;
  905. case PHY_INTERFACE_MODE_RMII:
  906. ge_mode = GE_MODE_RMII;
  907. break;
  908. default:
  909. break;
  910. }
  911. /* set the gmac to the right mode */
  912. mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
  913. SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
  914. ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id));
  915. if (priv->force_mode) {
  916. mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
  917. (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
  918. MAC_MODE | FORCE_MODE |
  919. MAC_TX_EN | MAC_RX_EN |
  920. BKOFF_EN | BACKPR_EN |
  921. FORCE_LINK;
  922. switch (priv->speed) {
  923. case SPEED_10:
  924. mcr |= SPEED_10M << FORCE_SPD_S;
  925. break;
  926. case SPEED_100:
  927. mcr |= SPEED_100M << FORCE_SPD_S;
  928. break;
  929. case SPEED_1000:
  930. mcr |= SPEED_1000M << FORCE_SPD_S;
  931. break;
  932. }
  933. if (priv->duplex)
  934. mcr |= FORCE_DPX;
  935. mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
  936. }
  937. if (priv->soc == SOC_MT7623) {
  938. /* Lower Tx Driving for TRGMII path */
  939. for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
  940. mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i),
  941. (8 << TD_DM_DRVP_S) |
  942. (8 << TD_DM_DRVN_S));
  943. mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, 0,
  944. RX_RST | RXC_DQSISEL);
  945. mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0);
  946. }
  947. }
  948. static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
  949. {
  950. char *pkt_base = priv->pkt_pool;
  951. int i;
  952. mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0);
  953. udelay(500);
  954. memset(priv->tx_ring_noc, 0, NUM_TX_DESC * sizeof(struct pdma_txdesc));
  955. memset(priv->rx_ring_noc, 0, NUM_RX_DESC * sizeof(struct pdma_rxdesc));
  956. memset(priv->pkt_pool, 0, TOTAL_PKT_BUF_SIZE);
  957. flush_dcache_range((ulong)pkt_base,
  958. (ulong)(pkt_base + TOTAL_PKT_BUF_SIZE));
  959. priv->rx_dma_owner_idx0 = 0;
  960. priv->tx_cpu_owner_idx0 = 0;
  961. for (i = 0; i < NUM_TX_DESC; i++) {
  962. priv->tx_ring_noc[i].txd_info2.LS0 = 1;
  963. priv->tx_ring_noc[i].txd_info2.DDONE = 1;
  964. priv->tx_ring_noc[i].txd_info4.FPORT = priv->gmac_id + 1;
  965. priv->tx_ring_noc[i].txd_info1.SDP0 = virt_to_phys(pkt_base);
  966. pkt_base += PKTSIZE_ALIGN;
  967. }
  968. for (i = 0; i < NUM_RX_DESC; i++) {
  969. priv->rx_ring_noc[i].rxd_info2.PLEN0 = PKTSIZE_ALIGN;
  970. priv->rx_ring_noc[i].rxd_info1.PDP0 = virt_to_phys(pkt_base);
  971. pkt_base += PKTSIZE_ALIGN;
  972. }
  973. mtk_pdma_write(priv, TX_BASE_PTR_REG(0),
  974. virt_to_phys(priv->tx_ring_noc));
  975. mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC);
  976. mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
  977. mtk_pdma_write(priv, RX_BASE_PTR_REG(0),
  978. virt_to_phys(priv->rx_ring_noc));
  979. mtk_pdma_write(priv, RX_MAX_CNT_REG(0), NUM_RX_DESC);
  980. mtk_pdma_write(priv, RX_CRX_IDX_REG(0), NUM_RX_DESC - 1);
  981. mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0);
  982. }
  983. static int mtk_eth_start(struct udevice *dev)
  984. {
  985. struct mtk_eth_priv *priv = dev_get_priv(dev);
  986. int ret;
  987. /* Reset FE */
  988. reset_assert(&priv->rst_fe);
  989. udelay(1000);
  990. reset_deassert(&priv->rst_fe);
  991. mdelay(10);
  992. /* Packets forward to PDMA */
  993. mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
  994. if (priv->gmac_id == 0)
  995. mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
  996. else
  997. mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
  998. udelay(500);
  999. mtk_eth_fifo_init(priv);
  1000. /* Start PHY */
  1001. if (priv->sw == SW_NONE) {
  1002. ret = mtk_phy_start(priv);
  1003. if (ret)
  1004. return ret;
  1005. }
  1006. mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0,
  1007. TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
  1008. udelay(500);
  1009. return 0;
  1010. }
  1011. static void mtk_eth_stop(struct udevice *dev)
  1012. {
  1013. struct mtk_eth_priv *priv = dev_get_priv(dev);
  1014. mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG,
  1015. TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0);
  1016. udelay(500);
  1017. wait_for_bit_le32(priv->fe_base + PDMA_BASE + PDMA_GLO_CFG_REG,
  1018. RX_DMA_BUSY | TX_DMA_BUSY, 0, 5000, 0);
  1019. }
  1020. static int mtk_eth_write_hwaddr(struct udevice *dev)
  1021. {
  1022. struct eth_pdata *pdata = dev_get_platdata(dev);
  1023. struct mtk_eth_priv *priv = dev_get_priv(dev);
  1024. unsigned char *mac = pdata->enetaddr;
  1025. u32 macaddr_lsb, macaddr_msb;
  1026. macaddr_msb = ((u32)mac[0] << 8) | (u32)mac[1];
  1027. macaddr_lsb = ((u32)mac[2] << 24) | ((u32)mac[3] << 16) |
  1028. ((u32)mac[4] << 8) | (u32)mac[5];
  1029. mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_MSB_REG, macaddr_msb);
  1030. mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_LSB_REG, macaddr_lsb);
  1031. return 0;
  1032. }
  1033. static int mtk_eth_send(struct udevice *dev, void *packet, int length)
  1034. {
  1035. struct mtk_eth_priv *priv = dev_get_priv(dev);
  1036. u32 idx = priv->tx_cpu_owner_idx0;
  1037. void *pkt_base;
  1038. if (!priv->tx_ring_noc[idx].txd_info2.DDONE) {
  1039. debug("mtk-eth: TX DMA descriptor ring is full\n");
  1040. return -EPERM;
  1041. }
  1042. pkt_base = (void *)phys_to_virt(priv->tx_ring_noc[idx].txd_info1.SDP0);
  1043. memcpy(pkt_base, packet, length);
  1044. flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
  1045. roundup(length, ARCH_DMA_MINALIGN));
  1046. priv->tx_ring_noc[idx].txd_info2.SDL0 = length;
  1047. priv->tx_ring_noc[idx].txd_info2.DDONE = 0;
  1048. priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC;
  1049. mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
  1050. return 0;
  1051. }
  1052. static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  1053. {
  1054. struct mtk_eth_priv *priv = dev_get_priv(dev);
  1055. u32 idx = priv->rx_dma_owner_idx0;
  1056. uchar *pkt_base;
  1057. u32 length;
  1058. if (!priv->rx_ring_noc[idx].rxd_info2.DDONE) {
  1059. debug("mtk-eth: RX DMA descriptor ring is empty\n");
  1060. return -EAGAIN;
  1061. }
  1062. length = priv->rx_ring_noc[idx].rxd_info2.PLEN0;
  1063. pkt_base = (void *)phys_to_virt(priv->rx_ring_noc[idx].rxd_info1.PDP0);
  1064. invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base +
  1065. roundup(length, ARCH_DMA_MINALIGN));
  1066. if (packetp)
  1067. *packetp = pkt_base;
  1068. return length;
  1069. }
  1070. static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  1071. {
  1072. struct mtk_eth_priv *priv = dev_get_priv(dev);
  1073. u32 idx = priv->rx_dma_owner_idx0;
  1074. priv->rx_ring_noc[idx].rxd_info2.DDONE = 0;
  1075. priv->rx_ring_noc[idx].rxd_info2.LS0 = 0;
  1076. priv->rx_ring_noc[idx].rxd_info2.PLEN0 = PKTSIZE_ALIGN;
  1077. mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx);
  1078. priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC;
  1079. return 0;
  1080. }
  1081. static int mtk_eth_probe(struct udevice *dev)
  1082. {
  1083. struct eth_pdata *pdata = dev_get_platdata(dev);
  1084. struct mtk_eth_priv *priv = dev_get_priv(dev);
  1085. ulong iobase = pdata->iobase;
  1086. int ret;
  1087. /* Frame Engine Register Base */
  1088. priv->fe_base = (void *)iobase;
  1089. /* GMAC Register Base */
  1090. priv->gmac_base = (void *)(iobase + GMAC_BASE);
  1091. /* MDIO register */
  1092. ret = mtk_mdio_register(dev);
  1093. if (ret)
  1094. return ret;
  1095. /* Prepare for tx/rx rings */
  1096. priv->tx_ring_noc = (struct pdma_txdesc *)
  1097. noncached_alloc(sizeof(struct pdma_txdesc) * NUM_TX_DESC,
  1098. ARCH_DMA_MINALIGN);
  1099. priv->rx_ring_noc = (struct pdma_rxdesc *)
  1100. noncached_alloc(sizeof(struct pdma_rxdesc) * NUM_RX_DESC,
  1101. ARCH_DMA_MINALIGN);
  1102. /* Set MAC mode */
  1103. mtk_mac_init(priv);
  1104. /* Probe phy if switch is not specified */
  1105. if (priv->sw == SW_NONE)
  1106. return mtk_phy_probe(dev);
  1107. /* Initialize switch */
  1108. return mt753x_switch_init(priv);
  1109. }
  1110. static int mtk_eth_remove(struct udevice *dev)
  1111. {
  1112. struct mtk_eth_priv *priv = dev_get_priv(dev);
  1113. /* MDIO unregister */
  1114. mdio_unregister(priv->mdio_bus);
  1115. mdio_free(priv->mdio_bus);
  1116. /* Stop possibly started DMA */
  1117. mtk_eth_stop(dev);
  1118. return 0;
  1119. }
  1120. static int mtk_eth_ofdata_to_platdata(struct udevice *dev)
  1121. {
  1122. struct eth_pdata *pdata = dev_get_platdata(dev);
  1123. struct mtk_eth_priv *priv = dev_get_priv(dev);
  1124. struct ofnode_phandle_args args;
  1125. struct regmap *regmap;
  1126. const char *str;
  1127. ofnode subnode;
  1128. int ret;
  1129. priv->soc = dev_get_driver_data(dev);
  1130. pdata->iobase = dev_read_addr(dev);
  1131. /* get corresponding ethsys phandle */
  1132. ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0,
  1133. &args);
  1134. if (ret)
  1135. return ret;
  1136. regmap = syscon_node_to_regmap(args.node);
  1137. if (IS_ERR(regmap))
  1138. return PTR_ERR(regmap);
  1139. priv->ethsys_base = regmap_get_range(regmap, 0);
  1140. if (!priv->ethsys_base) {
  1141. dev_err(dev, "Unable to find ethsys\n");
  1142. return -ENODEV;
  1143. }
  1144. /* Reset controllers */
  1145. ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
  1146. if (ret) {
  1147. printf("error: Unable to get reset ctrl for frame engine\n");
  1148. return ret;
  1149. }
  1150. priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0);
  1151. /* Interface mode is required */
  1152. str = dev_read_string(dev, "phy-mode");
  1153. if (str) {
  1154. pdata->phy_interface = phy_get_interface_by_name(str);
  1155. priv->phy_interface = pdata->phy_interface;
  1156. } else {
  1157. printf("error: phy-mode is not set\n");
  1158. return -EINVAL;
  1159. }
  1160. /* Force mode or autoneg */
  1161. subnode = ofnode_find_subnode(dev_ofnode(dev), "fixed-link");
  1162. if (ofnode_valid(subnode)) {
  1163. priv->force_mode = 1;
  1164. priv->speed = ofnode_read_u32_default(subnode, "speed", 0);
  1165. priv->duplex = ofnode_read_bool(subnode, "full-duplex");
  1166. if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
  1167. priv->speed != SPEED_1000) {
  1168. printf("error: no valid speed set in fixed-link\n");
  1169. return -EINVAL;
  1170. }
  1171. }
  1172. if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) {
  1173. /* get corresponding sgmii phandle */
  1174. ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
  1175. NULL, 0, 0, &args);
  1176. if (ret)
  1177. return ret;
  1178. regmap = syscon_node_to_regmap(args.node);
  1179. if (IS_ERR(regmap))
  1180. return PTR_ERR(regmap);
  1181. priv->sgmii_base = regmap_get_range(regmap, 0);
  1182. if (!priv->sgmii_base) {
  1183. dev_err(dev, "Unable to find sgmii\n");
  1184. return -ENODEV;
  1185. }
  1186. }
  1187. /* check for switch first, otherwise phy will be used */
  1188. priv->sw = SW_NONE;
  1189. priv->switch_init = NULL;
  1190. str = dev_read_string(dev, "mediatek,switch");
  1191. if (str) {
  1192. if (!strcmp(str, "mt7530")) {
  1193. priv->sw = SW_MT7530;
  1194. priv->switch_init = mt7530_setup;
  1195. priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
  1196. } else if (!strcmp(str, "mt7531")) {
  1197. priv->sw = SW_MT7531;
  1198. priv->switch_init = mt7531_setup;
  1199. priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
  1200. } else {
  1201. printf("error: unsupported switch\n");
  1202. return -EINVAL;
  1203. }
  1204. priv->mcm = dev_read_bool(dev, "mediatek,mcm");
  1205. if (priv->mcm) {
  1206. ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm);
  1207. if (ret) {
  1208. printf("error: no reset ctrl for mcm\n");
  1209. return ret;
  1210. }
  1211. } else {
  1212. gpio_request_by_name(dev, "reset-gpios", 0,
  1213. &priv->rst_gpio, GPIOD_IS_OUT);
  1214. }
  1215. } else {
  1216. ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0,
  1217. 0, &args);
  1218. if (ret) {
  1219. printf("error: phy-handle is not specified\n");
  1220. return ret;
  1221. }
  1222. priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1);
  1223. if (priv->phy_addr < 0) {
  1224. printf("error: phy address is not specified\n");
  1225. return ret;
  1226. }
  1227. }
  1228. return 0;
  1229. }
  1230. static const struct udevice_id mtk_eth_ids[] = {
  1231. { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 },
  1232. { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 },
  1233. { .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 },
  1234. {}
  1235. };
  1236. static const struct eth_ops mtk_eth_ops = {
  1237. .start = mtk_eth_start,
  1238. .stop = mtk_eth_stop,
  1239. .send = mtk_eth_send,
  1240. .recv = mtk_eth_recv,
  1241. .free_pkt = mtk_eth_free_pkt,
  1242. .write_hwaddr = mtk_eth_write_hwaddr,
  1243. };
  1244. U_BOOT_DRIVER(mtk_eth) = {
  1245. .name = "mtk-eth",
  1246. .id = UCLASS_ETH,
  1247. .of_match = mtk_eth_ids,
  1248. .ofdata_to_platdata = mtk_eth_ofdata_to_platdata,
  1249. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1250. .probe = mtk_eth_probe,
  1251. .remove = mtk_eth_remove,
  1252. .ops = &mtk_eth_ops,
  1253. .priv_auto_alloc_size = sizeof(struct mtk_eth_priv),
  1254. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  1255. };