ocelot_switch.c 18 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2018 Microsemi Corporation
  4. */
  5. #include <common.h>
  6. #include <config.h>
  7. #include <dm.h>
  8. #include <log.h>
  9. #include <malloc.h>
  10. #include <dm/of_access.h>
  11. #include <dm/of_addr.h>
  12. #include <fdt_support.h>
  13. #include <linux/bitops.h>
  14. #include <linux/io.h>
  15. #include <linux/ioport.h>
  16. #include <miiphy.h>
  17. #include <net.h>
  18. #include <wait_bit.h>
  19. #include "mscc_xfer.h"
  20. #include "mscc_mac_table.h"
  21. #include "mscc_miim.h"
  22. #define PHY_CFG 0x0
  23. #define PHY_CFG_ENA 0xF
  24. #define PHY_CFG_COMMON_RST BIT(4)
  25. #define PHY_CFG_RST (0xF << 5)
  26. #define PHY_STAT 0x4
  27. #define PHY_STAT_SUPERVISOR_COMPLETE BIT(0)
  28. #define ANA_PORT_VLAN_CFG(x) (0x7000 + 0x100 * (x))
  29. #define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
  30. #define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
  31. #define ANA_PORT_PORT_CFG(x) (0x7070 + 0x100 * (x))
  32. #define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
  33. #define ANA_PGID(x) (0x8c00 + 4 * (x))
  34. #define HSIO_ANA_SERDES1G_DES_CFG 0x4c
  35. #define HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x) ((x) << 1)
  36. #define HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5)
  37. #define HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8)
  38. #define HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13)
  39. #define HSIO_ANA_SERDES1G_IB_CFG 0x50
  40. #define HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x)
  41. #define HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6)
  42. #define HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP BIT(9)
  43. #define HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11)
  44. #define HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13)
  45. #define HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24)
  46. #define HSIO_ANA_SERDES1G_OB_CFG 0x54
  47. #define HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x)
  48. #define HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x) ((x) << 4)
  49. #define HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10)
  50. #define HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x) ((x) << 13)
  51. #define HSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17)
  52. #define HSIO_ANA_SERDES1G_SER_CFG 0x58
  53. #define HSIO_ANA_SERDES1G_COMMON_CFG 0x5c
  54. #define HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE BIT(0)
  55. #define HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18)
  56. #define HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST BIT(31)
  57. #define HSIO_ANA_SERDES1G_PLL_CFG 0x60
  58. #define HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7)
  59. #define HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8)
  60. #define HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21)
  61. #define HSIO_DIG_SERDES1G_DFT_CFG0 0x68
  62. #define HSIO_DIG_SERDES1G_MISC_CFG 0x7c
  63. #define HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0)
  64. #define HSIO_MCB_SERDES1G_CFG 0x88
  65. #define HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31)
  66. #define HSIO_MCB_SERDES1G_CFG_ADDR(x) (x)
  67. #define HSIO_HW_CFGSTAT_HW_CFG 0x10c
  68. #define SYS_FRM_AGING 0x574
  69. #define SYS_FRM_AGING_ENA BIT(20)
  70. #define SYS_SYSTEM_RST_CFG 0x508
  71. #define SYS_SYSTEM_RST_MEM_INIT BIT(0)
  72. #define SYS_SYSTEM_RST_MEM_ENA BIT(1)
  73. #define SYS_SYSTEM_RST_CORE_ENA BIT(2)
  74. #define SYS_PORT_MODE(x) (0x514 + 0x4 * (x))
  75. #define SYS_PORT_MODE_INCL_INJ_HDR(x) ((x) << 3)
  76. #define SYS_PORT_MODE_INCL_INJ_HDR_M GENMASK(4, 3)
  77. #define SYS_PORT_MODE_INCL_XTR_HDR(x) ((x) << 1)
  78. #define SYS_PORT_MODE_INCL_XTR_HDR_M GENMASK(2, 1)
  79. #define SYS_PAUSE_CFG(x) (0x608 + 0x4 * (x))
  80. #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
  81. #define QSYS_SWITCH_PORT_MODE(x) (0x11234 + 0x4 * (x))
  82. #define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(14)
  83. #define QSYS_QMAP 0x112d8
  84. #define QSYS_EGR_NO_SHARING 0x1129c
  85. /* Port registers */
  86. #define DEV_CLOCK_CFG 0x0
  87. #define DEV_CLOCK_CFG_LINK_SPEED_1000 1
  88. #define DEV_MAC_ENA_CFG 0x1c
  89. #define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
  90. #define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
  91. #define DEV_MAC_IFG_CFG 0x30
  92. #define DEV_MAC_IFG_CFG_TX_IFG(x) ((x) << 8)
  93. #define DEV_MAC_IFG_CFG_RX_IFG2(x) ((x) << 4)
  94. #define DEV_MAC_IFG_CFG_RX_IFG1(x) (x)
  95. #define PCS1G_CFG 0x48
  96. #define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
  97. #define PCS1G_MODE_CFG 0x4c
  98. #define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
  99. #define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
  100. #define PCS1G_SD_CFG 0x50
  101. #define PCS1G_ANEG_CFG 0x54
  102. #define PCS1G_ANEG_CFG_ADV_ABILITY(x) ((x) << 16)
  103. #define QS_XTR_GRP_CFG(x) (4 * (x))
  104. #define QS_XTR_GRP_CFG_MODE(x) ((x) << 2)
  105. #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
  106. #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
  107. #define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4)
  108. #define QS_INJ_GRP_CFG_MODE(x) ((x) << 2)
  109. #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
  110. #define IFH_INJ_BYPASS BIT(31)
  111. #define IFH_TAG_TYPE_C 0
  112. #define MAC_VID 1
  113. #define CPU_PORT 11
  114. #define INTERNAL_PORT_MSK 0x2FF
  115. #define IFH_LEN 4
  116. #define ETH_ALEN 6
  117. #define PGID_BROADCAST 13
  118. #define PGID_UNICAST 14
  119. #define PGID_SRC 80
  120. static const char * const regs_names[] = {
  121. "port0", "port1", "port2", "port3", "port4", "port5", "port6", "port7",
  122. "port8", "port9", "port10", "sys", "rew", "qs", "hsio", "qsys", "ana",
  123. };
  124. #define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
  125. #define MAX_PORT 11
  126. enum ocelot_ctrl_regs {
  127. SYS = MAX_PORT,
  128. REW,
  129. QS,
  130. HSIO,
  131. QSYS,
  132. ANA,
  133. };
  134. #define OCELOT_MIIM_BUS_COUNT 2
  135. struct ocelot_phy_port_t {
  136. size_t phy_addr;
  137. struct mii_dev *bus;
  138. u8 serdes_index;
  139. u8 phy_mode;
  140. };
  141. struct ocelot_private {
  142. void __iomem *regs[REGS_NAMES_COUNT];
  143. struct mii_dev *bus[OCELOT_MIIM_BUS_COUNT];
  144. struct ocelot_phy_port_t ports[MAX_PORT];
  145. };
  146. static struct mscc_miim_dev miim[OCELOT_MIIM_BUS_COUNT];
  147. static int miim_count = -1;
  148. static const unsigned long ocelot_regs_qs[] = {
  149. [MSCC_QS_XTR_RD] = 0x8,
  150. [MSCC_QS_XTR_FLUSH] = 0x18,
  151. [MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
  152. [MSCC_QS_INJ_WR] = 0x2c,
  153. [MSCC_QS_INJ_CTRL] = 0x34,
  154. };
  155. static const unsigned long ocelot_regs_ana_table[] = {
  156. [MSCC_ANA_TABLES_MACHDATA] = 0x8b34,
  157. [MSCC_ANA_TABLES_MACLDATA] = 0x8b38,
  158. [MSCC_ANA_TABLES_MACACCESS] = 0x8b3c,
  159. };
  160. static void mscc_phy_reset(void)
  161. {
  162. writel(0, BASE_DEVCPU_GCB + PERF_PHY_CFG + PHY_CFG);
  163. writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
  164. | PHY_CFG_ENA, BASE_DEVCPU_GCB + PERF_PHY_CFG + PHY_CFG);
  165. if (wait_for_bit_le32((const void *)(BASE_DEVCPU_GCB + PERF_PHY_CFG) +
  166. PHY_STAT, PHY_STAT_SUPERVISOR_COMPLETE,
  167. true, 2000, false)) {
  168. pr_err("Timeout in phy reset\n");
  169. }
  170. }
  171. __weak void mscc_switch_reset(void)
  172. {
  173. }
  174. static void ocelot_stop(struct udevice *dev)
  175. {
  176. mscc_switch_reset();
  177. mscc_phy_reset();
  178. }
  179. static void ocelot_cpu_capture_setup(struct ocelot_private *priv)
  180. {
  181. int i;
  182. /* map the 8 CPU extraction queues to CPU port 11 */
  183. writel(0, priv->regs[QSYS] + QSYS_QMAP);
  184. for (i = 0; i <= 1; i++) {
  185. /*
  186. * Do byte-swap and expect status after last data word
  187. * Extraction: Mode: manual extraction) | Byte_swap
  188. */
  189. writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP,
  190. priv->regs[QS] + QS_XTR_GRP_CFG(i));
  191. /*
  192. * Injection: Mode: manual extraction | Byte_swap
  193. */
  194. writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP,
  195. priv->regs[QS] + QS_INJ_GRP_CFG(i));
  196. }
  197. for (i = 0; i <= 1; i++)
  198. /* Enable IFH insertion/parsing on CPU ports */
  199. writel(SYS_PORT_MODE_INCL_INJ_HDR(1) |
  200. SYS_PORT_MODE_INCL_XTR_HDR(1),
  201. priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));
  202. /*
  203. * Setup the CPU port as VLAN aware to support switching frames
  204. * based on tags
  205. */
  206. writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
  207. MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
  208. /* Disable learning (only RECV_ENA must be set) */
  209. writel(ANA_PORT_PORT_CFG_RECV_ENA,
  210. priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
  211. /* Enable switching to/from cpu port */
  212. setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),
  213. QSYS_SWITCH_PORT_MODE_PORT_ENA);
  214. /* No pause on CPU port - not needed (off by default) */
  215. clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),
  216. SYS_PAUSE_CFG_PAUSE_ENA);
  217. setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));
  218. }
  219. static void ocelot_port_init(struct ocelot_private *priv, int port)
  220. {
  221. void __iomem *regs = priv->regs[port];
  222. /* Enable PCS */
  223. writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG);
  224. /* Disable Signal Detect */
  225. writel(0, regs + PCS1G_SD_CFG);
  226. /* Enable MAC RX and TX */
  227. writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA,
  228. regs + DEV_MAC_ENA_CFG);
  229. /* Clear sgmii_mode_ena */
  230. writel(0, regs + PCS1G_MODE_CFG);
  231. /*
  232. * Clear sw_resolve_ena(bit 0) and set adv_ability to
  233. * something meaningful just in case
  234. */
  235. writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG);
  236. /* Set MAC IFG Gaps */
  237. writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) |
  238. DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG);
  239. /* Set link speed and release all resets */
  240. writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG);
  241. /* Make VLAN aware for CPU traffic */
  242. writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
  243. MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
  244. /* Enable the port in the core */
  245. setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port),
  246. QSYS_SWITCH_PORT_MODE_PORT_ENA);
  247. }
  248. static void serdes1g_write(void __iomem *base, u32 addr)
  249. {
  250. u32 data;
  251. writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT |
  252. HSIO_MCB_SERDES1G_CFG_ADDR(addr),
  253. base + HSIO_MCB_SERDES1G_CFG);
  254. do {
  255. data = readl(base + HSIO_MCB_SERDES1G_CFG);
  256. } while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
  257. }
  258. static void serdes1g_setup(void __iomem *base, uint32_t addr,
  259. phy_interface_t interface)
  260. {
  261. writel(0x34, base + HSIO_HW_CFGSTAT_HW_CFG);
  262. writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG);
  263. writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0);
  264. writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) |
  265. HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) |
  266. HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP |
  267. HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM |
  268. HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1),
  269. base + HSIO_ANA_SERDES1G_IB_CFG);
  270. writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) |
  271. HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) |
  272. HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) |
  273. HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6),
  274. base + HSIO_ANA_SERDES1G_DES_CFG);
  275. writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) |
  276. HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) |
  277. HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) |
  278. HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) |
  279. HSIO_ANA_SERDES1G_OB_CFG_SLP(3),
  280. base + HSIO_ANA_SERDES1G_OB_CFG);
  281. writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
  282. HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE,
  283. base + HSIO_ANA_SERDES1G_COMMON_CFG);
  284. writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA |
  285. HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) |
  286. HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2,
  287. base + HSIO_ANA_SERDES1G_PLL_CFG);
  288. writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST,
  289. base + HSIO_DIG_SERDES1G_MISC_CFG);
  290. serdes1g_write(base, addr);
  291. writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
  292. HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE |
  293. HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST,
  294. base + HSIO_ANA_SERDES1G_COMMON_CFG);
  295. serdes1g_write(base, addr);
  296. writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG);
  297. serdes1g_write(base, addr);
  298. }
  299. static void serdes_setup(struct ocelot_private *priv)
  300. {
  301. size_t mask;
  302. int i = 0;
  303. for (i = 0; i < MAX_PORT; ++i) {
  304. if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff)
  305. continue;
  306. mask = BIT(priv->ports[i].serdes_index);
  307. serdes1g_setup(priv->regs[HSIO], mask,
  308. priv->ports[i].phy_mode);
  309. }
  310. }
  311. static int ocelot_switch_init(struct ocelot_private *priv)
  312. {
  313. /* Reset switch & memories */
  314. writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
  315. priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
  316. /* Wait to complete */
  317. if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
  318. SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
  319. pr_err("Timeout in memory reset\n");
  320. return -EIO;
  321. }
  322. /* Enable switch core */
  323. setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
  324. SYS_SYSTEM_RST_CORE_ENA);
  325. serdes_setup(priv);
  326. return 0;
  327. }
  328. static int ocelot_initialize(struct ocelot_private *priv)
  329. {
  330. int ret, i;
  331. /* Initialize switch memories, enable core */
  332. ret = ocelot_switch_init(priv);
  333. if (ret)
  334. return ret;
  335. /*
  336. * Disable port-to-port by switching
  337. * Put fron ports in "port isolation modes" - i.e. they cant send
  338. * to other ports - via the PGID sorce masks.
  339. */
  340. for (i = 0; i < MAX_PORT; i++)
  341. writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i));
  342. /* Flush queues */
  343. mscc_flush(priv->regs[QS], ocelot_regs_qs);
  344. /* Setup frame ageing - "2 sec" - The unit is 6.5us on Ocelot */
  345. writel(SYS_FRM_AGING_ENA | (20000000 / 65),
  346. priv->regs[SYS] + SYS_FRM_AGING);
  347. for (i = 0; i < MAX_PORT; i++)
  348. ocelot_port_init(priv, i);
  349. ocelot_cpu_capture_setup(priv);
  350. debug("Ports enabled\n");
  351. return 0;
  352. }
  353. static int ocelot_write_hwaddr(struct udevice *dev)
  354. {
  355. struct ocelot_private *priv = dev_get_priv(dev);
  356. struct eth_pdata *pdata = dev_get_platdata(dev);
  357. mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
  358. pdata->enetaddr, PGID_UNICAST);
  359. writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
  360. return 0;
  361. }
  362. static int ocelot_start(struct udevice *dev)
  363. {
  364. struct ocelot_private *priv = dev_get_priv(dev);
  365. struct eth_pdata *pdata = dev_get_platdata(dev);
  366. const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
  367. 0xff };
  368. int ret;
  369. ret = ocelot_initialize(priv);
  370. if (ret)
  371. return ret;
  372. /* Set MAC address tables entries for CPU redirection */
  373. mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table, mac,
  374. PGID_BROADCAST);
  375. writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
  376. priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
  377. /* It should be setup latter in ocelot_write_hwaddr */
  378. mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
  379. pdata->enetaddr, PGID_UNICAST);
  380. writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
  381. return 0;
  382. }
  383. static int ocelot_send(struct udevice *dev, void *packet, int length)
  384. {
  385. struct ocelot_private *priv = dev_get_priv(dev);
  386. u32 ifh[IFH_LEN];
  387. int port = BIT(0); /* use port 0 */
  388. u32 *buf = packet;
  389. /*
  390. * Generate the IFH for frame injection
  391. *
  392. * The IFH is a 128bit-value
  393. * bit 127: bypass the analyzer processing
  394. * bit 56-67: destination mask
  395. * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
  396. * bit 20-27: cpu extraction queue mask
  397. * bit 16: tag type 0: C-tag, 1: S-tag
  398. * bit 0-11: VID
  399. */
  400. ifh[0] = IFH_INJ_BYPASS;
  401. ifh[1] = (0xf00 & port) >> 8;
  402. ifh[2] = (0xff & port) << 24;
  403. ifh[3] = (IFH_TAG_TYPE_C << 16);
  404. return mscc_send(priv->regs[QS], ocelot_regs_qs,
  405. ifh, IFH_LEN, buf, length);
  406. }
  407. static int ocelot_recv(struct udevice *dev, int flags, uchar **packetp)
  408. {
  409. struct ocelot_private *priv = dev_get_priv(dev);
  410. u32 *rxbuf = (u32 *)net_rx_packets[0];
  411. int byte_cnt;
  412. byte_cnt = mscc_recv(priv->regs[QS], ocelot_regs_qs, rxbuf, IFH_LEN,
  413. false);
  414. *packetp = net_rx_packets[0];
  415. return byte_cnt;
  416. }
  417. static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
  418. {
  419. int i = 0;
  420. for (i = 0; i < OCELOT_MIIM_BUS_COUNT; ++i)
  421. if (miim[i].miim_base == base && miim[i].miim_size == size)
  422. return miim[i].bus;
  423. return NULL;
  424. }
  425. static void add_port_entry(struct ocelot_private *priv, size_t index,
  426. size_t phy_addr, struct mii_dev *bus,
  427. u8 serdes_index, u8 phy_mode)
  428. {
  429. priv->ports[index].phy_addr = phy_addr;
  430. priv->ports[index].bus = bus;
  431. priv->ports[index].serdes_index = serdes_index;
  432. priv->ports[index].phy_mode = phy_mode;
  433. }
  434. static int external_bus(struct ocelot_private *priv, size_t port_index)
  435. {
  436. return priv->ports[port_index].serdes_index != 0xff;
  437. }
  438. static int ocelot_probe(struct udevice *dev)
  439. {
  440. struct ocelot_private *priv = dev_get_priv(dev);
  441. int i, ret;
  442. struct resource res;
  443. fdt32_t faddr;
  444. phys_addr_t addr_base;
  445. unsigned long addr_size;
  446. ofnode eth_node, node, mdio_node;
  447. size_t phy_addr;
  448. struct mii_dev *bus;
  449. struct ofnode_phandle_args phandle;
  450. struct phy_device *phy;
  451. if (!priv)
  452. return -EINVAL;
  453. for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
  454. priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
  455. if (!priv->regs[i]) {
  456. debug
  457. ("Error can't get regs base addresses for %s\n",
  458. regs_names[i]);
  459. return -ENOMEM;
  460. }
  461. }
  462. /* Initialize miim buses */
  463. memset(&miim, 0x0, sizeof(struct mscc_miim_dev) *
  464. OCELOT_MIIM_BUS_COUNT);
  465. /* iterate all the ports and find out on which bus they are */
  466. i = 0;
  467. eth_node = dev_read_first_subnode(dev);
  468. for (node = ofnode_first_subnode(eth_node); ofnode_valid(node);
  469. node = ofnode_next_subnode(node)) {
  470. if (ofnode_read_resource(node, 0, &res))
  471. return -ENOMEM;
  472. i = res.start;
  473. ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
  474. &phandle);
  475. /* Get phy address on mdio bus */
  476. if (ofnode_read_resource(phandle.node, 0, &res))
  477. return -ENOMEM;
  478. phy_addr = res.start;
  479. /* Get mdio node */
  480. mdio_node = ofnode_get_parent(phandle.node);
  481. if (ofnode_read_resource(mdio_node, 0, &res))
  482. return -ENOMEM;
  483. faddr = cpu_to_fdt32(res.start);
  484. addr_base = ofnode_translate_address(mdio_node, &faddr);
  485. addr_size = res.end - res.start;
  486. /* If the bus is new then create a new bus */
  487. if (!get_mdiobus(addr_base, addr_size))
  488. priv->bus[miim_count] =
  489. mscc_mdiobus_init(miim, &miim_count, addr_base,
  490. addr_size);
  491. /* Connect mdio bus with the port */
  492. bus = get_mdiobus(addr_base, addr_size);
  493. /* Get serdes info */
  494. ret = ofnode_parse_phandle_with_args(node, "phys", NULL,
  495. 3, 0, &phandle);
  496. if (ret)
  497. add_port_entry(priv, i, phy_addr, bus, 0xff, 0xff);
  498. else
  499. add_port_entry(priv, i, phy_addr, bus, phandle.args[1],
  500. phandle.args[2]);
  501. }
  502. mscc_phy_reset();
  503. for (i = 0; i < MAX_PORT; i++) {
  504. if (!priv->ports[i].bus)
  505. continue;
  506. phy = phy_connect(priv->ports[i].bus,
  507. priv->ports[i].phy_addr, dev,
  508. PHY_INTERFACE_MODE_NONE);
  509. if (phy && external_bus(priv, i))
  510. board_phy_config(phy);
  511. }
  512. return 0;
  513. }
  514. static int ocelot_remove(struct udevice *dev)
  515. {
  516. struct ocelot_private *priv = dev_get_priv(dev);
  517. int i;
  518. for (i = 0; i < OCELOT_MIIM_BUS_COUNT; i++) {
  519. mdio_unregister(priv->bus[i]);
  520. mdio_free(priv->bus[i]);
  521. }
  522. return 0;
  523. }
  524. static const struct eth_ops ocelot_ops = {
  525. .start = ocelot_start,
  526. .stop = ocelot_stop,
  527. .send = ocelot_send,
  528. .recv = ocelot_recv,
  529. .write_hwaddr = ocelot_write_hwaddr,
  530. };
  531. static const struct udevice_id mscc_ocelot_ids[] = {
  532. {.compatible = "mscc,vsc7514-switch"},
  533. { /* Sentinel */ }
  534. };
  535. U_BOOT_DRIVER(ocelot) = {
  536. .name = "ocelot-switch",
  537. .id = UCLASS_ETH,
  538. .of_match = mscc_ocelot_ids,
  539. .probe = ocelot_probe,
  540. .remove = ocelot_remove,
  541. .ops = &ocelot_ops,
  542. .priv_auto_alloc_size = sizeof(struct ocelot_private),
  543. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  544. };