luton_switch.c 21 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2019 Microsemi Corporation
  4. */
  5. #include <common.h>
  6. #include <config.h>
  7. #include <dm.h>
  8. #include <malloc.h>
  9. #include <dm/of_access.h>
  10. #include <dm/of_addr.h>
  11. #include <fdt_support.h>
  12. #include <linux/bitops.h>
  13. #include <linux/io.h>
  14. #include <linux/ioport.h>
  15. #include <miiphy.h>
  16. #include <net.h>
  17. #include <wait_bit.h>
  18. #include "mscc_xfer.h"
  19. #include "mscc_mac_table.h"
  20. #include "mscc_miim.h"
  21. #define ANA_PORT_VLAN_CFG(x) (0x00 + 0x80 * (x))
  22. #define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
  23. #define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
  24. #define ANA_PORT_CPU_FWD_CFG(x) (0x50 + 0x80 * (x))
  25. #define ANA_PORT_CPU_FWD_CFG_SRC_COPY_ENA BIT(1)
  26. #define ANA_PORT_PORT_CFG(x) (0x60 + 0x80 * (x))
  27. #define ANA_PORT_PORT_CFG_RECV_ENA BIT(5)
  28. #define ANA_PGID(x) (0x1000 + 4 * (x))
  29. #define SYS_FRM_AGING 0x8300
  30. #define SYS_SYSTEM_RST_CFG 0x81b0
  31. #define SYS_SYSTEM_RST_MEM_INIT BIT(0)
  32. #define SYS_SYSTEM_RST_MEM_ENA BIT(1)
  33. #define SYS_SYSTEM_RST_CORE_ENA BIT(2)
  34. #define SYS_PORT_MODE(x) (0x81bc + 0x4 * (x))
  35. #define SYS_PORT_MODE_INCL_INJ_HDR BIT(0)
  36. #define SYS_SWITCH_PORT_MODE(x) (0x8294 + 0x4 * (x))
  37. #define SYS_SWITCH_PORT_MODE_PORT_ENA BIT(3)
  38. #define SYS_EGR_NO_SHARING 0x8378
  39. #define SYS_SCH_CPU 0x85a0
  40. #define REW_PORT_CFG(x) (0x8 + 0x80 * (x))
  41. #define REW_PORT_CFG_IFH_INSERT_ENA BIT(7)
  42. #define GCB_DEVCPU_RST_SOFT_CHIP_RST 0x90
  43. #define GCB_DEVCPU_RST_SOFT_CHIP_RST_SOFT_PHY BIT(1)
  44. #define GCB_MISC_STAT 0x11c
  45. #define GCB_MISC_STAT_PHY_READY BIT(3)
  46. #define QS_XTR_MAP(x) (0x10 + 4 * (x))
  47. #define QS_XTR_MAP_GRP BIT(4)
  48. #define QS_XTR_MAP_ENA BIT(0)
  49. #define HSIO_PLL5G_CFG_PLL5G_CFG2 0x8
  50. #define HSIO_RCOMP_CFG_CFG0 0x20
  51. #define HSIO_RCOMP_CFG_CFG0_MODE_SEL(x) ((x) << 8)
  52. #define HSIO_RCOMP_CFG_CFG0_RUN_CAL BIT(12)
  53. #define HSIO_RCOMP_STATUS 0x24
  54. #define HSIO_RCOMP_STATUS_BUSY BIT(12)
  55. #define HSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0)
  56. #define HSIO_SERDES6G_ANA_CFG_DES_CFG 0x64
  57. #define HSIO_SERDES6G_ANA_CFG_DES_CFG_BW_ANA(x) ((x) << 1)
  58. #define HSIO_SERDES6G_ANA_CFG_DES_CFG_BW_HYST(x) ((x) << 5)
  59. #define HSIO_SERDES6G_ANA_CFG_DES_CFG_MBTR_CTRL(x) ((x) << 10)
  60. #define HSIO_SERDES6G_ANA_CFG_DES_CFG_PHS_CTRL(x) ((x) << 13)
  61. #define HSIO_SERDES6G_ANA_CFG_IB_CFG 0x68
  62. #define HSIO_SERDES6G_ANA_CFG_IB_CFG_RESISTOR_CTRL(x) (x)
  63. #define HSIO_SERDES6G_ANA_CFG_IB_CFG_VBCOM(x) ((x) << 4)
  64. #define HSIO_SERDES6G_ANA_CFG_IB_CFG_VBAC(x) ((x) << 7)
  65. #define HSIO_SERDES6G_ANA_CFG_IB_CFG_RT(x) ((x) << 9)
  66. #define HSIO_SERDES6G_ANA_CFG_IB_CFG_RF(x) ((x) << 14)
  67. #define HSIO_SERDES6G_ANA_CFG_IB_CFG1 0x6c
  68. #define HSIO_SERDES6G_ANA_CFG_IB_CFG1_RST BIT(0)
  69. #define HSIO_SERDES6G_ANA_CFG_IB_CFG1_ENA_OFFSDC BIT(2)
  70. #define HSIO_SERDES6G_ANA_CFG_IB_CFG1_ENA_OFFSAC BIT(3)
  71. #define HSIO_SERDES6G_ANA_CFG_IB_CFG1_ANEG_MODE BIT(6)
  72. #define HSIO_SERDES6G_ANA_CFG_IB_CFG1_CHF BIT(7)
  73. #define HSIO_SERDES6G_ANA_CFG_IB_CFG1_C(x) ((x) << 8)
  74. #define HSIO_SERDES6G_ANA_CFG_OB_CFG 0x70
  75. #define HSIO_SERDES6G_ANA_CFG_OB_CFG_SR(x) ((x) << 4)
  76. #define HSIO_SERDES6G_ANA_CFG_OB_CFG_SR_H BIT(8)
  77. #define HSIO_SERDES6G_ANA_CFG_OB_CFG_POST0(x) ((x) << 23)
  78. #define HSIO_SERDES6G_ANA_CFG_OB_CFG_POL BIT(29)
  79. #define HSIO_SERDES6G_ANA_CFG_OB_CFG_ENA1V_MODE BIT(30)
  80. #define HSIO_SERDES6G_ANA_CFG_OB_CFG1 0x74
  81. #define HSIO_SERDES6G_ANA_CFG_OB_CFG1_LEV(x) (x)
  82. #define HSIO_SERDES6G_ANA_CFG_OB_CFG1_ENA_CAS(x) ((x) << 6)
  83. #define HSIO_SERDES6G_ANA_CFG_COMMON_CFG 0x7c
  84. #define HSIO_SERDES6G_ANA_CFG_COMMON_CFG_IF_MODE(x) (x)
  85. #define HSIO_SERDES6G_ANA_CFG_COMMON_CFG_ENA_LANE BIT(18)
  86. #define HSIO_SERDES6G_ANA_CFG_COMMON_CFG_SYS_RST BIT(31)
  87. #define HSIO_SERDES6G_ANA_CFG_PLL_CFG 0x80
  88. #define HSIO_SERDES6G_ANA_CFG_PLL_CFG_FSM_ENA BIT(7)
  89. #define HSIO_SERDES6G_ANA_CFG_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8)
  90. #define HSIO_SERDES6G_ANA_CFG_SER_CFG 0x84
  91. #define HSIO_SERDES6G_DIG_CFG_MISC_CFG 0x88
  92. #define HSIO_SERDES6G_DIG_CFG_MISC_CFG_LANE_RST BIT(0)
  93. #define HSIO_MCB_SERDES6G_CFG 0xac
  94. #define HSIO_MCB_SERDES6G_CFG_WR_ONE_SHOT BIT(31)
  95. #define HSIO_MCB_SERDES6G_CFG_ADDR(x) (x)
  96. #define DEV_GMII_PORT_MODE_CLK 0x0
  97. #define DEV_GMII_PORT_MODE_CLK_PHY_RST BIT(0)
  98. #define DEV_GMII_MAC_CFG_MAC_ENA 0xc
  99. #define DEV_GMII_MAC_CFG_MAC_ENA_RX_ENA BIT(4)
  100. #define DEV_GMII_MAC_CFG_MAC_ENA_TX_ENA BIT(0)
  101. #define DEV_PORT_MODE_CLK 0x4
  102. #define DEV_PORT_MODE_CLK_PHY_RST BIT(2)
  103. #define DEV_PORT_MODE_CLK_LINK_SPEED_1000 1
  104. #define DEV_MAC_CFG_MAC_ENA 0x10
  105. #define DEV_MAC_CFG_MAC_ENA_RX_ENA BIT(4)
  106. #define DEV_MAC_CFG_MAC_ENA_TX_ENA BIT(0)
  107. #define DEV_MAC_CFG_MAC_IFG 0x24
  108. #define DEV_MAC_CFG_MAC_IFG_TX_IFG(x) ((x) << 8)
  109. #define DEV_MAC_CFG_MAC_IFG_RX_IFG2(x) ((x) << 4)
  110. #define DEV_MAC_CFG_MAC_IFG_RX_IFG1(x) (x)
  111. #define DEV_PCS1G_CFG_PCS1G_CFG 0x40
  112. #define DEV_PCS1G_CFG_PCS1G_CFG_PCS_ENA BIT(0)
  113. #define DEV_PCS1G_CFG_PCS1G_MODE 0x44
  114. #define DEV_PCS1G_CFG_PCS1G_SD 0x48
  115. #define DEV_PCS1G_CFG_PCS1G_ANEG 0x4c
  116. #define DEV_PCS1G_CFG_PCS1G_ANEG_ADV_ABILITY(x) ((x) << 16)
  117. #define IFH_INJ_BYPASS BIT(31)
  118. #define IFH_TAG_TYPE_C 0
  119. #define MAC_VID 1
  120. #define CPU_PORT 26
  121. #define INTERNAL_PORT_MSK 0xFFFFFF
  122. #define IFH_LEN 2
  123. #define ETH_ALEN 6
  124. #define PGID_BROADCAST 28
  125. #define PGID_UNICAST 29
  126. #define PGID_SRC 80
  127. static const char * const regs_names[] = {
  128. "port0", "port1", "port2", "port3", "port4", "port5", "port6", "port7",
  129. "port8", "port9", "port10", "port11", "port12", "port13", "port14",
  130. "port15", "port16", "port17", "port18", "port19", "port20", "port21",
  131. "port22", "port23",
  132. "sys", "ana", "rew", "gcb", "qs", "hsio",
  133. };
  134. #define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
  135. #define MAX_PORT 24
  136. enum luton_ctrl_regs {
  137. SYS = MAX_PORT,
  138. ANA,
  139. REW,
  140. GCB,
  141. QS,
  142. HSIO
  143. };
  144. #define MIN_INT_PORT 0
  145. #define PORT10 10
  146. #define PORT11 11
  147. #define MAX_INT_PORT 12
  148. #define MIN_EXT_PORT MAX_INT_PORT
  149. #define MAX_EXT_PORT MAX_PORT
  150. #define LUTON_MIIM_BUS_COUNT 2
  151. struct luton_phy_port_t {
  152. size_t phy_addr;
  153. struct mii_dev *bus;
  154. u8 serdes_index;
  155. u8 phy_mode;
  156. };
  157. struct luton_private {
  158. void __iomem *regs[REGS_NAMES_COUNT];
  159. struct mii_dev *bus[LUTON_MIIM_BUS_COUNT];
  160. struct luton_phy_port_t ports[MAX_PORT];
  161. };
  162. static const unsigned long luton_regs_qs[] = {
  163. [MSCC_QS_XTR_RD] = 0x18,
  164. [MSCC_QS_XTR_FLUSH] = 0x28,
  165. [MSCC_QS_XTR_DATA_PRESENT] = 0x2c,
  166. [MSCC_QS_INJ_WR] = 0x3c,
  167. [MSCC_QS_INJ_CTRL] = 0x44,
  168. };
  169. static const unsigned long luton_regs_ana_table[] = {
  170. [MSCC_ANA_TABLES_MACHDATA] = 0x11b0,
  171. [MSCC_ANA_TABLES_MACLDATA] = 0x11b4,
  172. [MSCC_ANA_TABLES_MACACCESS] = 0x11b8,
  173. };
  174. static struct mscc_miim_dev miim[LUTON_MIIM_BUS_COUNT];
  175. static int miim_count = -1;
  176. static void luton_stop(struct udevice *dev)
  177. {
  178. struct luton_private *priv = dev_get_priv(dev);
  179. /*
  180. * Switch core only reset affects VCORE-III bus and MIPS frequency
  181. * and thereby also the DDR SDRAM controller. The workaround is to
  182. * not to redirect any trafic to the CPU after the data transfer.
  183. */
  184. writel(GENMASK(9, 2), priv->regs[SYS] + SYS_SCH_CPU);
  185. }
  186. static void luton_cpu_capture_setup(struct luton_private *priv)
  187. {
  188. int i;
  189. /* map the 8 CPU extraction queues to CPU port 26 */
  190. writel(0x0, priv->regs[SYS] + SYS_SCH_CPU);
  191. for (i = 0; i <= 1; i++) {
  192. /*
  193. * One to one mapping from CPU Queue number to Group extraction
  194. * number
  195. */
  196. writel(QS_XTR_MAP_ENA | (QS_XTR_MAP_GRP * i),
  197. priv->regs[QS] + QS_XTR_MAP(i));
  198. /* Enable IFH insertion/parsing on CPU ports */
  199. setbits_le32(priv->regs[REW] + REW_PORT_CFG(CPU_PORT + i),
  200. REW_PORT_CFG_IFH_INSERT_ENA);
  201. /* Enable IFH parsing on CPU port 0 and 1 */
  202. setbits_le32(priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i),
  203. SYS_PORT_MODE_INCL_INJ_HDR);
  204. }
  205. /* Make VLAN aware for CPU traffic */
  206. writel(ANA_PORT_VLAN_CFG_AWARE_ENA |
  207. ANA_PORT_VLAN_CFG_POP_CNT(1) |
  208. MAC_VID,
  209. priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
  210. /* Disable learning (only RECV_ENA must be set) */
  211. writel(ANA_PORT_PORT_CFG_RECV_ENA,
  212. priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
  213. /* Enable switching to/from cpu port */
  214. setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(CPU_PORT),
  215. SYS_SWITCH_PORT_MODE_PORT_ENA);
  216. setbits_le32(priv->regs[SYS] + SYS_EGR_NO_SHARING, BIT(CPU_PORT));
  217. }
  218. static void luton_gmii_port_init(struct luton_private *priv, int port)
  219. {
  220. void __iomem *regs = priv->regs[port];
  221. writel(0, regs + DEV_GMII_PORT_MODE_CLK);
  222. /* Enable MAC RX and TX */
  223. writel(DEV_GMII_MAC_CFG_MAC_ENA_RX_ENA |
  224. DEV_GMII_MAC_CFG_MAC_ENA_TX_ENA,
  225. regs + DEV_GMII_MAC_CFG_MAC_ENA);
  226. /* Make VLAN aware for CPU traffic */
  227. writel(ANA_PORT_VLAN_CFG_AWARE_ENA |
  228. ANA_PORT_VLAN_CFG_POP_CNT(1) |
  229. MAC_VID,
  230. priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
  231. /* Enable switching to/from port */
  232. setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port),
  233. SYS_SWITCH_PORT_MODE_PORT_ENA);
  234. }
  235. static void luton_port_init(struct luton_private *priv, int port)
  236. {
  237. void __iomem *regs = priv->regs[port];
  238. writel(0, regs + DEV_PORT_MODE_CLK);
  239. /* Enable MAC RX and TX */
  240. writel(DEV_MAC_CFG_MAC_ENA_RX_ENA |
  241. DEV_MAC_CFG_MAC_ENA_TX_ENA,
  242. regs + DEV_MAC_CFG_MAC_ENA);
  243. /* Make VLAN aware for CPU traffic */
  244. writel(ANA_PORT_VLAN_CFG_AWARE_ENA |
  245. ANA_PORT_VLAN_CFG_POP_CNT(1) |
  246. MAC_VID,
  247. priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
  248. /* Enable switching to/from port */
  249. setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port),
  250. SYS_SWITCH_PORT_MODE_PORT_ENA);
  251. }
  252. static void luton_ext_port_init(struct luton_private *priv, int port)
  253. {
  254. void __iomem *regs = priv->regs[port];
  255. /* Enable PCS */
  256. writel(DEV_PCS1G_CFG_PCS1G_CFG_PCS_ENA,
  257. regs + DEV_PCS1G_CFG_PCS1G_CFG);
  258. /* Disable Signal Detect */
  259. writel(0, regs + DEV_PCS1G_CFG_PCS1G_SD);
  260. /* Enable MAC RX and TX */
  261. writel(DEV_MAC_CFG_MAC_ENA_RX_ENA |
  262. DEV_MAC_CFG_MAC_ENA_TX_ENA,
  263. regs + DEV_MAC_CFG_MAC_ENA);
  264. /* Clear sgmii_mode_ena */
  265. writel(0, regs + DEV_PCS1G_CFG_PCS1G_MODE);
  266. /*
  267. * Clear sw_resolve_ena(bit 0) and set adv_ability to
  268. * something meaningful just in case
  269. */
  270. writel(DEV_PCS1G_CFG_PCS1G_ANEG_ADV_ABILITY(0x20),
  271. regs + DEV_PCS1G_CFG_PCS1G_ANEG);
  272. /* Set MAC IFG Gaps */
  273. writel(DEV_MAC_CFG_MAC_IFG_TX_IFG(7) |
  274. DEV_MAC_CFG_MAC_IFG_RX_IFG1(1) |
  275. DEV_MAC_CFG_MAC_IFG_RX_IFG2(5),
  276. regs + DEV_MAC_CFG_MAC_IFG);
  277. /* Set link speed and release all resets */
  278. writel(DEV_PORT_MODE_CLK_LINK_SPEED_1000,
  279. regs + DEV_PORT_MODE_CLK);
  280. /* Make VLAN aware for CPU traffic */
  281. writel(ANA_PORT_VLAN_CFG_AWARE_ENA |
  282. ANA_PORT_VLAN_CFG_POP_CNT(1) |
  283. MAC_VID,
  284. priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
  285. /* Enable switching to/from port */
  286. setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port),
  287. SYS_SWITCH_PORT_MODE_PORT_ENA);
  288. }
  289. static void serdes6g_write(void __iomem *base, u32 addr)
  290. {
  291. u32 data;
  292. writel(HSIO_MCB_SERDES6G_CFG_WR_ONE_SHOT |
  293. HSIO_MCB_SERDES6G_CFG_ADDR(addr),
  294. base + HSIO_MCB_SERDES6G_CFG);
  295. do {
  296. data = readl(base + HSIO_MCB_SERDES6G_CFG);
  297. } while (data & HSIO_MCB_SERDES6G_CFG_WR_ONE_SHOT);
  298. }
  299. static void serdes6g_setup(void __iomem *base, uint32_t addr,
  300. phy_interface_t interface)
  301. {
  302. writel(HSIO_RCOMP_CFG_CFG0_MODE_SEL(0x3) |
  303. HSIO_RCOMP_CFG_CFG0_RUN_CAL,
  304. base + HSIO_RCOMP_CFG_CFG0);
  305. while (readl(base + HSIO_RCOMP_STATUS) &
  306. HSIO_RCOMP_STATUS_BUSY)
  307. ;
  308. writel(HSIO_SERDES6G_ANA_CFG_OB_CFG_SR(0xb) |
  309. HSIO_SERDES6G_ANA_CFG_OB_CFG_SR_H |
  310. HSIO_SERDES6G_ANA_CFG_OB_CFG_POST0(0x10) |
  311. HSIO_SERDES6G_ANA_CFG_OB_CFG_POL |
  312. HSIO_SERDES6G_ANA_CFG_OB_CFG_ENA1V_MODE,
  313. base + HSIO_SERDES6G_ANA_CFG_OB_CFG);
  314. writel(HSIO_SERDES6G_ANA_CFG_OB_CFG1_LEV(0x18) |
  315. HSIO_SERDES6G_ANA_CFG_OB_CFG1_ENA_CAS(0x1),
  316. base + HSIO_SERDES6G_ANA_CFG_OB_CFG1);
  317. writel(HSIO_SERDES6G_ANA_CFG_IB_CFG_RESISTOR_CTRL(0xc) |
  318. HSIO_SERDES6G_ANA_CFG_IB_CFG_VBCOM(0x4) |
  319. HSIO_SERDES6G_ANA_CFG_IB_CFG_VBAC(0x5) |
  320. HSIO_SERDES6G_ANA_CFG_IB_CFG_RT(0xf) |
  321. HSIO_SERDES6G_ANA_CFG_IB_CFG_RF(0x4),
  322. base + HSIO_SERDES6G_ANA_CFG_IB_CFG);
  323. writel(HSIO_SERDES6G_ANA_CFG_IB_CFG1_RST |
  324. HSIO_SERDES6G_ANA_CFG_IB_CFG1_ENA_OFFSDC |
  325. HSIO_SERDES6G_ANA_CFG_IB_CFG1_ENA_OFFSAC |
  326. HSIO_SERDES6G_ANA_CFG_IB_CFG1_ANEG_MODE |
  327. HSIO_SERDES6G_ANA_CFG_IB_CFG1_CHF |
  328. HSIO_SERDES6G_ANA_CFG_IB_CFG1_C(0x4),
  329. base + HSIO_SERDES6G_ANA_CFG_IB_CFG1);
  330. writel(HSIO_SERDES6G_ANA_CFG_DES_CFG_BW_ANA(0x5) |
  331. HSIO_SERDES6G_ANA_CFG_DES_CFG_BW_HYST(0x5) |
  332. HSIO_SERDES6G_ANA_CFG_DES_CFG_MBTR_CTRL(0x2) |
  333. HSIO_SERDES6G_ANA_CFG_DES_CFG_PHS_CTRL(0x6),
  334. base + HSIO_SERDES6G_ANA_CFG_DES_CFG);
  335. writel(HSIO_SERDES6G_ANA_CFG_PLL_CFG_FSM_ENA |
  336. HSIO_SERDES6G_ANA_CFG_PLL_CFG_FSM_CTRL_DATA(0x78),
  337. base + HSIO_SERDES6G_ANA_CFG_PLL_CFG);
  338. writel(HSIO_SERDES6G_ANA_CFG_COMMON_CFG_IF_MODE(0x30) |
  339. HSIO_SERDES6G_ANA_CFG_COMMON_CFG_ENA_LANE,
  340. base + HSIO_SERDES6G_ANA_CFG_COMMON_CFG);
  341. /*
  342. * There are 4 serdes6g, configure all except serdes6g0, therefore
  343. * the address is b1110
  344. */
  345. serdes6g_write(base, addr);
  346. writel(readl(base + HSIO_SERDES6G_ANA_CFG_COMMON_CFG) |
  347. HSIO_SERDES6G_ANA_CFG_COMMON_CFG_SYS_RST,
  348. base + HSIO_SERDES6G_ANA_CFG_COMMON_CFG);
  349. serdes6g_write(base, addr);
  350. clrbits_le32(base + HSIO_SERDES6G_ANA_CFG_IB_CFG1,
  351. HSIO_SERDES6G_ANA_CFG_IB_CFG1_RST);
  352. writel(HSIO_SERDES6G_DIG_CFG_MISC_CFG_LANE_RST,
  353. base + HSIO_SERDES6G_DIG_CFG_MISC_CFG);
  354. serdes6g_write(base, addr);
  355. }
  356. static void serdes_setup(struct luton_private *priv)
  357. {
  358. size_t mask;
  359. int i = 0;
  360. for (i = 0; i < MAX_PORT; ++i) {
  361. if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff)
  362. continue;
  363. mask = BIT(priv->ports[i].serdes_index);
  364. serdes6g_setup(priv->regs[HSIO], mask, priv->ports[i].phy_mode);
  365. }
  366. }
  367. static int luton_switch_init(struct luton_private *priv)
  368. {
  369. setbits_le32(priv->regs[HSIO] + HSIO_PLL5G_CFG_PLL5G_CFG2, BIT(1));
  370. clrbits_le32(priv->regs[HSIO] + HSIO_PLL5G_CFG_PLL5G_CFG2, BIT(1));
  371. /* Reset switch & memories */
  372. writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
  373. priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
  374. /* Wait to complete */
  375. if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
  376. SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
  377. printf("Timeout in memory reset\n");
  378. }
  379. /* Enable switch core */
  380. setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
  381. SYS_SYSTEM_RST_CORE_ENA);
  382. /* Setup the Serdes macros */
  383. serdes_setup(priv);
  384. return 0;
  385. }
  386. static int luton_initialize(struct luton_private *priv)
  387. {
  388. int ret, i;
  389. /* Initialize switch memories, enable core */
  390. ret = luton_switch_init(priv);
  391. if (ret)
  392. return ret;
  393. /*
  394. * Disable port-to-port by switching
  395. * Put front ports in "port isolation modes" - i.e. they can't send
  396. * to other ports - via the PGID sorce masks.
  397. */
  398. for (i = 0; i < MAX_PORT; i++)
  399. writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i));
  400. /* Flush queues */
  401. mscc_flush(priv->regs[QS], luton_regs_qs);
  402. /* Setup frame ageing - "2 sec" - The unit is 4ns on Luton*/
  403. writel(2000000000 / 4,
  404. priv->regs[SYS] + SYS_FRM_AGING);
  405. for (i = 0; i < MAX_PORT; i++) {
  406. if (i < PORT10)
  407. luton_gmii_port_init(priv, i);
  408. else
  409. if (i == PORT10 || i == PORT11)
  410. luton_port_init(priv, i);
  411. else
  412. luton_ext_port_init(priv, i);
  413. }
  414. luton_cpu_capture_setup(priv);
  415. return 0;
  416. }
  417. static int luton_write_hwaddr(struct udevice *dev)
  418. {
  419. struct luton_private *priv = dev_get_priv(dev);
  420. struct eth_pdata *pdata = dev_get_platdata(dev);
  421. mscc_mac_table_add(priv->regs[ANA], luton_regs_ana_table,
  422. pdata->enetaddr, PGID_UNICAST);
  423. writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
  424. return 0;
  425. }
  426. static int luton_start(struct udevice *dev)
  427. {
  428. struct luton_private *priv = dev_get_priv(dev);
  429. struct eth_pdata *pdata = dev_get_platdata(dev);
  430. const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
  431. 0xff };
  432. int ret;
  433. ret = luton_initialize(priv);
  434. if (ret)
  435. return ret;
  436. /* Set MAC address tables entries for CPU redirection */
  437. mscc_mac_table_add(priv->regs[ANA], luton_regs_ana_table,
  438. mac, PGID_BROADCAST);
  439. writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
  440. priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
  441. mscc_mac_table_add(priv->regs[ANA], luton_regs_ana_table,
  442. pdata->enetaddr, PGID_UNICAST);
  443. writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
  444. return 0;
  445. }
  446. static int luton_send(struct udevice *dev, void *packet, int length)
  447. {
  448. struct luton_private *priv = dev_get_priv(dev);
  449. u32 ifh[IFH_LEN];
  450. int port = BIT(0); /* use port 0 */
  451. u32 *buf = packet;
  452. ifh[0] = IFH_INJ_BYPASS | port;
  453. ifh[1] = (IFH_TAG_TYPE_C << 16);
  454. return mscc_send(priv->regs[QS], luton_regs_qs,
  455. ifh, IFH_LEN, buf, length);
  456. }
  457. static int luton_recv(struct udevice *dev, int flags, uchar **packetp)
  458. {
  459. struct luton_private *priv = dev_get_priv(dev);
  460. u32 *rxbuf = (u32 *)net_rx_packets[0];
  461. int byte_cnt = 0;
  462. byte_cnt = mscc_recv(priv->regs[QS], luton_regs_qs, rxbuf, IFH_LEN,
  463. true);
  464. *packetp = net_rx_packets[0];
  465. return byte_cnt;
  466. }
  467. static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
  468. {
  469. int i = 0;
  470. for (i = 0; i < LUTON_MIIM_BUS_COUNT; ++i)
  471. if (miim[i].miim_base == base && miim[i].miim_size == size)
  472. return miim[i].bus;
  473. return NULL;
  474. }
  475. static void add_port_entry(struct luton_private *priv, size_t index,
  476. size_t phy_addr, struct mii_dev *bus,
  477. u8 serdes_index, u8 phy_mode)
  478. {
  479. priv->ports[index].phy_addr = phy_addr;
  480. priv->ports[index].bus = bus;
  481. priv->ports[index].serdes_index = serdes_index;
  482. priv->ports[index].phy_mode = phy_mode;
  483. }
  484. static int luton_probe(struct udevice *dev)
  485. {
  486. struct luton_private *priv = dev_get_priv(dev);
  487. int i, ret;
  488. struct resource res;
  489. fdt32_t faddr;
  490. phys_addr_t addr_base;
  491. unsigned long addr_size;
  492. ofnode eth_node, node, mdio_node;
  493. size_t phy_addr;
  494. struct mii_dev *bus;
  495. struct ofnode_phandle_args phandle;
  496. struct phy_device *phy;
  497. if (!priv)
  498. return -EINVAL;
  499. /* Get registers and map them to the private structure */
  500. for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
  501. priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
  502. if (!priv->regs[i]) {
  503. debug
  504. ("Error can't get regs base addresses for %s\n",
  505. regs_names[i]);
  506. return -ENOMEM;
  507. }
  508. }
  509. /* Release reset in the CU-PHY */
  510. writel(0, priv->regs[GCB] + GCB_DEVCPU_RST_SOFT_CHIP_RST);
  511. /* Ports with ext phy don't need to reset clk */
  512. for (i = 0; i < MAX_INT_PORT; i++) {
  513. if (i < PORT10)
  514. clrbits_le32(priv->regs[i] + DEV_GMII_PORT_MODE_CLK,
  515. DEV_GMII_PORT_MODE_CLK_PHY_RST);
  516. else
  517. clrbits_le32(priv->regs[i] + DEV_PORT_MODE_CLK,
  518. DEV_PORT_MODE_CLK_PHY_RST);
  519. }
  520. /* Wait for internal PHY to be ready */
  521. if (wait_for_bit_le32(priv->regs[GCB] + GCB_MISC_STAT,
  522. GCB_MISC_STAT_PHY_READY, true, 500, false))
  523. return -EACCES;
  524. /* Initialize miim buses */
  525. memset(&miim, 0x0, sizeof(miim) * LUTON_MIIM_BUS_COUNT);
  526. /* iterate all the ports and find out on which bus they are */
  527. i = 0;
  528. eth_node = dev_read_first_subnode(dev);
  529. for (node = ofnode_first_subnode(eth_node);
  530. ofnode_valid(node);
  531. node = ofnode_next_subnode(node)) {
  532. if (ofnode_read_resource(node, 0, &res))
  533. return -ENOMEM;
  534. i = res.start;
  535. ret = ofnode_parse_phandle_with_args(node, "phy-handle", NULL,
  536. 0, 0, &phandle);
  537. if (ret)
  538. continue;
  539. /* Get phy address on mdio bus */
  540. if (ofnode_read_resource(phandle.node, 0, &res))
  541. return -ENOMEM;
  542. phy_addr = res.start;
  543. /* Get mdio node */
  544. mdio_node = ofnode_get_parent(phandle.node);
  545. if (ofnode_read_resource(mdio_node, 0, &res))
  546. return -ENOMEM;
  547. faddr = cpu_to_fdt32(res.start);
  548. addr_base = ofnode_translate_address(mdio_node, &faddr);
  549. addr_size = res.end - res.start;
  550. /* If the bus is new then create a new bus */
  551. if (!get_mdiobus(addr_base, addr_size))
  552. priv->bus[miim_count] =
  553. mscc_mdiobus_init(miim, &miim_count, addr_base,
  554. addr_size);
  555. /* Connect mdio bus with the port */
  556. bus = get_mdiobus(addr_base, addr_size);
  557. /* Get serdes info */
  558. ret = ofnode_parse_phandle_with_args(node, "phys", NULL,
  559. 3, 0, &phandle);
  560. if (ret)
  561. add_port_entry(priv, i, phy_addr, bus, 0xff, 0xff);
  562. else
  563. add_port_entry(priv, i, phy_addr, bus, phandle.args[1],
  564. phandle.args[2]);
  565. }
  566. for (i = 0; i < MAX_PORT; i++) {
  567. if (!priv->ports[i].bus)
  568. continue;
  569. phy = phy_connect(priv->ports[i].bus,
  570. priv->ports[i].phy_addr, dev,
  571. PHY_INTERFACE_MODE_NONE);
  572. if (phy && i >= MAX_INT_PORT)
  573. board_phy_config(phy);
  574. }
  575. /*
  576. * coma_mode is need on only one phy, because all the other phys
  577. * will be affected.
  578. */
  579. mscc_miim_write(priv->ports[0].bus, 0, 0, 31, 0x10);
  580. mscc_miim_write(priv->ports[0].bus, 0, 0, 14, 0x800);
  581. mscc_miim_write(priv->ports[0].bus, 0, 0, 31, 0);
  582. return 0;
  583. }
  584. static int luton_remove(struct udevice *dev)
  585. {
  586. struct luton_private *priv = dev_get_priv(dev);
  587. int i;
  588. for (i = 0; i < LUTON_MIIM_BUS_COUNT; i++) {
  589. mdio_unregister(priv->bus[i]);
  590. mdio_free(priv->bus[i]);
  591. }
  592. return 0;
  593. }
  594. static const struct eth_ops luton_ops = {
  595. .start = luton_start,
  596. .stop = luton_stop,
  597. .send = luton_send,
  598. .recv = luton_recv,
  599. .write_hwaddr = luton_write_hwaddr,
  600. };
  601. static const struct udevice_id mscc_luton_ids[] = {
  602. {.compatible = "mscc,vsc7527-switch", },
  603. { /* Sentinel */ }
  604. };
  605. U_BOOT_DRIVER(luton) = {
  606. .name = "luton-switch",
  607. .id = UCLASS_ETH,
  608. .of_match = mscc_luton_ids,
  609. .probe = luton_probe,
  610. .remove = luton_remove,
  611. .ops = &luton_ops,
  612. .priv_auto_alloc_size = sizeof(struct luton_private),
  613. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  614. };