ks8851_mll.h 9.5 KB

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  1. /*
  2. * drivers/net/ks8851_mll.c
  3. *
  4. * Supports:
  5. * KS8851 16bit MLL chip from Micrel Inc.
  6. *
  7. * Copyright (c) 2009 Micrel Inc.
  8. *
  9. * modified by
  10. * (c) 2011 Bticino s.p.a, Roberto Cerati <roberto.cerati@bticino.it>
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24. */
  25. #ifndef _KS8851_MLL_H_
  26. #define _KS8851_MLL_H_
  27. #include <linux/types.h>
  28. #define KS_CCR 0x08
  29. #define CCR_EEPROM (1 << 9)
  30. #define CCR_SPI (1 << 8)
  31. #define CCR_8BIT (1 << 7)
  32. #define CCR_16BIT (1 << 6)
  33. #define CCR_32BIT (1 << 5)
  34. #define CCR_SHARED (1 << 4)
  35. #define CCR_32PIN (1 << 0)
  36. /* MAC address registers */
  37. #define KS_MARL 0x10
  38. #define KS_MARM 0x12
  39. #define KS_MARH 0x14
  40. #define KS_OBCR 0x20
  41. #define OBCR_ODS_16MA (1 << 6)
  42. #define KS_EEPCR 0x22
  43. #define EEPCR_EESA (1 << 4)
  44. #define EEPCR_EESB (1 << 3)
  45. #define EEPCR_EEDO (1 << 2)
  46. #define EEPCR_EESCK (1 << 1)
  47. #define EEPCR_EECS (1 << 0)
  48. #define KS_MBIR 0x24
  49. #define MBIR_TXMBF (1 << 12)
  50. #define MBIR_TXMBFA (1 << 11)
  51. #define MBIR_RXMBF (1 << 4)
  52. #define MBIR_RXMBFA (1 << 3)
  53. #define KS_GRR 0x26
  54. #define GRR_QMU (1 << 1)
  55. #define GRR_GSR (1 << 0)
  56. #define KS_WFCR 0x2A
  57. #define WFCR_MPRXE (1 << 7)
  58. #define WFCR_WF3E (1 << 3)
  59. #define WFCR_WF2E (1 << 2)
  60. #define WFCR_WF1E (1 << 1)
  61. #define WFCR_WF0E (1 << 0)
  62. #define KS_WF0CRC0 0x30
  63. #define KS_WF0CRC1 0x32
  64. #define KS_WF0BM0 0x34
  65. #define KS_WF0BM1 0x36
  66. #define KS_WF0BM2 0x38
  67. #define KS_WF0BM3 0x3A
  68. #define KS_WF1CRC0 0x40
  69. #define KS_WF1CRC1 0x42
  70. #define KS_WF1BM0 0x44
  71. #define KS_WF1BM1 0x46
  72. #define KS_WF1BM2 0x48
  73. #define KS_WF1BM3 0x4A
  74. #define KS_WF2CRC0 0x50
  75. #define KS_WF2CRC1 0x52
  76. #define KS_WF2BM0 0x54
  77. #define KS_WF2BM1 0x56
  78. #define KS_WF2BM2 0x58
  79. #define KS_WF2BM3 0x5A
  80. #define KS_WF3CRC0 0x60
  81. #define KS_WF3CRC1 0x62
  82. #define KS_WF3BM0 0x64
  83. #define KS_WF3BM1 0x66
  84. #define KS_WF3BM2 0x68
  85. #define KS_WF3BM3 0x6A
  86. #define KS_TXCR 0x70
  87. #define TXCR_TCGICMP (1 << 8)
  88. #define TXCR_TCGUDP (1 << 7)
  89. #define TXCR_TCGTCP (1 << 6)
  90. #define TXCR_TCGIP (1 << 5)
  91. #define TXCR_FTXQ (1 << 4)
  92. #define TXCR_TXFCE (1 << 3)
  93. #define TXCR_TXPE (1 << 2)
  94. #define TXCR_TXCRC (1 << 1)
  95. #define TXCR_TXE (1 << 0)
  96. #define KS_TXSR 0x72
  97. #define TXSR_TXLC (1 << 13)
  98. #define TXSR_TXMC (1 << 12)
  99. #define TXSR_TXFID_MASK (0x3f << 0)
  100. #define TXSR_TXFID_SHIFT (0)
  101. #define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
  102. #define KS_RXCR1 0x74
  103. #define RXCR1_FRXQ (1 << 15)
  104. #define RXCR1_RXUDPFCC (1 << 14)
  105. #define RXCR1_RXTCPFCC (1 << 13)
  106. #define RXCR1_RXIPFCC (1 << 12)
  107. #define RXCR1_RXPAFMA (1 << 11)
  108. #define RXCR1_RXFCE (1 << 10)
  109. #define RXCR1_RXEFE (1 << 9)
  110. #define RXCR1_RXMAFMA (1 << 8)
  111. #define RXCR1_RXBE (1 << 7)
  112. #define RXCR1_RXME (1 << 6)
  113. #define RXCR1_RXUE (1 << 5)
  114. #define RXCR1_RXAE (1 << 4)
  115. #define RXCR1_RXINVF (1 << 1)
  116. #define RXCR1_RXE (1 << 0)
  117. #define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \
  118. RXCR1_RXMAFMA | RXCR1_RXPAFMA)
  119. #define KS_RXCR2 0x76
  120. #define RXCR2_SRDBL_MASK (0x7 << 5)
  121. #define RXCR2_SRDBL_SHIFT (5)
  122. #define RXCR2_SRDBL_4B (0x0 << 5)
  123. #define RXCR2_SRDBL_8B (0x1 << 5)
  124. #define RXCR2_SRDBL_16B (0x2 << 5)
  125. #define RXCR2_SRDBL_32B (0x3 << 5)
  126. /* #define RXCR2_SRDBL_FRAME (0x4 << 5) */
  127. #define RXCR2_IUFFP (1 << 4)
  128. #define RXCR2_RXIUFCEZ (1 << 3)
  129. #define RXCR2_UDPLFE (1 << 2)
  130. #define RXCR2_RXICMPFCC (1 << 1)
  131. #define RXCR2_RXSAF (1 << 0)
  132. #define KS_TXMIR 0x78
  133. #define KS_RXFHSR 0x7C
  134. #define RXFSHR_RXFV (1 << 15)
  135. #define RXFSHR_RXICMPFCS (1 << 13)
  136. #define RXFSHR_RXIPFCS (1 << 12)
  137. #define RXFSHR_RXTCPFCS (1 << 11)
  138. #define RXFSHR_RXUDPFCS (1 << 10)
  139. #define RXFSHR_RXBF (1 << 7)
  140. #define RXFSHR_RXMF (1 << 6)
  141. #define RXFSHR_RXUF (1 << 5)
  142. #define RXFSHR_RXMR (1 << 4)
  143. #define RXFSHR_RXFT (1 << 3)
  144. #define RXFSHR_RXFTL (1 << 2)
  145. #define RXFSHR_RXRF (1 << 1)
  146. #define RXFSHR_RXCE (1 << 0)
  147. #define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\
  148. RXFSHR_RXFTL | RXFSHR_RXMR |\
  149. RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\
  150. RXFSHR_RXTCPFCS)
  151. #define KS_RXFHBCR 0x7E
  152. #define RXFHBCR_CNT_MASK 0x0FFF
  153. #define KS_TXQCR 0x80
  154. #define TXQCR_AETFE (1 << 2)
  155. #define TXQCR_TXQMAM (1 << 1)
  156. #define TXQCR_METFE (1 << 0)
  157. #define KS_RXQCR 0x82
  158. #define RXQCR_RXDTTS (1 << 12)
  159. #define RXQCR_RXDBCTS (1 << 11)
  160. #define RXQCR_RXFCTS (1 << 10)
  161. #define RXQCR_RXIPHTOE (1 << 9)
  162. #define RXQCR_RXDTTE (1 << 7)
  163. #define RXQCR_RXDBCTE (1 << 6)
  164. #define RXQCR_RXFCTE (1 << 5)
  165. #define RXQCR_ADRFE (1 << 4)
  166. #define RXQCR_SDA (1 << 3)
  167. #define RXQCR_RRXEF (1 << 0)
  168. #define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE)
  169. #define KS_TXFDPR 0x84
  170. #define TXFDPR_TXFPAI (1 << 14)
  171. #define TXFDPR_TXFP_MASK (0x7ff << 0)
  172. #define TXFDPR_TXFP_SHIFT (0)
  173. #define KS_RXFDPR 0x86
  174. #define RXFDPR_RXFPAI (1 << 14)
  175. #define KS_RXDTTR 0x8C
  176. #define KS_RXDBCTR 0x8E
  177. #define KS_IER 0x90
  178. #define KS_ISR 0x92
  179. #define IRQ_LCI (1 << 15)
  180. #define IRQ_TXI (1 << 14)
  181. #define IRQ_RXI (1 << 13)
  182. #define IRQ_RXOI (1 << 11)
  183. #define IRQ_TXPSI (1 << 9)
  184. #define IRQ_RXPSI (1 << 8)
  185. #define IRQ_TXSAI (1 << 6)
  186. #define IRQ_RXWFDI (1 << 5)
  187. #define IRQ_RXMPDI (1 << 4)
  188. #define IRQ_LDI (1 << 3)
  189. #define IRQ_EDI (1 << 2)
  190. #define IRQ_SPIBEI (1 << 1)
  191. #define IRQ_DEDI (1 << 0)
  192. #define KS_RXFCTR 0x9C
  193. #define RXFCTR_THRESHOLD_MASK 0x00FF
  194. #define KS_RXFC 0x9D
  195. #define RXFCTR_RXFC_MASK (0xff << 8)
  196. #define RXFCTR_RXFC_SHIFT (8)
  197. #define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
  198. #define RXFCTR_RXFCT_MASK (0xff << 0)
  199. #define RXFCTR_RXFCT_SHIFT (0)
  200. #define KS_TXNTFSR 0x9E
  201. #define KS_MAHTR0 0xA0
  202. #define KS_MAHTR1 0xA2
  203. #define KS_MAHTR2 0xA4
  204. #define KS_MAHTR3 0xA6
  205. #define KS_FCLWR 0xB0
  206. #define KS_FCHWR 0xB2
  207. #define KS_FCOWR 0xB4
  208. #define KS_CIDER 0xC0
  209. #define CIDER_ID 0x8870
  210. #define CIDER_REV_MASK (0x7 << 1)
  211. #define CIDER_REV_SHIFT (1)
  212. #define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
  213. #define KS_CGCR 0xC6
  214. #define KS_IACR 0xC8
  215. #define IACR_RDEN (1 << 12)
  216. #define IACR_TSEL_MASK (0x3 << 10)
  217. #define IACR_TSEL_SHIFT (10)
  218. #define IACR_TSEL_MIB (0x3 << 10)
  219. #define IACR_ADDR_MASK (0x1f << 0)
  220. #define IACR_ADDR_SHIFT (0)
  221. #define KS_IADLR 0xD0
  222. #define KS_IAHDR 0xD2
  223. #define KS_PMECR 0xD4
  224. #define PMECR_PME_DELAY (1 << 14)
  225. #define PMECR_PME_POL (1 << 12)
  226. #define PMECR_WOL_WAKEUP (1 << 11)
  227. #define PMECR_WOL_MAGICPKT (1 << 10)
  228. #define PMECR_WOL_LINKUP (1 << 9)
  229. #define PMECR_WOL_ENERGY (1 << 8)
  230. #define PMECR_AUTO_WAKE_EN (1 << 7)
  231. #define PMECR_WAKEUP_NORMAL (1 << 6)
  232. #define PMECR_WKEVT_MASK (0xf << 2)
  233. #define PMECR_WKEVT_SHIFT (2)
  234. #define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
  235. #define PMECR_WKEVT_ENERGY (0x1 << 2)
  236. #define PMECR_WKEVT_LINK (0x2 << 2)
  237. #define PMECR_WKEVT_MAGICPKT (0x4 << 2)
  238. #define PMECR_WKEVT_FRAME (0x8 << 2)
  239. #define PMECR_PM_MASK (0x3 << 0)
  240. #define PMECR_PM_SHIFT (0)
  241. #define PMECR_PM_NORMAL (0x0 << 0)
  242. #define PMECR_PM_ENERGY (0x1 << 0)
  243. #define PMECR_PM_SOFTDOWN (0x2 << 0)
  244. #define PMECR_PM_POWERSAVE (0x3 << 0)
  245. /* Standard MII PHY data */
  246. #define KS_P1MBCR 0xE4
  247. #define P1MBCR_FORCE_FDX (1 << 8)
  248. #define KS_P1MBSR 0xE6
  249. #define P1MBSR_AN_COMPLETE (1 << 5)
  250. #define P1MBSR_AN_CAPABLE (1 << 3)
  251. #define P1MBSR_LINK_UP (1 << 2)
  252. #define KS_PHY1ILR 0xE8
  253. #define KS_PHY1IHR 0xEA
  254. #define KS_P1ANAR 0xEC
  255. #define KS_P1ANLPR 0xEE
  256. #define KS_P1SCLMD 0xF4
  257. #define P1SCLMD_LEDOFF (1 << 15)
  258. #define P1SCLMD_TXIDS (1 << 14)
  259. #define P1SCLMD_RESTARTAN (1 << 13)
  260. #define P1SCLMD_DISAUTOMDIX (1 << 10)
  261. #define P1SCLMD_FORCEMDIX (1 << 9)
  262. #define P1SCLMD_AUTONEGEN (1 << 7)
  263. #define P1SCLMD_FORCE100 (1 << 6)
  264. #define P1SCLMD_FORCEFDX (1 << 5)
  265. #define P1SCLMD_ADV_FLOW (1 << 4)
  266. #define P1SCLMD_ADV_100BT_FDX (1 << 3)
  267. #define P1SCLMD_ADV_100BT_HDX (1 << 2)
  268. #define P1SCLMD_ADV_10BT_FDX (1 << 1)
  269. #define P1SCLMD_ADV_10BT_HDX (1 << 0)
  270. #define KS_P1CR 0xF6
  271. #define P1CR_HP_MDIX (1 << 15)
  272. #define P1CR_REV_POL (1 << 13)
  273. #define P1CR_OP_100M (1 << 10)
  274. #define P1CR_OP_FDX (1 << 9)
  275. #define P1CR_OP_MDI (1 << 7)
  276. #define P1CR_AN_DONE (1 << 6)
  277. #define P1CR_LINK_GOOD (1 << 5)
  278. #define P1CR_PNTR_FLOW (1 << 4)
  279. #define P1CR_PNTR_100BT_FDX (1 << 3)
  280. #define P1CR_PNTR_100BT_HDX (1 << 2)
  281. #define P1CR_PNTR_10BT_FDX (1 << 1)
  282. #define P1CR_PNTR_10BT_HDX (1 << 0)
  283. /* TX Frame control */
  284. #define TXFR_TXIC (1 << 15)
  285. #define TXFR_TXFID_MASK (0x3f << 0)
  286. #define TXFR_TXFID_SHIFT (0)
  287. #define KS_P1SR 0xF8
  288. #define P1SR_HP_MDIX (1 << 15)
  289. #define P1SR_REV_POL (1 << 13)
  290. #define P1SR_OP_100M (1 << 10)
  291. #define P1SR_OP_FDX (1 << 9)
  292. #define P1SR_OP_MDI (1 << 7)
  293. #define P1SR_AN_DONE (1 << 6)
  294. #define P1SR_LINK_GOOD (1 << 5)
  295. #define P1SR_PNTR_FLOW (1 << 4)
  296. #define P1SR_PNTR_100BT_FDX (1 << 3)
  297. #define P1SR_PNTR_100BT_HDX (1 << 2)
  298. #define P1SR_PNTR_10BT_FDX (1 << 1)
  299. #define P1SR_PNTR_10BT_HDX (1 << 0)
  300. #define ENUM_BUS_NONE 0
  301. #define ENUM_BUS_8BIT 1
  302. #define ENUM_BUS_16BIT 2
  303. #define ENUM_BUS_32BIT 3
  304. #define MAX_MCAST_LST 32
  305. #define HW_MCAST_SIZE 8
  306. #define MAC_ADDR_LEN 6
  307. /* Chip ID values */
  308. struct chip_id {
  309. u16 id;
  310. char *name;
  311. };
  312. #endif