ks8851_mll.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Micrel KS8851_MLL 16bit Network driver
  4. * Copyright (c) 2011 Roberto Cerati <roberto.cerati@bticino.it>
  5. */
  6. #include <log.h>
  7. #include <asm/io.h>
  8. #include <common.h>
  9. #include <command.h>
  10. #include <malloc.h>
  11. #include <net.h>
  12. #include <miiphy.h>
  13. #include <linux/delay.h>
  14. #include "ks8851_mll.h"
  15. #define DRIVERNAME "ks8851_mll"
  16. #define RX_BUF_SIZE 2000
  17. /*
  18. * struct ks_net - KS8851 driver private data
  19. * @dev : legacy non-DM ethernet device structure
  20. * @iobase : register base
  21. * @bus_width : i/o bus width.
  22. * @sharedbus : Multipex(addr and data bus) mode indicator.
  23. * @extra_byte : number of extra byte prepended rx pkt.
  24. */
  25. struct ks_net {
  26. #ifndef CONFIG_DM_ETH
  27. struct eth_device dev;
  28. #endif
  29. phys_addr_t iobase;
  30. int bus_width;
  31. u16 sharedbus;
  32. u16 rxfc;
  33. u8 extra_byte;
  34. };
  35. #define BE3 0x8000 /* Byte Enable 3 */
  36. #define BE2 0x4000 /* Byte Enable 2 */
  37. #define BE1 0x2000 /* Byte Enable 1 */
  38. #define BE0 0x1000 /* Byte Enable 0 */
  39. static u8 ks_rdreg8(struct ks_net *ks, u16 offset)
  40. {
  41. u8 shift_bit = offset & 0x03;
  42. u8 shift_data = (offset & 1) << 3;
  43. writew(offset | (BE0 << shift_bit), ks->iobase + 2);
  44. return (u8)(readw(ks->iobase) >> shift_data);
  45. }
  46. static u16 ks_rdreg16(struct ks_net *ks, u16 offset)
  47. {
  48. writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2);
  49. return readw(ks->iobase);
  50. }
  51. static void ks_wrreg16(struct ks_net *ks, u16 offset, u16 val)
  52. {
  53. writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2);
  54. writew(val, ks->iobase);
  55. }
  56. /*
  57. * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode
  58. * enabled.
  59. * @ks: The chip state
  60. * @wptr: buffer address to save data
  61. * @len: length in byte to read
  62. */
  63. static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len)
  64. {
  65. len >>= 1;
  66. while (len--)
  67. *wptr++ = readw(ks->iobase);
  68. }
  69. /*
  70. * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
  71. * @ks: The chip information
  72. * @wptr: buffer address
  73. * @len: length in byte to write
  74. */
  75. static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len)
  76. {
  77. len >>= 1;
  78. while (len--)
  79. writew(*wptr++, ks->iobase);
  80. }
  81. static void ks_enable_int(struct ks_net *ks)
  82. {
  83. ks_wrreg16(ks, KS_IER, IRQ_LCI | IRQ_TXI | IRQ_RXI);
  84. }
  85. static void ks_set_powermode(struct ks_net *ks, unsigned int pwrmode)
  86. {
  87. unsigned int pmecr;
  88. ks_rdreg16(ks, KS_GRR);
  89. pmecr = ks_rdreg16(ks, KS_PMECR);
  90. pmecr &= ~PMECR_PM_MASK;
  91. pmecr |= pwrmode;
  92. ks_wrreg16(ks, KS_PMECR, pmecr);
  93. }
  94. /*
  95. * ks_read_config - read chip configuration of bus width.
  96. * @ks: The chip information
  97. */
  98. static void ks_read_config(struct ks_net *ks)
  99. {
  100. u16 reg_data = 0;
  101. /* Regardless of bus width, 8 bit read should always work. */
  102. reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF;
  103. reg_data |= ks_rdreg8(ks, KS_CCR + 1) << 8;
  104. /* addr/data bus are multiplexed */
  105. ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
  106. /*
  107. * There are garbage data when reading data from QMU,
  108. * depending on bus-width.
  109. */
  110. if (reg_data & CCR_8BIT) {
  111. ks->bus_width = ENUM_BUS_8BIT;
  112. ks->extra_byte = 1;
  113. } else if (reg_data & CCR_16BIT) {
  114. ks->bus_width = ENUM_BUS_16BIT;
  115. ks->extra_byte = 2;
  116. } else {
  117. ks->bus_width = ENUM_BUS_32BIT;
  118. ks->extra_byte = 4;
  119. }
  120. }
  121. /*
  122. * ks_soft_reset - issue one of the soft reset to the device
  123. * @ks: The device state.
  124. * @op: The bit(s) to set in the GRR
  125. *
  126. * Issue the relevant soft-reset command to the device's GRR register
  127. * specified by @op.
  128. *
  129. * Note, the delays are in there as a caution to ensure that the reset
  130. * has time to take effect and then complete. Since the datasheet does
  131. * not currently specify the exact sequence, we have chosen something
  132. * that seems to work with our device.
  133. */
  134. static void ks_soft_reset(struct ks_net *ks, unsigned int op)
  135. {
  136. /* Disable interrupt first */
  137. ks_wrreg16(ks, KS_IER, 0x0000);
  138. ks_wrreg16(ks, KS_GRR, op);
  139. mdelay(10); /* wait a short time to effect reset */
  140. ks_wrreg16(ks, KS_GRR, 0);
  141. mdelay(1); /* wait for condition to clear */
  142. }
  143. void ks_enable_qmu(struct ks_net *ks)
  144. {
  145. u16 w;
  146. w = ks_rdreg16(ks, KS_TXCR);
  147. /* Enables QMU Transmit (TXCR). */
  148. ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE);
  149. /* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */
  150. w = ks_rdreg16(ks, KS_RXQCR);
  151. ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE);
  152. /* Enables QMU Receive (RXCR1). */
  153. w = ks_rdreg16(ks, KS_RXCR1);
  154. ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE);
  155. }
  156. static void ks_disable_qmu(struct ks_net *ks)
  157. {
  158. u16 w;
  159. w = ks_rdreg16(ks, KS_TXCR);
  160. /* Disables QMU Transmit (TXCR). */
  161. w &= ~TXCR_TXE;
  162. ks_wrreg16(ks, KS_TXCR, w);
  163. /* Disables QMU Receive (RXCR1). */
  164. w = ks_rdreg16(ks, KS_RXCR1);
  165. w &= ~RXCR1_RXE;
  166. ks_wrreg16(ks, KS_RXCR1, w);
  167. }
  168. static inline void ks_read_qmu(struct ks_net *ks, u16 *buf, u32 len)
  169. {
  170. u32 r = ks->extra_byte & 0x1;
  171. u32 w = ks->extra_byte - r;
  172. /* 1. set sudo DMA mode */
  173. ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
  174. ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
  175. /*
  176. * 2. read prepend data
  177. *
  178. * read 4 + extra bytes and discard them.
  179. * extra bytes for dummy, 2 for status, 2 for len
  180. */
  181. if (r)
  182. ks_rdreg8(ks, 0);
  183. ks_inblk(ks, buf, w + 2 + 2);
  184. /* 3. read pkt data */
  185. ks_inblk(ks, buf, ALIGN(len, 4));
  186. /* 4. reset sudo DMA Mode */
  187. ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
  188. }
  189. static int ks_rcv(struct ks_net *ks, uchar *data)
  190. {
  191. u16 sts, len;
  192. if (!ks->rxfc)
  193. ks->rxfc = ks_rdreg16(ks, KS_RXFCTR) >> 8;
  194. if (!ks->rxfc)
  195. return 0;
  196. /* Checking Received packet status */
  197. sts = ks_rdreg16(ks, KS_RXFHSR);
  198. /* Get packet len from hardware */
  199. len = ks_rdreg16(ks, KS_RXFHBCR);
  200. if ((sts & RXFSHR_RXFV) && len && (len < RX_BUF_SIZE)) {
  201. /* read data block including CRC 4 bytes */
  202. ks_read_qmu(ks, (u16 *)data, len);
  203. ks->rxfc--;
  204. return len - 4;
  205. }
  206. ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_RRXEF);
  207. printf(DRIVERNAME ": bad packet\n");
  208. return 0;
  209. }
  210. /*
  211. * ks_read_selftest - read the selftest memory info.
  212. * @ks: The device state
  213. *
  214. * Read and check the TX/RX memory selftest information.
  215. */
  216. static int ks_read_selftest(struct ks_net *ks)
  217. {
  218. u16 both_done = MBIR_TXMBF | MBIR_RXMBF;
  219. u16 mbir;
  220. int ret = 0;
  221. mbir = ks_rdreg16(ks, KS_MBIR);
  222. if ((mbir & both_done) != both_done) {
  223. printf(DRIVERNAME ": Memory selftest not finished\n");
  224. return 0;
  225. }
  226. if (mbir & MBIR_TXMBFA) {
  227. printf(DRIVERNAME ": TX memory selftest fails\n");
  228. ret |= 1;
  229. }
  230. if (mbir & MBIR_RXMBFA) {
  231. printf(DRIVERNAME ": RX memory selftest fails\n");
  232. ret |= 2;
  233. }
  234. debug(DRIVERNAME ": the selftest passes\n");
  235. return ret;
  236. }
  237. static void ks_setup(struct ks_net *ks)
  238. {
  239. u16 w;
  240. /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
  241. ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
  242. /* Setup Receive Frame Data Pointer Auto-Increment */
  243. ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
  244. /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
  245. ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
  246. /* Setup RxQ Command Control (RXQCR) */
  247. ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
  248. /*
  249. * set the force mode to half duplex, default is full duplex
  250. * because if the auto-negotiation fails, most switch uses
  251. * half-duplex.
  252. */
  253. w = ks_rdreg16(ks, KS_P1MBCR);
  254. w &= ~P1MBCR_FORCE_FDX;
  255. ks_wrreg16(ks, KS_P1MBCR, w);
  256. w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
  257. ks_wrreg16(ks, KS_TXCR, w);
  258. w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
  259. /* Normal mode */
  260. w |= RXCR1_RXPAFMA;
  261. ks_wrreg16(ks, KS_RXCR1, w);
  262. }
  263. static void ks_setup_int(struct ks_net *ks)
  264. {
  265. /* Clear the interrupts status of the hardware. */
  266. ks_wrreg16(ks, KS_ISR, 0xffff);
  267. }
  268. static int ks8851_mll_detect_chip(struct ks_net *ks)
  269. {
  270. unsigned short val;
  271. ks_read_config(ks);
  272. val = ks_rdreg16(ks, KS_CIDER);
  273. if (val == 0xffff) {
  274. /* Special case -- no chip present */
  275. printf(DRIVERNAME ": is chip mounted ?\n");
  276. return -1;
  277. } else if ((val & 0xfff0) != CIDER_ID) {
  278. printf(DRIVERNAME ": Invalid chip id 0x%04x\n", val);
  279. return -1;
  280. }
  281. debug("Read back KS8851 id 0x%x\n", val);
  282. if ((val & 0xfff0) != CIDER_ID) {
  283. printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
  284. return -1;
  285. }
  286. return 0;
  287. }
  288. static void ks8851_mll_reset(struct ks_net *ks)
  289. {
  290. /* wake up powermode to normal mode */
  291. ks_set_powermode(ks, PMECR_PM_NORMAL);
  292. mdelay(1); /* wait for normal mode to take effect */
  293. /* Disable interrupt and reset */
  294. ks_soft_reset(ks, GRR_GSR);
  295. /* turn off the IRQs and ack any outstanding */
  296. ks_wrreg16(ks, KS_IER, 0x0000);
  297. ks_wrreg16(ks, KS_ISR, 0xffff);
  298. /* shutdown RX/TX QMU */
  299. ks_disable_qmu(ks);
  300. }
  301. static void ks8851_mll_phy_configure(struct ks_net *ks)
  302. {
  303. u16 data;
  304. ks_setup(ks);
  305. ks_setup_int(ks);
  306. /* Probing the phy */
  307. data = ks_rdreg16(ks, KS_OBCR);
  308. ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16MA);
  309. debug(DRIVERNAME ": phy initialized\n");
  310. }
  311. static void ks8851_mll_enable(struct ks_net *ks)
  312. {
  313. ks_wrreg16(ks, KS_ISR, 0xffff);
  314. ks_enable_int(ks);
  315. ks_enable_qmu(ks);
  316. }
  317. static int ks8851_mll_init_common(struct ks_net *ks)
  318. {
  319. if (ks_read_selftest(ks)) {
  320. printf(DRIVERNAME ": Selftest failed\n");
  321. return -1;
  322. }
  323. ks8851_mll_reset(ks);
  324. /* Configure the PHY, initialize the link state */
  325. ks8851_mll_phy_configure(ks);
  326. ks->rxfc = 0;
  327. /* Turn on Tx + Rx */
  328. ks8851_mll_enable(ks);
  329. return 0;
  330. }
  331. static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len)
  332. {
  333. __le16 txw[2];
  334. /* start header at txb[0] to align txw entries */
  335. txw[0] = 0;
  336. txw[1] = cpu_to_le16(len);
  337. /* 1. set sudo-DMA mode */
  338. ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
  339. ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
  340. /* 2. write status/length info */
  341. ks_outblk(ks, txw, 4);
  342. /* 3. write pkt data */
  343. ks_outblk(ks, (u16 *)pdata, ALIGN(len, 4));
  344. /* 4. reset sudo-DMA mode */
  345. ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
  346. /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
  347. ks_wrreg16(ks, KS_TXQCR, TXQCR_METFE);
  348. /* 6. wait until TXQCR_METFE is auto-cleared */
  349. do { } while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE);
  350. }
  351. static int ks8851_mll_send_common(struct ks_net *ks, void *packet, int length)
  352. {
  353. u8 *data = (u8 *)packet;
  354. u16 tmplen = (u16)length;
  355. u16 retv;
  356. /*
  357. * Extra space are required:
  358. * 4 byte for alignment, 4 for status/length, 4 for CRC
  359. */
  360. retv = ks_rdreg16(ks, KS_TXMIR) & 0x1fff;
  361. if (retv >= tmplen + 12) {
  362. ks_write_qmu(ks, data, tmplen);
  363. return 0;
  364. }
  365. printf(DRIVERNAME ": failed to send packet: No buffer\n");
  366. return -1;
  367. }
  368. static void ks8851_mll_halt_common(struct ks_net *ks)
  369. {
  370. ks8851_mll_reset(ks);
  371. }
  372. /*
  373. * Maximum receive ring size; that is, the number of packets
  374. * we can buffer before overflow happens. Basically, this just
  375. * needs to be enough to prevent a packet being discarded while
  376. * we are processing the previous one.
  377. */
  378. static int ks8851_mll_recv_common(struct ks_net *ks, uchar *data)
  379. {
  380. u16 status;
  381. int ret = 0;
  382. status = ks_rdreg16(ks, KS_ISR);
  383. ks_wrreg16(ks, KS_ISR, status);
  384. if (ks->rxfc || (status & IRQ_RXI))
  385. ret = ks_rcv(ks, data);
  386. if (status & IRQ_LDI) {
  387. u16 pmecr = ks_rdreg16(ks, KS_PMECR);
  388. pmecr &= ~PMECR_WKEVT_MASK;
  389. ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
  390. }
  391. return ret;
  392. }
  393. static void ks8851_mll_write_hwaddr_common(struct ks_net *ks, u8 enetaddr[6])
  394. {
  395. u16 addrl, addrm, addrh;
  396. addrh = (enetaddr[0] << 8) | enetaddr[1];
  397. addrm = (enetaddr[2] << 8) | enetaddr[3];
  398. addrl = (enetaddr[4] << 8) | enetaddr[5];
  399. ks_wrreg16(ks, KS_MARH, addrh);
  400. ks_wrreg16(ks, KS_MARM, addrm);
  401. ks_wrreg16(ks, KS_MARL, addrl);
  402. }
  403. #ifndef CONFIG_DM_ETH
  404. static int ks8851_mll_init(struct eth_device *dev, struct bd_info *bd)
  405. {
  406. struct ks_net *ks = container_of(dev, struct ks_net, dev);
  407. return ks8851_mll_init_common(ks);
  408. }
  409. static void ks8851_mll_halt(struct eth_device *dev)
  410. {
  411. struct ks_net *ks = container_of(dev, struct ks_net, dev);
  412. ks8851_mll_halt_common(ks);
  413. }
  414. static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
  415. {
  416. struct ks_net *ks = container_of(dev, struct ks_net, dev);
  417. return ks8851_mll_send_common(ks, packet, length);
  418. }
  419. static int ks8851_mll_recv(struct eth_device *dev)
  420. {
  421. struct ks_net *ks = container_of(dev, struct ks_net, dev);
  422. int ret;
  423. ret = ks8851_mll_recv_common(ks, net_rx_packets[0]);
  424. if (ret)
  425. net_process_received_packet(net_rx_packets[0], ret);
  426. return ret;
  427. }
  428. static int ks8851_mll_write_hwaddr(struct eth_device *dev)
  429. {
  430. struct ks_net *ks = container_of(dev, struct ks_net, dev);
  431. ks8851_mll_write_hwaddr_common(ks, ks->dev.enetaddr);
  432. return 0;
  433. }
  434. int ks8851_mll_initialize(u8 dev_num, int base_addr)
  435. {
  436. struct ks_net *ks;
  437. ks = calloc(1, sizeof(*ks));
  438. if (!ks)
  439. return -ENOMEM;
  440. ks->iobase = base_addr;
  441. /* Try to detect chip. Will fail if not present. */
  442. if (ks8851_mll_detect_chip(ks)) {
  443. free(ks);
  444. return -1;
  445. }
  446. ks->dev.init = ks8851_mll_init;
  447. ks->dev.halt = ks8851_mll_halt;
  448. ks->dev.send = ks8851_mll_send;
  449. ks->dev.recv = ks8851_mll_recv;
  450. ks->dev.write_hwaddr = ks8851_mll_write_hwaddr;
  451. sprintf(ks->dev.name, "%s-%hu", DRIVERNAME, dev_num);
  452. eth_register(&ks->dev);
  453. return 0;
  454. }
  455. #else /* ifdef CONFIG_DM_ETH */
  456. static int ks8851_start(struct udevice *dev)
  457. {
  458. struct ks_net *ks = dev_get_priv(dev);
  459. return ks8851_mll_init_common(ks);
  460. }
  461. static void ks8851_stop(struct udevice *dev)
  462. {
  463. struct ks_net *ks = dev_get_priv(dev);
  464. ks8851_mll_halt_common(ks);
  465. }
  466. static int ks8851_send(struct udevice *dev, void *packet, int length)
  467. {
  468. struct ks_net *ks = dev_get_priv(dev);
  469. int ret;
  470. ret = ks8851_mll_send_common(ks, packet, length);
  471. return ret ? 0 : -ETIMEDOUT;
  472. }
  473. static int ks8851_recv(struct udevice *dev, int flags, uchar **packetp)
  474. {
  475. struct ks_net *ks = dev_get_priv(dev);
  476. uchar *data = net_rx_packets[0];
  477. int ret;
  478. ret = ks8851_mll_recv_common(ks, data);
  479. if (ret)
  480. *packetp = (void *)data;
  481. return ret ? ret : -EAGAIN;
  482. }
  483. static int ks8851_write_hwaddr(struct udevice *dev)
  484. {
  485. struct ks_net *ks = dev_get_priv(dev);
  486. struct eth_pdata *pdata = dev_get_platdata(dev);
  487. ks8851_mll_write_hwaddr_common(ks, pdata->enetaddr);
  488. return 0;
  489. }
  490. static int ks8851_read_rom_hwaddr(struct udevice *dev)
  491. {
  492. struct ks_net *ks = dev_get_priv(dev);
  493. struct eth_pdata *pdata = dev_get_platdata(dev);
  494. u16 addrl, addrm, addrh;
  495. /* No EEPROM means no valid MAC address. */
  496. if (!(ks_rdreg16(ks, KS_CCR) & CCR_EEPROM))
  497. return -EINVAL;
  498. /*
  499. * If the EEPROM contains valid MAC address, it is loaded into
  500. * the NIC on power on. Read the MAC out of the NIC registers.
  501. */
  502. addrl = ks_rdreg16(ks, KS_MARL);
  503. addrm = ks_rdreg16(ks, KS_MARM);
  504. addrh = ks_rdreg16(ks, KS_MARH);
  505. pdata->enetaddr[0] = (addrh >> 8) & 0xff;
  506. pdata->enetaddr[1] = addrh & 0xff;
  507. pdata->enetaddr[2] = (addrm >> 8) & 0xff;
  508. pdata->enetaddr[3] = addrm & 0xff;
  509. pdata->enetaddr[4] = (addrl >> 8) & 0xff;
  510. pdata->enetaddr[5] = addrl & 0xff;
  511. return !is_valid_ethaddr(pdata->enetaddr);
  512. }
  513. static int ks8851_bind(struct udevice *dev)
  514. {
  515. return device_set_name(dev, dev->name);
  516. }
  517. static int ks8851_probe(struct udevice *dev)
  518. {
  519. struct ks_net *ks = dev_get_priv(dev);
  520. /* Try to detect chip. Will fail if not present. */
  521. ks8851_mll_detect_chip(ks);
  522. return 0;
  523. }
  524. static int ks8851_ofdata_to_platdata(struct udevice *dev)
  525. {
  526. struct ks_net *ks = dev_get_priv(dev);
  527. struct eth_pdata *pdata = dev_get_platdata(dev);
  528. pdata->iobase = dev_read_addr(dev);
  529. ks->iobase = pdata->iobase;
  530. return 0;
  531. }
  532. static const struct eth_ops ks8851_ops = {
  533. .start = ks8851_start,
  534. .stop = ks8851_stop,
  535. .send = ks8851_send,
  536. .recv = ks8851_recv,
  537. .write_hwaddr = ks8851_write_hwaddr,
  538. .read_rom_hwaddr = ks8851_read_rom_hwaddr,
  539. };
  540. static const struct udevice_id ks8851_ids[] = {
  541. { .compatible = "micrel,ks8851-mll" },
  542. { }
  543. };
  544. U_BOOT_DRIVER(ks8851) = {
  545. .name = "eth_ks8851",
  546. .id = UCLASS_ETH,
  547. .of_match = ks8851_ids,
  548. .bind = ks8851_bind,
  549. .ofdata_to_platdata = ks8851_ofdata_to_platdata,
  550. .probe = ks8851_probe,
  551. .ops = &ks8851_ops,
  552. .priv_auto_alloc_size = sizeof(struct ks_net),
  553. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  554. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  555. };
  556. #endif