higmacv300.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2019, Linaro Limited
  4. */
  5. #include <cpu_func.h>
  6. #include <log.h>
  7. #include <malloc.h>
  8. #include <asm/cache.h>
  9. #include <asm/io.h>
  10. #include <common.h>
  11. #include <console.h>
  12. #include <linux/bitops.h>
  13. #include <linux/bug.h>
  14. #include <linux/delay.h>
  15. #include <linux/mii.h>
  16. #include <miiphy.h>
  17. #include <net.h>
  18. #include <reset.h>
  19. #include <wait_bit.h>
  20. #define STATION_ADDR_LOW 0x0000
  21. #define STATION_ADDR_HIGH 0x0004
  22. #define MAC_DUPLEX_HALF_CTRL 0x0008
  23. #define PORT_MODE 0x0040
  24. #define PORT_EN 0x0044
  25. #define BIT_TX_EN BIT(2)
  26. #define BIT_RX_EN BIT(1)
  27. #define MODE_CHANGE_EN 0x01b4
  28. #define BIT_MODE_CHANGE_EN BIT(0)
  29. #define MDIO_SINGLE_CMD 0x03c0
  30. #define BIT_MDIO_BUSY BIT(20)
  31. #define MDIO_READ (BIT(17) | BIT_MDIO_BUSY)
  32. #define MDIO_WRITE (BIT(16) | BIT_MDIO_BUSY)
  33. #define MDIO_SINGLE_DATA 0x03c4
  34. #define MDIO_RDATA_STATUS 0x03d0
  35. #define BIT_MDIO_RDATA_INVALID BIT(0)
  36. #define RX_FQ_START_ADDR 0x0500
  37. #define RX_FQ_DEPTH 0x0504
  38. #define RX_FQ_WR_ADDR 0x0508
  39. #define RX_FQ_RD_ADDR 0x050c
  40. #define RX_FQ_REG_EN 0x0518
  41. #define RX_BQ_START_ADDR 0x0520
  42. #define RX_BQ_DEPTH 0x0524
  43. #define RX_BQ_WR_ADDR 0x0528
  44. #define RX_BQ_RD_ADDR 0x052c
  45. #define RX_BQ_REG_EN 0x0538
  46. #define TX_BQ_START_ADDR 0x0580
  47. #define TX_BQ_DEPTH 0x0584
  48. #define TX_BQ_WR_ADDR 0x0588
  49. #define TX_BQ_RD_ADDR 0x058c
  50. #define TX_BQ_REG_EN 0x0598
  51. #define TX_RQ_START_ADDR 0x05a0
  52. #define TX_RQ_DEPTH 0x05a4
  53. #define TX_RQ_WR_ADDR 0x05a8
  54. #define TX_RQ_RD_ADDR 0x05ac
  55. #define TX_RQ_REG_EN 0x05b8
  56. #define BIT_START_ADDR_EN BIT(2)
  57. #define BIT_DEPTH_EN BIT(1)
  58. #define DESC_WR_RD_ENA 0x05cc
  59. #define BIT_RX_OUTCFF_WR BIT(3)
  60. #define BIT_RX_CFF_RD BIT(2)
  61. #define BIT_TX_OUTCFF_WR BIT(1)
  62. #define BIT_TX_CFF_RD BIT(0)
  63. #define BITS_DESC_ENA (BIT_RX_OUTCFF_WR | BIT_RX_CFF_RD | \
  64. BIT_TX_OUTCFF_WR | BIT_TX_CFF_RD)
  65. /* MACIF_CTRL */
  66. #define RGMII_SPEED_1000 0x2c
  67. #define RGMII_SPEED_100 0x2f
  68. #define RGMII_SPEED_10 0x2d
  69. #define MII_SPEED_100 0x0f
  70. #define MII_SPEED_10 0x0d
  71. #define GMAC_SPEED_1000 0x05
  72. #define GMAC_SPEED_100 0x01
  73. #define GMAC_SPEED_10 0x00
  74. #define GMAC_FULL_DUPLEX BIT(4)
  75. #define RX_DESC_NUM 64
  76. #define TX_DESC_NUM 2
  77. #define DESC_SIZE 32
  78. #define DESC_WORD_SHIFT 3
  79. #define DESC_BYTE_SHIFT 5
  80. #define DESC_CNT(n) ((n) >> DESC_BYTE_SHIFT)
  81. #define DESC_BYTE(n) ((n) << DESC_BYTE_SHIFT)
  82. #define DESC_VLD_FREE 0
  83. #define DESC_VLD_BUSY 1
  84. #define MAC_MAX_FRAME_SIZE 1600
  85. enum higmac_queue {
  86. RX_FQ,
  87. RX_BQ,
  88. TX_BQ,
  89. TX_RQ,
  90. };
  91. struct higmac_desc {
  92. unsigned int buf_addr;
  93. unsigned int buf_len:11;
  94. unsigned int reserve0:5;
  95. unsigned int data_len:11;
  96. unsigned int reserve1:2;
  97. unsigned int fl:2;
  98. unsigned int descvid:1;
  99. unsigned int reserve2[6];
  100. };
  101. struct higmac_priv {
  102. void __iomem *base;
  103. void __iomem *macif_ctrl;
  104. struct reset_ctl rst_phy;
  105. struct higmac_desc *rxfq;
  106. struct higmac_desc *rxbq;
  107. struct higmac_desc *txbq;
  108. struct higmac_desc *txrq;
  109. int rxdesc_in_use;
  110. struct mii_dev *bus;
  111. struct phy_device *phydev;
  112. int phyintf;
  113. int phyaddr;
  114. };
  115. #define flush_desc(d) flush_cache((unsigned long)(d), sizeof(*(d)))
  116. #define invalidate_desc(d) \
  117. invalidate_dcache_range((unsigned long)(d), \
  118. (unsigned long)(d) + sizeof(*(d)))
  119. static int higmac_write_hwaddr(struct udevice *dev)
  120. {
  121. struct eth_pdata *pdata = dev_get_platdata(dev);
  122. struct higmac_priv *priv = dev_get_priv(dev);
  123. unsigned char *mac = pdata->enetaddr;
  124. u32 val;
  125. val = mac[1] | (mac[0] << 8);
  126. writel(val, priv->base + STATION_ADDR_HIGH);
  127. val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
  128. writel(val, priv->base + STATION_ADDR_LOW);
  129. return 0;
  130. }
  131. static int higmac_free_pkt(struct udevice *dev, uchar *packet, int length)
  132. {
  133. struct higmac_priv *priv = dev_get_priv(dev);
  134. /* Inform GMAC that the RX descriptor is no longer in use */
  135. writel(DESC_BYTE(priv->rxdesc_in_use), priv->base + RX_BQ_RD_ADDR);
  136. return 0;
  137. }
  138. static int higmac_recv(struct udevice *dev, int flags, uchar **packetp)
  139. {
  140. struct higmac_priv *priv = dev_get_priv(dev);
  141. struct higmac_desc *fqd = priv->rxfq;
  142. struct higmac_desc *bqd = priv->rxbq;
  143. int fqw_pos, fqr_pos, bqw_pos, bqr_pos;
  144. int timeout = 100000;
  145. int len = 0;
  146. int space;
  147. int i;
  148. fqw_pos = DESC_CNT(readl(priv->base + RX_FQ_WR_ADDR));
  149. fqr_pos = DESC_CNT(readl(priv->base + RX_FQ_RD_ADDR));
  150. if (fqw_pos >= fqr_pos)
  151. space = RX_DESC_NUM - (fqw_pos - fqr_pos);
  152. else
  153. space = fqr_pos - fqw_pos;
  154. /* Leave one free to distinguish full filled from empty buffer */
  155. for (i = 0; i < space - 1; i++) {
  156. fqd = priv->rxfq + fqw_pos;
  157. invalidate_dcache_range(fqd->buf_addr,
  158. fqd->buf_addr + MAC_MAX_FRAME_SIZE);
  159. if (++fqw_pos >= RX_DESC_NUM)
  160. fqw_pos = 0;
  161. writel(DESC_BYTE(fqw_pos), priv->base + RX_FQ_WR_ADDR);
  162. }
  163. bqr_pos = DESC_CNT(readl(priv->base + RX_BQ_RD_ADDR));
  164. bqd += bqr_pos;
  165. /* BQ is only ever written by GMAC */
  166. invalidate_desc(bqd);
  167. do {
  168. bqw_pos = DESC_CNT(readl(priv->base + RX_BQ_WR_ADDR));
  169. udelay(1);
  170. } while (--timeout && bqw_pos == bqr_pos);
  171. if (!timeout)
  172. return -ETIMEDOUT;
  173. if (++bqr_pos >= RX_DESC_NUM)
  174. bqr_pos = 0;
  175. len = bqd->data_len;
  176. /* CPU should not have touched this buffer since we added it to FQ */
  177. invalidate_dcache_range(bqd->buf_addr, bqd->buf_addr + len);
  178. *packetp = (void *)(unsigned long)bqd->buf_addr;
  179. /* Record the RX_BQ descriptor that is holding RX data */
  180. priv->rxdesc_in_use = bqr_pos;
  181. return len;
  182. }
  183. static int higmac_send(struct udevice *dev, void *packet, int length)
  184. {
  185. struct higmac_priv *priv = dev_get_priv(dev);
  186. struct higmac_desc *bqd = priv->txbq;
  187. int bqw_pos, rqw_pos, rqr_pos;
  188. int timeout = 1000;
  189. flush_cache((unsigned long)packet, length);
  190. bqw_pos = DESC_CNT(readl(priv->base + TX_BQ_WR_ADDR));
  191. bqd += bqw_pos;
  192. bqd->buf_addr = (unsigned long)packet;
  193. bqd->descvid = DESC_VLD_BUSY;
  194. bqd->data_len = length;
  195. flush_desc(bqd);
  196. if (++bqw_pos >= TX_DESC_NUM)
  197. bqw_pos = 0;
  198. writel(DESC_BYTE(bqw_pos), priv->base + TX_BQ_WR_ADDR);
  199. rqr_pos = DESC_CNT(readl(priv->base + TX_RQ_RD_ADDR));
  200. if (++rqr_pos >= TX_DESC_NUM)
  201. rqr_pos = 0;
  202. do {
  203. rqw_pos = DESC_CNT(readl(priv->base + TX_RQ_WR_ADDR));
  204. udelay(1);
  205. } while (--timeout && rqr_pos != rqw_pos);
  206. if (!timeout)
  207. return -ETIMEDOUT;
  208. writel(DESC_BYTE(rqr_pos), priv->base + TX_RQ_RD_ADDR);
  209. return 0;
  210. }
  211. static int higmac_adjust_link(struct higmac_priv *priv)
  212. {
  213. struct phy_device *phydev = priv->phydev;
  214. int interface = priv->phyintf;
  215. u32 val;
  216. switch (interface) {
  217. case PHY_INTERFACE_MODE_RGMII:
  218. if (phydev->speed == SPEED_1000)
  219. val = RGMII_SPEED_1000;
  220. else if (phydev->speed == SPEED_100)
  221. val = RGMII_SPEED_100;
  222. else
  223. val = RGMII_SPEED_10;
  224. break;
  225. case PHY_INTERFACE_MODE_MII:
  226. if (phydev->speed == SPEED_100)
  227. val = MII_SPEED_100;
  228. else
  229. val = MII_SPEED_10;
  230. break;
  231. default:
  232. debug("unsupported mode: %d\n", interface);
  233. return -EINVAL;
  234. }
  235. if (phydev->duplex)
  236. val |= GMAC_FULL_DUPLEX;
  237. writel(val, priv->macif_ctrl);
  238. if (phydev->speed == SPEED_1000)
  239. val = GMAC_SPEED_1000;
  240. else if (phydev->speed == SPEED_100)
  241. val = GMAC_SPEED_100;
  242. else
  243. val = GMAC_SPEED_10;
  244. writel(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
  245. writel(val, priv->base + PORT_MODE);
  246. writel(0, priv->base + MODE_CHANGE_EN);
  247. writel(phydev->duplex, priv->base + MAC_DUPLEX_HALF_CTRL);
  248. return 0;
  249. }
  250. static int higmac_start(struct udevice *dev)
  251. {
  252. struct higmac_priv *priv = dev_get_priv(dev);
  253. struct phy_device *phydev = priv->phydev;
  254. int ret;
  255. ret = phy_startup(phydev);
  256. if (ret)
  257. return ret;
  258. if (!phydev->link) {
  259. debug("%s: link down\n", phydev->dev->name);
  260. return -ENODEV;
  261. }
  262. ret = higmac_adjust_link(priv);
  263. if (ret)
  264. return ret;
  265. /* Enable port */
  266. writel(BITS_DESC_ENA, priv->base + DESC_WR_RD_ENA);
  267. writel(BIT_TX_EN | BIT_RX_EN, priv->base + PORT_EN);
  268. return 0;
  269. }
  270. static void higmac_stop(struct udevice *dev)
  271. {
  272. struct higmac_priv *priv = dev_get_priv(dev);
  273. /* Disable port */
  274. writel(0, priv->base + PORT_EN);
  275. writel(0, priv->base + DESC_WR_RD_ENA);
  276. }
  277. static const struct eth_ops higmac_ops = {
  278. .start = higmac_start,
  279. .send = higmac_send,
  280. .recv = higmac_recv,
  281. .free_pkt = higmac_free_pkt,
  282. .stop = higmac_stop,
  283. .write_hwaddr = higmac_write_hwaddr,
  284. };
  285. static int higmac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  286. {
  287. struct higmac_priv *priv = bus->priv;
  288. int ret;
  289. ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
  290. false, 1000, false);
  291. if (ret)
  292. return ret;
  293. writel(MDIO_READ | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
  294. ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
  295. false, 1000, false);
  296. if (ret)
  297. return ret;
  298. if (readl(priv->base + MDIO_RDATA_STATUS) & BIT_MDIO_RDATA_INVALID)
  299. return -EINVAL;
  300. return readl(priv->base + MDIO_SINGLE_DATA) >> 16;
  301. }
  302. static int higmac_mdio_write(struct mii_dev *bus, int addr, int devad,
  303. int reg, u16 value)
  304. {
  305. struct higmac_priv *priv = bus->priv;
  306. int ret;
  307. ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
  308. false, 1000, false);
  309. if (ret)
  310. return ret;
  311. writel(value, priv->base + MDIO_SINGLE_DATA);
  312. writel(MDIO_WRITE | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);
  313. return 0;
  314. }
  315. static int higmac_init_rx_descs(struct higmac_desc *descs, int num)
  316. {
  317. int i;
  318. for (i = 0; i < num; i++) {
  319. struct higmac_desc *desc = &descs[i];
  320. desc->buf_addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
  321. MAC_MAX_FRAME_SIZE);
  322. if (!desc->buf_addr)
  323. goto free_bufs;
  324. desc->descvid = DESC_VLD_FREE;
  325. desc->buf_len = MAC_MAX_FRAME_SIZE - 1;
  326. flush_desc(desc);
  327. }
  328. return 0;
  329. free_bufs:
  330. while (--i > 0)
  331. free((void *)(unsigned long)descs[i].buf_addr);
  332. return -ENOMEM;
  333. }
  334. static int higmac_init_hw_queue(struct higmac_priv *priv,
  335. enum higmac_queue queue)
  336. {
  337. struct higmac_desc *desc, **pdesc;
  338. u32 regaddr, regen, regdep;
  339. int depth;
  340. int len;
  341. switch (queue) {
  342. case RX_FQ:
  343. regaddr = RX_FQ_START_ADDR;
  344. regen = RX_FQ_REG_EN;
  345. regdep = RX_FQ_DEPTH;
  346. depth = RX_DESC_NUM;
  347. pdesc = &priv->rxfq;
  348. break;
  349. case RX_BQ:
  350. regaddr = RX_BQ_START_ADDR;
  351. regen = RX_BQ_REG_EN;
  352. regdep = RX_BQ_DEPTH;
  353. depth = RX_DESC_NUM;
  354. pdesc = &priv->rxbq;
  355. break;
  356. case TX_BQ:
  357. regaddr = TX_BQ_START_ADDR;
  358. regen = TX_BQ_REG_EN;
  359. regdep = TX_BQ_DEPTH;
  360. depth = TX_DESC_NUM;
  361. pdesc = &priv->txbq;
  362. break;
  363. case TX_RQ:
  364. regaddr = TX_RQ_START_ADDR;
  365. regen = TX_RQ_REG_EN;
  366. regdep = TX_RQ_DEPTH;
  367. depth = TX_DESC_NUM;
  368. pdesc = &priv->txrq;
  369. break;
  370. }
  371. /* Enable depth */
  372. writel(BIT_DEPTH_EN, priv->base + regen);
  373. writel(depth << DESC_WORD_SHIFT, priv->base + regdep);
  374. writel(0, priv->base + regen);
  375. len = depth * sizeof(*desc);
  376. desc = memalign(ARCH_DMA_MINALIGN, len);
  377. if (!desc)
  378. return -ENOMEM;
  379. memset(desc, 0, len);
  380. flush_cache((unsigned long)desc, len);
  381. *pdesc = desc;
  382. /* Set up RX_FQ descriptors */
  383. if (queue == RX_FQ)
  384. higmac_init_rx_descs(desc, depth);
  385. /* Enable start address */
  386. writel(BIT_START_ADDR_EN, priv->base + regen);
  387. writel((unsigned long)desc, priv->base + regaddr);
  388. writel(0, priv->base + regen);
  389. return 0;
  390. }
  391. static int higmac_hw_init(struct higmac_priv *priv)
  392. {
  393. int ret;
  394. /* Initialize hardware queues */
  395. ret = higmac_init_hw_queue(priv, RX_FQ);
  396. if (ret)
  397. return ret;
  398. ret = higmac_init_hw_queue(priv, RX_BQ);
  399. if (ret)
  400. goto free_rx_fq;
  401. ret = higmac_init_hw_queue(priv, TX_BQ);
  402. if (ret)
  403. goto free_rx_bq;
  404. ret = higmac_init_hw_queue(priv, TX_RQ);
  405. if (ret)
  406. goto free_tx_bq;
  407. /* Reset phy */
  408. reset_deassert(&priv->rst_phy);
  409. mdelay(10);
  410. reset_assert(&priv->rst_phy);
  411. mdelay(30);
  412. reset_deassert(&priv->rst_phy);
  413. mdelay(30);
  414. return 0;
  415. free_tx_bq:
  416. free(priv->txbq);
  417. free_rx_bq:
  418. free(priv->rxbq);
  419. free_rx_fq:
  420. free(priv->rxfq);
  421. return ret;
  422. }
  423. static int higmac_probe(struct udevice *dev)
  424. {
  425. struct higmac_priv *priv = dev_get_priv(dev);
  426. struct phy_device *phydev;
  427. struct mii_dev *bus;
  428. int ret;
  429. ret = higmac_hw_init(priv);
  430. if (ret)
  431. return ret;
  432. bus = mdio_alloc();
  433. if (!bus)
  434. return -ENOMEM;
  435. bus->read = higmac_mdio_read;
  436. bus->write = higmac_mdio_write;
  437. bus->priv = priv;
  438. priv->bus = bus;
  439. ret = mdio_register_seq(bus, dev->seq);
  440. if (ret)
  441. return ret;
  442. phydev = phy_connect(bus, priv->phyaddr, dev, priv->phyintf);
  443. if (!phydev)
  444. return -ENODEV;
  445. phydev->supported &= PHY_GBIT_FEATURES;
  446. phydev->advertising = phydev->supported;
  447. priv->phydev = phydev;
  448. return phy_config(phydev);
  449. }
  450. static int higmac_remove(struct udevice *dev)
  451. {
  452. struct higmac_priv *priv = dev_get_priv(dev);
  453. int i;
  454. mdio_unregister(priv->bus);
  455. mdio_free(priv->bus);
  456. /* Free RX packet buffers */
  457. for (i = 0; i < RX_DESC_NUM; i++)
  458. free((void *)(unsigned long)priv->rxfq[i].buf_addr);
  459. return 0;
  460. }
  461. static int higmac_ofdata_to_platdata(struct udevice *dev)
  462. {
  463. struct higmac_priv *priv = dev_get_priv(dev);
  464. int phyintf = PHY_INTERFACE_MODE_NONE;
  465. const char *phy_mode;
  466. ofnode phy_node;
  467. priv->base = dev_remap_addr_index(dev, 0);
  468. priv->macif_ctrl = dev_remap_addr_index(dev, 1);
  469. phy_mode = dev_read_string(dev, "phy-mode");
  470. if (phy_mode)
  471. phyintf = phy_get_interface_by_name(phy_mode);
  472. if (phyintf == PHY_INTERFACE_MODE_NONE)
  473. return -ENODEV;
  474. priv->phyintf = phyintf;
  475. phy_node = dev_read_subnode(dev, "phy");
  476. if (!ofnode_valid(phy_node)) {
  477. debug("failed to find phy node\n");
  478. return -ENODEV;
  479. }
  480. priv->phyaddr = ofnode_read_u32_default(phy_node, "reg", 0);
  481. return reset_get_by_name(dev, "phy", &priv->rst_phy);
  482. }
  483. static const struct udevice_id higmac_ids[] = {
  484. { .compatible = "hisilicon,hi3798cv200-gmac" },
  485. { }
  486. };
  487. U_BOOT_DRIVER(eth_higmac) = {
  488. .name = "eth_higmac",
  489. .id = UCLASS_ETH,
  490. .of_match = higmac_ids,
  491. .ofdata_to_platdata = higmac_ofdata_to_platdata,
  492. .probe = higmac_probe,
  493. .remove = higmac_remove,
  494. .ops = &higmac_ops,
  495. .priv_auto_alloc_size = sizeof(struct higmac_priv),
  496. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  497. };