ftgmac100.h 8.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Faraday FTGMAC100 Ethernet
  4. *
  5. * (C) Copyright 2010 Faraday Technology
  6. * Po-Yu Chuang <ratbert@faraday-tech.com>
  7. *
  8. * (C) Copyright 2010 Andes Technology
  9. * Macpaul Lin <macpaul@andestech.com>
  10. */
  11. #ifndef __FTGMAC100_H
  12. #define __FTGMAC100_H
  13. /* The registers offset table of ftgmac100 */
  14. #include <linux/bitops.h>
  15. struct ftgmac100 {
  16. unsigned int isr; /* 0x00 */
  17. unsigned int ier; /* 0x04 */
  18. unsigned int mac_madr; /* 0x08 */
  19. unsigned int mac_ladr; /* 0x0c */
  20. unsigned int maht0; /* 0x10 */
  21. unsigned int maht1; /* 0x14 */
  22. unsigned int txpd; /* 0x18 */
  23. unsigned int rxpd; /* 0x1c */
  24. unsigned int txr_badr; /* 0x20 */
  25. unsigned int rxr_badr; /* 0x24 */
  26. unsigned int hptxpd; /* 0x28 */
  27. unsigned int hptxpd_badr; /* 0x2c */
  28. unsigned int itc; /* 0x30 */
  29. unsigned int aptc; /* 0x34 */
  30. unsigned int dblac; /* 0x38 */
  31. unsigned int dmafifos; /* 0x3c */
  32. unsigned int revr; /* 0x40 */
  33. unsigned int fear; /* 0x44 */
  34. unsigned int tpafcr; /* 0x48 */
  35. unsigned int rbsr; /* 0x4c */
  36. unsigned int maccr; /* 0x50 */
  37. unsigned int macsr; /* 0x54 */
  38. unsigned int tm; /* 0x58 */
  39. unsigned int resv1; /* 0x5c */ /* not defined in spec */
  40. unsigned int phycr; /* 0x60 */
  41. unsigned int phydata; /* 0x64 */
  42. unsigned int fcr; /* 0x68 */
  43. unsigned int bpr; /* 0x6c */
  44. unsigned int wolcr; /* 0x70 */
  45. unsigned int wolsr; /* 0x74 */
  46. unsigned int wfcrc; /* 0x78 */
  47. unsigned int resv2; /* 0x7c */ /* not defined in spec */
  48. unsigned int wfbm1; /* 0x80 */
  49. unsigned int wfbm2; /* 0x84 */
  50. unsigned int wfbm3; /* 0x88 */
  51. unsigned int wfbm4; /* 0x8c */
  52. unsigned int nptxr_ptr; /* 0x90 */
  53. unsigned int hptxr_ptr; /* 0x94 */
  54. unsigned int rxr_ptr; /* 0x98 */
  55. unsigned int resv3; /* 0x9c */ /* not defined in spec */
  56. unsigned int tx; /* 0xa0 */
  57. unsigned int tx_mcol_scol; /* 0xa4 */
  58. unsigned int tx_ecol_fail; /* 0xa8 */
  59. unsigned int tx_lcol_und; /* 0xac */
  60. unsigned int rx; /* 0xb0 */
  61. unsigned int rx_bc; /* 0xb4 */
  62. unsigned int rx_mc; /* 0xb8 */
  63. unsigned int rx_pf_aep; /* 0xbc */
  64. unsigned int rx_runt; /* 0xc0 */
  65. unsigned int rx_crcer_ftl; /* 0xc4 */
  66. unsigned int rx_col_lost; /* 0xc8 */
  67. };
  68. /*
  69. * Interrupt status register & interrupt enable register
  70. */
  71. #define FTGMAC100_INT_RPKT_BUF BIT(0)
  72. #define FTGMAC100_INT_RPKT_FIFO BIT(1)
  73. #define FTGMAC100_INT_NO_RXBUF BIT(2)
  74. #define FTGMAC100_INT_RPKT_LOST BIT(3)
  75. #define FTGMAC100_INT_XPKT_ETH BIT(4)
  76. #define FTGMAC100_INT_XPKT_FIFO BIT(5)
  77. #define FTGMAC100_INT_NO_NPTXBUF BIT(6)
  78. #define FTGMAC100_INT_XPKT_LOST BIT(7)
  79. #define FTGMAC100_INT_AHB_ERR BIT(8)
  80. #define FTGMAC100_INT_PHYSTS_CHG BIT(9)
  81. #define FTGMAC100_INT_NO_HPTXBUF BIT(10)
  82. /*
  83. * Interrupt timer control register
  84. */
  85. #define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0)
  86. #define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4)
  87. #define FTGMAC100_ITC_RXINT_TIME_SEL BIT(7)
  88. #define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8)
  89. #define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12)
  90. #define FTGMAC100_ITC_TXINT_TIME_SEL BIT(15)
  91. /*
  92. * Automatic polling timer control register
  93. */
  94. #define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
  95. #define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4)
  96. #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
  97. #define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12)
  98. /*
  99. * DMA burst length and arbitration control register
  100. */
  101. #define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0)
  102. #define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3)
  103. #define FTGMAC100_DBLAC_RX_THR_EN BIT(6)
  104. #define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8)
  105. #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10)
  106. #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12)
  107. #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16)
  108. #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
  109. #define FTGMAC100_DBLAC_IFG_INC BIT(23)
  110. /*
  111. * DMA FIFO status register
  112. */
  113. #define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf)
  114. #define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf)
  115. #define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7)
  116. #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf)
  117. #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3)
  118. #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf)
  119. #define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY BIT(26)
  120. #define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY BIT(27)
  121. #define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28)
  122. #define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29)
  123. #define FTGMAC100_DMAFIFOS_RXDMA_REQ BIT(30)
  124. #define FTGMAC100_DMAFIFOS_TXDMA_REQ BIT(31)
  125. /*
  126. * Receive buffer size register
  127. */
  128. #define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff)
  129. /*
  130. * MAC control register
  131. */
  132. #define FTGMAC100_MACCR_TXDMA_EN BIT(0)
  133. #define FTGMAC100_MACCR_RXDMA_EN BIT(1)
  134. #define FTGMAC100_MACCR_TXMAC_EN BIT(2)
  135. #define FTGMAC100_MACCR_RXMAC_EN BIT(3)
  136. #define FTGMAC100_MACCR_RM_VLAN BIT(4)
  137. #define FTGMAC100_MACCR_HPTXR_EN BIT(5)
  138. #define FTGMAC100_MACCR_LOOP_EN BIT(6)
  139. #define FTGMAC100_MACCR_ENRX_IN_HALFTX BIT(7)
  140. #define FTGMAC100_MACCR_FULLDUP BIT(8)
  141. #define FTGMAC100_MACCR_GIGA_MODE BIT(9)
  142. #define FTGMAC100_MACCR_CRC_APD BIT(10)
  143. #define FTGMAC100_MACCR_RX_RUNT BIT(12)
  144. #define FTGMAC100_MACCR_JUMBO_LF BIT(13)
  145. #define FTGMAC100_MACCR_RX_ALL BIT(14)
  146. #define FTGMAC100_MACCR_HT_MULTI_EN BIT(15)
  147. #define FTGMAC100_MACCR_RX_MULTIPKT BIT(16)
  148. #define FTGMAC100_MACCR_RX_BROADPKT BIT(17)
  149. #define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18)
  150. #define FTGMAC100_MACCR_FAST_MODE BIT(19)
  151. #define FTGMAC100_MACCR_SW_RST BIT(31)
  152. /*
  153. * PHY control register
  154. */
  155. #define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f
  156. #define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f)
  157. #define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16)
  158. #define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21)
  159. #define FTGMAC100_PHYCR_MIIRD BIT(26)
  160. #define FTGMAC100_PHYCR_MIIWR BIT(27)
  161. /*
  162. * PHY data register
  163. */
  164. #define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff)
  165. #define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff)
  166. /*
  167. * Transmit descriptor, aligned to 16 bytes
  168. */
  169. struct ftgmac100_txdes {
  170. unsigned int txdes0;
  171. unsigned int txdes1;
  172. unsigned int txdes2; /* not used by HW */
  173. unsigned int txdes3; /* TXBUF_BADR */
  174. } __aligned(16);
  175. #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
  176. #define FTGMAC100_TXDES0_EDOTR BIT(15)
  177. #define FTGMAC100_TXDES0_CRC_ERR BIT(19)
  178. #define FTGMAC100_TXDES0_LTS BIT(28)
  179. #define FTGMAC100_TXDES0_FTS BIT(29)
  180. #define FTGMAC100_TXDES0_TXDMA_OWN BIT(31)
  181. #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
  182. #define FTGMAC100_TXDES1_INS_VLANTAG BIT(16)
  183. #define FTGMAC100_TXDES1_TCP_CHKSUM BIT(17)
  184. #define FTGMAC100_TXDES1_UDP_CHKSUM BIT(18)
  185. #define FTGMAC100_TXDES1_IP_CHKSUM BIT(19)
  186. #define FTGMAC100_TXDES1_LLC BIT(22)
  187. #define FTGMAC100_TXDES1_TX2FIC BIT(30)
  188. #define FTGMAC100_TXDES1_TXIC BIT(31)
  189. /*
  190. * Receive descriptor, aligned to 16 bytes
  191. */
  192. struct ftgmac100_rxdes {
  193. unsigned int rxdes0;
  194. unsigned int rxdes1;
  195. unsigned int rxdes2; /* not used by HW */
  196. unsigned int rxdes3; /* RXBUF_BADR */
  197. } __aligned(16);
  198. #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff)
  199. #define FTGMAC100_RXDES0_EDORR BIT(15)
  200. #define FTGMAC100_RXDES0_MULTICAST BIT(16)
  201. #define FTGMAC100_RXDES0_BROADCAST BIT(17)
  202. #define FTGMAC100_RXDES0_RX_ERR BIT(18)
  203. #define FTGMAC100_RXDES0_CRC_ERR BIT(19)
  204. #define FTGMAC100_RXDES0_FTL BIT(20)
  205. #define FTGMAC100_RXDES0_RUNT BIT(21)
  206. #define FTGMAC100_RXDES0_RX_ODD_NB BIT(22)
  207. #define FTGMAC100_RXDES0_FIFO_FULL BIT(23)
  208. #define FTGMAC100_RXDES0_PAUSE_OPCODE BIT(24)
  209. #define FTGMAC100_RXDES0_PAUSE_FRAME BIT(25)
  210. #define FTGMAC100_RXDES0_LRS BIT(28)
  211. #define FTGMAC100_RXDES0_FRS BIT(29)
  212. #define FTGMAC100_RXDES0_RXPKT_RDY BIT(31)
  213. #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
  214. #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
  215. #define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20)
  216. #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
  217. #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
  218. #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
  219. #define FTGMAC100_RXDES1_LLC BIT(22)
  220. #define FTGMAC100_RXDES1_DF BIT(23)
  221. #define FTGMAC100_RXDES1_VLANTAG_AVAIL BIT(24)
  222. #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR BIT(25)
  223. #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26)
  224. #define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27)
  225. #endif /* __FTGMAC100_H */