ftgmac100.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Faraday FTGMAC100 Ethernet
  4. *
  5. * (C) Copyright 2009 Faraday Technology
  6. * Po-Yu Chuang <ratbert@faraday-tech.com>
  7. *
  8. * (C) Copyright 2010 Andes Technology
  9. * Macpaul Lin <macpaul@andestech.com>
  10. *
  11. * Copyright (C) 2018, IBM Corporation.
  12. */
  13. #include <common.h>
  14. #include <clk.h>
  15. #include <cpu_func.h>
  16. #include <dm.h>
  17. #include <log.h>
  18. #include <malloc.h>
  19. #include <miiphy.h>
  20. #include <net.h>
  21. #include <wait_bit.h>
  22. #include <asm/cache.h>
  23. #include <dm/device_compat.h>
  24. #include <linux/bitops.h>
  25. #include <linux/io.h>
  26. #include <linux/iopoll.h>
  27. #include "ftgmac100.h"
  28. /* Min frame ethernet frame size without FCS */
  29. #define ETH_ZLEN 60
  30. /* Receive Buffer Size Register - HW default is 0x640 */
  31. #define FTGMAC100_RBSR_DEFAULT 0x640
  32. /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
  33. #define PKTBUFSTX 4 /* must be power of 2 */
  34. /* Timeout for transmit */
  35. #define FTGMAC100_TX_TIMEOUT_MS 1000
  36. /* Timeout for a mdio read/write operation */
  37. #define FTGMAC100_MDIO_TIMEOUT_USEC 10000
  38. /*
  39. * MDC clock cycle threshold
  40. *
  41. * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
  42. */
  43. #define MDC_CYCTHR 0x34
  44. /*
  45. * ftgmac100 model variants
  46. */
  47. enum ftgmac100_model {
  48. FTGMAC100_MODEL_FARADAY,
  49. FTGMAC100_MODEL_ASPEED,
  50. };
  51. /**
  52. * struct ftgmac100_data - private data for the FTGMAC100 driver
  53. *
  54. * @iobase: The base address of the hardware registers
  55. * @txdes: The array of transmit descriptors
  56. * @rxdes: The array of receive descriptors
  57. * @tx_index: Transmit descriptor index in @txdes
  58. * @rx_index: Receive descriptor index in @rxdes
  59. * @phy_addr: The PHY interface address to use
  60. * @phydev: The PHY device backing the MAC
  61. * @bus: The mdio bus
  62. * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
  63. * @max_speed: Maximum speed of Ethernet connection supported by MAC
  64. * @clks: The bulk of clocks assigned to the device in the DT
  65. * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer
  66. * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer
  67. */
  68. struct ftgmac100_data {
  69. struct ftgmac100 *iobase;
  70. struct ftgmac100_txdes txdes[PKTBUFSTX] __aligned(ARCH_DMA_MINALIGN);
  71. struct ftgmac100_rxdes rxdes[PKTBUFSRX] __aligned(ARCH_DMA_MINALIGN);
  72. int tx_index;
  73. int rx_index;
  74. u32 phy_addr;
  75. struct phy_device *phydev;
  76. struct mii_dev *bus;
  77. u32 phy_mode;
  78. u32 max_speed;
  79. struct clk_bulk clks;
  80. /* End of RX/TX ring buffer bits. Depend on model */
  81. u32 rxdes0_edorr_mask;
  82. u32 txdes0_edotr_mask;
  83. };
  84. /*
  85. * struct mii_bus functions
  86. */
  87. static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
  88. int reg_addr)
  89. {
  90. struct ftgmac100_data *priv = bus->priv;
  91. struct ftgmac100 *ftgmac100 = priv->iobase;
  92. int phycr;
  93. int data;
  94. int ret;
  95. phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
  96. FTGMAC100_PHYCR_PHYAD(phy_addr) |
  97. FTGMAC100_PHYCR_REGAD(reg_addr) |
  98. FTGMAC100_PHYCR_MIIRD;
  99. writel(phycr, &ftgmac100->phycr);
  100. ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
  101. !(phycr & FTGMAC100_PHYCR_MIIRD),
  102. FTGMAC100_MDIO_TIMEOUT_USEC);
  103. if (ret) {
  104. pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
  105. priv->phydev->dev->name, phy_addr, reg_addr);
  106. return ret;
  107. }
  108. data = readl(&ftgmac100->phydata);
  109. return FTGMAC100_PHYDATA_MIIRDATA(data);
  110. }
  111. static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
  112. int reg_addr, u16 value)
  113. {
  114. struct ftgmac100_data *priv = bus->priv;
  115. struct ftgmac100 *ftgmac100 = priv->iobase;
  116. int phycr;
  117. int data;
  118. int ret;
  119. phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
  120. FTGMAC100_PHYCR_PHYAD(phy_addr) |
  121. FTGMAC100_PHYCR_REGAD(reg_addr) |
  122. FTGMAC100_PHYCR_MIIWR;
  123. data = FTGMAC100_PHYDATA_MIIWDATA(value);
  124. writel(data, &ftgmac100->phydata);
  125. writel(phycr, &ftgmac100->phycr);
  126. ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
  127. !(phycr & FTGMAC100_PHYCR_MIIWR),
  128. FTGMAC100_MDIO_TIMEOUT_USEC);
  129. if (ret) {
  130. pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
  131. priv->phydev->dev->name, phy_addr, reg_addr);
  132. }
  133. return ret;
  134. }
  135. static int ftgmac100_mdio_init(struct udevice *dev)
  136. {
  137. struct ftgmac100_data *priv = dev_get_priv(dev);
  138. struct mii_dev *bus;
  139. int ret;
  140. bus = mdio_alloc();
  141. if (!bus)
  142. return -ENOMEM;
  143. bus->read = ftgmac100_mdio_read;
  144. bus->write = ftgmac100_mdio_write;
  145. bus->priv = priv;
  146. ret = mdio_register_seq(bus, dev->seq);
  147. if (ret) {
  148. free(bus);
  149. return ret;
  150. }
  151. priv->bus = bus;
  152. return 0;
  153. }
  154. static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
  155. {
  156. struct ftgmac100 *ftgmac100 = priv->iobase;
  157. struct phy_device *phydev = priv->phydev;
  158. u32 maccr;
  159. if (!phydev->link) {
  160. dev_err(phydev->dev, "No link\n");
  161. return -EREMOTEIO;
  162. }
  163. /* read MAC control register and clear related bits */
  164. maccr = readl(&ftgmac100->maccr) &
  165. ~(FTGMAC100_MACCR_GIGA_MODE |
  166. FTGMAC100_MACCR_FAST_MODE |
  167. FTGMAC100_MACCR_FULLDUP);
  168. if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
  169. maccr |= FTGMAC100_MACCR_GIGA_MODE;
  170. if (phydev->speed == 100)
  171. maccr |= FTGMAC100_MACCR_FAST_MODE;
  172. if (phydev->duplex)
  173. maccr |= FTGMAC100_MACCR_FULLDUP;
  174. /* update MII config into maccr */
  175. writel(maccr, &ftgmac100->maccr);
  176. return 0;
  177. }
  178. static int ftgmac100_phy_init(struct udevice *dev)
  179. {
  180. struct ftgmac100_data *priv = dev_get_priv(dev);
  181. struct phy_device *phydev;
  182. int ret;
  183. phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
  184. if (!phydev)
  185. return -ENODEV;
  186. phydev->supported &= PHY_GBIT_FEATURES;
  187. if (priv->max_speed) {
  188. ret = phy_set_supported(phydev, priv->max_speed);
  189. if (ret)
  190. return ret;
  191. }
  192. phydev->advertising = phydev->supported;
  193. priv->phydev = phydev;
  194. phy_config(phydev);
  195. return 0;
  196. }
  197. /*
  198. * Reset MAC
  199. */
  200. static void ftgmac100_reset(struct ftgmac100_data *priv)
  201. {
  202. struct ftgmac100 *ftgmac100 = priv->iobase;
  203. debug("%s()\n", __func__);
  204. setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
  205. while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
  206. ;
  207. }
  208. /*
  209. * Set MAC address
  210. */
  211. static int ftgmac100_set_mac(struct ftgmac100_data *priv,
  212. const unsigned char *mac)
  213. {
  214. struct ftgmac100 *ftgmac100 = priv->iobase;
  215. unsigned int maddr = mac[0] << 8 | mac[1];
  216. unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
  217. debug("%s(%x %x)\n", __func__, maddr, laddr);
  218. writel(maddr, &ftgmac100->mac_madr);
  219. writel(laddr, &ftgmac100->mac_ladr);
  220. return 0;
  221. }
  222. /*
  223. * disable transmitter, receiver
  224. */
  225. static void ftgmac100_stop(struct udevice *dev)
  226. {
  227. struct ftgmac100_data *priv = dev_get_priv(dev);
  228. struct ftgmac100 *ftgmac100 = priv->iobase;
  229. debug("%s()\n", __func__);
  230. writel(0, &ftgmac100->maccr);
  231. phy_shutdown(priv->phydev);
  232. }
  233. static int ftgmac100_start(struct udevice *dev)
  234. {
  235. struct eth_pdata *plat = dev_get_platdata(dev);
  236. struct ftgmac100_data *priv = dev_get_priv(dev);
  237. struct ftgmac100 *ftgmac100 = priv->iobase;
  238. struct phy_device *phydev = priv->phydev;
  239. unsigned int maccr;
  240. ulong start, end;
  241. int ret;
  242. int i;
  243. debug("%s()\n", __func__);
  244. ftgmac100_reset(priv);
  245. /* set the ethernet address */
  246. ftgmac100_set_mac(priv, plat->enetaddr);
  247. /* disable all interrupts */
  248. writel(0, &ftgmac100->ier);
  249. /* initialize descriptors */
  250. priv->tx_index = 0;
  251. priv->rx_index = 0;
  252. for (i = 0; i < PKTBUFSTX; i++) {
  253. priv->txdes[i].txdes3 = 0;
  254. priv->txdes[i].txdes0 = 0;
  255. }
  256. priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
  257. start = ((ulong)&priv->txdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
  258. end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
  259. flush_dcache_range(start, end);
  260. for (i = 0; i < PKTBUFSRX; i++) {
  261. priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
  262. priv->rxdes[i].rxdes0 = 0;
  263. }
  264. priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
  265. start = ((ulong)&priv->rxdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
  266. end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
  267. flush_dcache_range(start, end);
  268. /* transmit ring */
  269. writel((u32)priv->txdes, &ftgmac100->txr_badr);
  270. /* receive ring */
  271. writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
  272. /* poll receive descriptor automatically */
  273. writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
  274. /* config receive buffer size register */
  275. writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
  276. /* enable transmitter, receiver */
  277. maccr = FTGMAC100_MACCR_TXMAC_EN |
  278. FTGMAC100_MACCR_RXMAC_EN |
  279. FTGMAC100_MACCR_TXDMA_EN |
  280. FTGMAC100_MACCR_RXDMA_EN |
  281. FTGMAC100_MACCR_CRC_APD |
  282. FTGMAC100_MACCR_FULLDUP |
  283. FTGMAC100_MACCR_RX_RUNT |
  284. FTGMAC100_MACCR_RX_BROADPKT;
  285. writel(maccr, &ftgmac100->maccr);
  286. ret = phy_startup(phydev);
  287. if (ret) {
  288. dev_err(phydev->dev, "Could not start PHY\n");
  289. return ret;
  290. }
  291. ret = ftgmac100_phy_adjust_link(priv);
  292. if (ret) {
  293. dev_err(phydev->dev, "Could not adjust link\n");
  294. return ret;
  295. }
  296. printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
  297. phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
  298. return 0;
  299. }
  300. static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
  301. {
  302. struct ftgmac100_data *priv = dev_get_priv(dev);
  303. struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
  304. ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
  305. ulong des_end = des_start +
  306. roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
  307. /* Release buffer to DMA and flush descriptor */
  308. curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
  309. flush_dcache_range(des_start, des_end);
  310. /* Move to next descriptor */
  311. priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
  312. return 0;
  313. }
  314. /*
  315. * Get a data block via Ethernet
  316. */
  317. static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
  318. {
  319. struct ftgmac100_data *priv = dev_get_priv(dev);
  320. struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
  321. unsigned short rxlen;
  322. ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
  323. ulong des_end = des_start +
  324. roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
  325. ulong data_start = curr_des->rxdes3;
  326. ulong data_end;
  327. invalidate_dcache_range(des_start, des_end);
  328. if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
  329. return -EAGAIN;
  330. if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
  331. FTGMAC100_RXDES0_CRC_ERR |
  332. FTGMAC100_RXDES0_FTL |
  333. FTGMAC100_RXDES0_RUNT |
  334. FTGMAC100_RXDES0_RX_ODD_NB)) {
  335. return -EAGAIN;
  336. }
  337. rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
  338. debug("%s(): RX buffer %d, %x received\n",
  339. __func__, priv->rx_index, rxlen);
  340. /* Invalidate received data */
  341. data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
  342. invalidate_dcache_range(data_start, data_end);
  343. *packetp = (uchar *)data_start;
  344. return rxlen;
  345. }
  346. static u32 ftgmac100_read_txdesc(const void *desc)
  347. {
  348. const struct ftgmac100_txdes *txdes = desc;
  349. ulong des_start = ((ulong)txdes) & ~(ARCH_DMA_MINALIGN - 1);
  350. ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
  351. invalidate_dcache_range(des_start, des_end);
  352. return txdes->txdes0;
  353. }
  354. BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc)
  355. /*
  356. * Send a data block via Ethernet
  357. */
  358. static int ftgmac100_send(struct udevice *dev, void *packet, int length)
  359. {
  360. struct ftgmac100_data *priv = dev_get_priv(dev);
  361. struct ftgmac100 *ftgmac100 = priv->iobase;
  362. struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
  363. ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
  364. ulong des_end = des_start +
  365. roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
  366. ulong data_start;
  367. ulong data_end;
  368. int rc;
  369. invalidate_dcache_range(des_start, des_end);
  370. if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
  371. dev_err(dev, "no TX descriptor available\n");
  372. return -EPERM;
  373. }
  374. debug("%s(%x, %x)\n", __func__, (int)packet, length);
  375. length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
  376. curr_des->txdes3 = (unsigned int)packet;
  377. /* Flush data to be sent */
  378. data_start = curr_des->txdes3;
  379. data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
  380. flush_dcache_range(data_start, data_end);
  381. /* Only one segment on TXBUF */
  382. curr_des->txdes0 &= priv->txdes0_edotr_mask;
  383. curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
  384. FTGMAC100_TXDES0_LTS |
  385. FTGMAC100_TXDES0_TXBUF_SIZE(length) |
  386. FTGMAC100_TXDES0_TXDMA_OWN ;
  387. /* Flush modified buffer descriptor */
  388. flush_dcache_range(des_start, des_end);
  389. /* Start transmit */
  390. writel(1, &ftgmac100->txpd);
  391. rc = wait_for_bit_ftgmac100_txdone(curr_des,
  392. FTGMAC100_TXDES0_TXDMA_OWN, false,
  393. FTGMAC100_TX_TIMEOUT_MS, true);
  394. if (rc)
  395. return rc;
  396. debug("%s(): packet sent\n", __func__);
  397. /* Move to next descriptor */
  398. priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
  399. return 0;
  400. }
  401. static int ftgmac100_write_hwaddr(struct udevice *dev)
  402. {
  403. struct eth_pdata *pdata = dev_get_platdata(dev);
  404. struct ftgmac100_data *priv = dev_get_priv(dev);
  405. return ftgmac100_set_mac(priv, pdata->enetaddr);
  406. }
  407. static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
  408. {
  409. struct eth_pdata *pdata = dev_get_platdata(dev);
  410. struct ftgmac100_data *priv = dev_get_priv(dev);
  411. const char *phy_mode;
  412. pdata->iobase = dev_read_addr(dev);
  413. pdata->phy_interface = -1;
  414. phy_mode = dev_read_string(dev, "phy-mode");
  415. if (phy_mode)
  416. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  417. if (pdata->phy_interface == -1) {
  418. dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
  419. return -EINVAL;
  420. }
  421. pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
  422. if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
  423. priv->rxdes0_edorr_mask = BIT(30);
  424. priv->txdes0_edotr_mask = BIT(30);
  425. } else {
  426. priv->rxdes0_edorr_mask = BIT(15);
  427. priv->txdes0_edotr_mask = BIT(15);
  428. }
  429. return clk_get_bulk(dev, &priv->clks);
  430. }
  431. static int ftgmac100_probe(struct udevice *dev)
  432. {
  433. struct eth_pdata *pdata = dev_get_platdata(dev);
  434. struct ftgmac100_data *priv = dev_get_priv(dev);
  435. int ret;
  436. priv->iobase = (struct ftgmac100 *)pdata->iobase;
  437. priv->phy_mode = pdata->phy_interface;
  438. priv->max_speed = pdata->max_speed;
  439. priv->phy_addr = 0;
  440. #ifdef CONFIG_PHY_ADDR
  441. priv->phy_addr = CONFIG_PHY_ADDR;
  442. #endif
  443. ret = clk_enable_bulk(&priv->clks);
  444. if (ret)
  445. goto out;
  446. ret = ftgmac100_mdio_init(dev);
  447. if (ret) {
  448. dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
  449. goto out;
  450. }
  451. ret = ftgmac100_phy_init(dev);
  452. if (ret) {
  453. dev_err(dev, "Failed to initialize PHY: %d\n", ret);
  454. goto out;
  455. }
  456. out:
  457. if (ret)
  458. clk_release_bulk(&priv->clks);
  459. return ret;
  460. }
  461. static int ftgmac100_remove(struct udevice *dev)
  462. {
  463. struct ftgmac100_data *priv = dev_get_priv(dev);
  464. free(priv->phydev);
  465. mdio_unregister(priv->bus);
  466. mdio_free(priv->bus);
  467. clk_release_bulk(&priv->clks);
  468. return 0;
  469. }
  470. static const struct eth_ops ftgmac100_ops = {
  471. .start = ftgmac100_start,
  472. .send = ftgmac100_send,
  473. .recv = ftgmac100_recv,
  474. .stop = ftgmac100_stop,
  475. .free_pkt = ftgmac100_free_pkt,
  476. .write_hwaddr = ftgmac100_write_hwaddr,
  477. };
  478. static const struct udevice_id ftgmac100_ids[] = {
  479. { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
  480. { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
  481. { }
  482. };
  483. U_BOOT_DRIVER(ftgmac100) = {
  484. .name = "ftgmac100",
  485. .id = UCLASS_ETH,
  486. .of_match = ftgmac100_ids,
  487. .ofdata_to_platdata = ftgmac100_ofdata_to_platdata,
  488. .probe = ftgmac100_probe,
  489. .remove = ftgmac100_remove,
  490. .ops = &ftgmac100_ops,
  491. .priv_auto_alloc_size = sizeof(struct ftgmac100_data),
  492. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  493. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  494. };