tgec_phy.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. * Andy Fleming <afleming@gmail.com>
  5. * Some part is taken from tsec.c
  6. */
  7. #include <common.h>
  8. #include <miiphy.h>
  9. #include <phy.h>
  10. #include <asm/io.h>
  11. #include <fsl_tgec.h>
  12. #include <fm_eth.h>
  13. /*
  14. * Write value to the PHY for this device to the register at regnum, waiting
  15. * until the write is done before it returns. All PHY configuration has to be
  16. * done through the TSEC1 MIIM regs
  17. */
  18. static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
  19. int regnum, u16 value)
  20. {
  21. u32 mdio_ctl;
  22. u32 stat_val;
  23. struct tgec_mdio_controller *regs = bus->priv;
  24. if (dev_addr == MDIO_DEVAD_NONE)
  25. return 0;
  26. /* Wait till the bus is free */
  27. stat_val = MDIO_STAT_CLKDIV(100);
  28. out_be32(&regs->mdio_stat, stat_val);
  29. while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
  30. ;
  31. /* Set the port and dev addr */
  32. mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
  33. out_be32(&regs->mdio_ctl, mdio_ctl);
  34. /* Set the register address */
  35. out_be32(&regs->mdio_addr, regnum & 0xffff);
  36. /* Wait till the bus is free */
  37. while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
  38. ;
  39. /* Write the value to the register */
  40. out_be32(&regs->mdio_data, MDIO_DATA(value));
  41. /* Wait till the MDIO write is complete */
  42. while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
  43. ;
  44. return 0;
  45. }
  46. /*
  47. * Reads from register regnum in the PHY for device dev, returning the value.
  48. * Clears miimcom first. All PHY configuration has to be done through the
  49. * TSEC1 MIIM regs
  50. */
  51. static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
  52. int regnum)
  53. {
  54. u32 mdio_ctl;
  55. u32 stat_val;
  56. struct tgec_mdio_controller *regs = bus->priv;
  57. if (dev_addr == MDIO_DEVAD_NONE)
  58. return 0xffff;
  59. stat_val = MDIO_STAT_CLKDIV(100);
  60. out_be32(&regs->mdio_stat, stat_val);
  61. /* Wait till the bus is free */
  62. while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
  63. ;
  64. /* Set the Port and Device Addrs */
  65. mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
  66. out_be32(&regs->mdio_ctl, mdio_ctl);
  67. /* Set the register address */
  68. out_be32(&regs->mdio_addr, regnum & 0xffff);
  69. /* Wait till the bus is free */
  70. while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
  71. ;
  72. /* Initiate the read */
  73. mdio_ctl |= MDIO_CTL_READ;
  74. out_be32(&regs->mdio_ctl, mdio_ctl);
  75. /* Wait till the MDIO write is complete */
  76. while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
  77. ;
  78. /* Return all Fs if nothing was there */
  79. if (in_be32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
  80. return 0xffff;
  81. return in_be32(&regs->mdio_data) & 0xffff;
  82. }
  83. static int tgec_mdio_reset(struct mii_dev *bus)
  84. {
  85. return 0;
  86. }
  87. int fm_tgec_mdio_init(struct bd_info *bis, struct tgec_mdio_info *info)
  88. {
  89. struct mii_dev *bus = mdio_alloc();
  90. if (!bus) {
  91. printf("Failed to allocate FM TGEC MDIO bus\n");
  92. return -1;
  93. }
  94. bus->read = tgec_mdio_read;
  95. bus->write = tgec_mdio_write;
  96. bus->reset = tgec_mdio_reset;
  97. strcpy(bus->name, info->name);
  98. bus->priv = info->regs;
  99. return mdio_register(bus);
  100. }