t4240.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2012 Freescale Semiconductor, Inc.
  4. * Roy Zang <tie-fei.zang@freescale.com>
  5. */
  6. #include <common.h>
  7. #include <phy.h>
  8. #include <fm_eth.h>
  9. #include <asm/io.h>
  10. #include <asm/immap_85xx.h>
  11. #include <asm/fsl_serdes.h>
  12. u32 port_to_devdisr[] = {
  13. [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
  14. [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
  15. [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
  16. [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
  17. [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
  18. [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
  19. [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
  20. [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
  21. [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
  22. [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
  23. [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
  24. [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
  25. [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
  26. [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
  27. [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
  28. [FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6,
  29. [FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9,
  30. [FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10,
  31. [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1,
  32. [FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2,
  33. };
  34. static int is_device_disabled(enum fm_port port)
  35. {
  36. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  37. u32 devdisr2 = in_be32(&gur->devdisr2);
  38. return port_to_devdisr[port] & devdisr2;
  39. }
  40. void fman_disable_port(enum fm_port port)
  41. {
  42. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  43. setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  44. }
  45. void fman_enable_port(enum fm_port port)
  46. {
  47. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  48. clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  49. }
  50. phy_interface_t fman_port_enet_if(enum fm_port port)
  51. {
  52. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  53. u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
  54. if (is_device_disabled(port))
  55. return PHY_INTERFACE_MODE_NONE;
  56. if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
  57. ((is_serdes_configured(XAUI_FM1_MAC9)) ||
  58. (is_serdes_configured(XAUI_FM1_MAC10)) ||
  59. (is_serdes_configured(XFI_FM1_MAC9)) ||
  60. (is_serdes_configured(XFI_FM1_MAC10))))
  61. return PHY_INTERFACE_MODE_XGMII;
  62. if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) &&
  63. ((is_serdes_configured(XFI_FM1_MAC9)) ||
  64. (is_serdes_configured(XFI_FM1_MAC10))))
  65. return PHY_INTERFACE_MODE_NONE;
  66. if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
  67. ((is_serdes_configured(XAUI_FM2_MAC9)) ||
  68. (is_serdes_configured(XAUI_FM2_MAC10)) ||
  69. (is_serdes_configured(XFI_FM2_MAC9)) ||
  70. (is_serdes_configured(XFI_FM2_MAC10))))
  71. return PHY_INTERFACE_MODE_XGMII;
  72. #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
  73. #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
  74. #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
  75. #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
  76. #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
  77. #define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII 0x08000000
  78. #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
  79. /* handle RGMII first */
  80. if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
  81. FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII))
  82. return PHY_INTERFACE_MODE_RGMII;
  83. if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
  84. FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII))
  85. return PHY_INTERFACE_MODE_RGMII;
  86. if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
  87. FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII))
  88. return PHY_INTERFACE_MODE_RGMII;
  89. switch (port) {
  90. case FM1_DTSEC1:
  91. case FM1_DTSEC2:
  92. case FM1_DTSEC3:
  93. case FM1_DTSEC4:
  94. case FM1_DTSEC5:
  95. case FM1_DTSEC6:
  96. case FM1_DTSEC9:
  97. case FM1_DTSEC10:
  98. if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  99. return PHY_INTERFACE_MODE_SGMII;
  100. break;
  101. case FM2_DTSEC1:
  102. case FM2_DTSEC2:
  103. case FM2_DTSEC3:
  104. case FM2_DTSEC4:
  105. case FM2_DTSEC5:
  106. case FM2_DTSEC6:
  107. case FM2_DTSEC9:
  108. case FM2_DTSEC10:
  109. if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
  110. return PHY_INTERFACE_MODE_SGMII;
  111. break;
  112. default:
  113. break;
  114. }
  115. /* handle QSGMII */
  116. switch (port) {
  117. case FM1_DTSEC1:
  118. case FM1_DTSEC2:
  119. case FM1_DTSEC3:
  120. case FM1_DTSEC4:
  121. /* check lane G on SerDes1 */
  122. if (is_serdes_configured(QSGMII_FM1_A))
  123. return PHY_INTERFACE_MODE_QSGMII;
  124. break;
  125. case FM1_DTSEC5:
  126. case FM1_DTSEC6:
  127. case FM1_DTSEC9:
  128. case FM1_DTSEC10:
  129. /* check lane C on SerDes1 */
  130. if (is_serdes_configured(QSGMII_FM1_B))
  131. return PHY_INTERFACE_MODE_QSGMII;
  132. break;
  133. case FM2_DTSEC1:
  134. case FM2_DTSEC2:
  135. case FM2_DTSEC3:
  136. case FM2_DTSEC4:
  137. /* check lane G on SerDes2 */
  138. if (is_serdes_configured(QSGMII_FM2_A))
  139. return PHY_INTERFACE_MODE_QSGMII;
  140. break;
  141. case FM2_DTSEC5:
  142. case FM2_DTSEC6:
  143. case FM2_DTSEC9:
  144. case FM2_DTSEC10:
  145. /* check lane C on SerDes2 */
  146. if (is_serdes_configured(QSGMII_FM2_B))
  147. return PHY_INTERFACE_MODE_QSGMII;
  148. break;
  149. default:
  150. break;
  151. }
  152. return PHY_INTERFACE_MODE_NONE;
  153. }