t2080.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2012 Freescale Semiconductor, Inc.
  4. *
  5. * Shengzhou Liu <Shengzhou.Liu@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <phy.h>
  9. #include <fm_eth.h>
  10. #include <asm/immap_85xx.h>
  11. #include <asm/fsl_serdes.h>
  12. u32 port_to_devdisr[] = {
  13. [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
  14. [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
  15. [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
  16. [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
  17. [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
  18. [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
  19. [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
  20. [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
  21. [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
  22. [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
  23. [FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3,
  24. [FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4,
  25. };
  26. static int is_device_disabled(enum fm_port port)
  27. {
  28. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  29. u32 devdisr2 = in_be32(&gur->devdisr2);
  30. return port_to_devdisr[port] & devdisr2;
  31. }
  32. void fman_disable_port(enum fm_port port)
  33. {
  34. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  35. setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  36. }
  37. phy_interface_t fman_port_enet_if(enum fm_port port)
  38. {
  39. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  40. u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
  41. if (is_device_disabled(port))
  42. return PHY_INTERFACE_MODE_NONE;
  43. if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
  44. ((is_serdes_configured(XAUI_FM1_MAC9)) ||
  45. (is_serdes_configured(XFI_FM1_MAC9)) ||
  46. (is_serdes_configured(XFI_FM1_MAC10))))
  47. return PHY_INTERFACE_MODE_XGMII;
  48. if ((port == FM1_10GEC3 || port == FM1_10GEC4) &&
  49. ((is_serdes_configured(XFI_FM1_MAC1)) ||
  50. (is_serdes_configured(XFI_FM1_MAC2))))
  51. return PHY_INTERFACE_MODE_XGMII;
  52. if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
  53. FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII))
  54. return PHY_INTERFACE_MODE_RGMII;
  55. if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
  56. FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII))
  57. return PHY_INTERFACE_MODE_RGMII;
  58. if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
  59. FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII))
  60. return PHY_INTERFACE_MODE_RGMII;
  61. switch (port) {
  62. case FM1_DTSEC1:
  63. case FM1_DTSEC2:
  64. case FM1_DTSEC3:
  65. case FM1_DTSEC4:
  66. case FM1_DTSEC5:
  67. case FM1_DTSEC6:
  68. case FM1_DTSEC9:
  69. case FM1_DTSEC10:
  70. if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  71. return PHY_INTERFACE_MODE_SGMII;
  72. break;
  73. default:
  74. return PHY_INTERFACE_MODE_NONE;
  75. }
  76. return PHY_INTERFACE_MODE_NONE;
  77. }