t1024.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* Copyright 2014 Freescale Semiconductor, Inc.
  3. *
  4. * Shengzhou Liu <Shengzhou.Liu@freescale.com>
  5. */
  6. #include <common.h>
  7. #include <phy.h>
  8. #include <fm_eth.h>
  9. #include <asm/immap_85xx.h>
  10. #include <asm/fsl_serdes.h>
  11. u32 port_to_devdisr[] = {
  12. [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
  13. [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
  14. [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
  15. [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
  16. [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */
  17. };
  18. static int is_device_disabled(enum fm_port port)
  19. {
  20. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  21. u32 devdisr2 = in_be32(&gur->devdisr2);
  22. return port_to_devdisr[port] & devdisr2;
  23. }
  24. void fman_disable_port(enum fm_port port)
  25. {
  26. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  27. setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  28. }
  29. phy_interface_t fman_port_enet_if(enum fm_port port)
  30. {
  31. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  32. u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
  33. if (is_device_disabled(port))
  34. return PHY_INTERFACE_MODE_NONE;
  35. if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1)))
  36. return PHY_INTERFACE_MODE_XGMII;
  37. if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
  38. FSL_CORENET_RCWSR13_EC2_RGMII) &&
  39. (!is_serdes_configured(QSGMII_FM1_A)))
  40. return PHY_INTERFACE_MODE_RGMII;
  41. if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
  42. FSL_CORENET_RCWSR13_EC1_RGMII) &&
  43. (!is_serdes_configured(QSGMII_FM1_A)))
  44. return PHY_INTERFACE_MODE_RGMII;
  45. /* handle SGMII */
  46. switch (port) {
  47. case FM1_DTSEC1:
  48. case FM1_DTSEC2:
  49. case FM1_DTSEC3:
  50. if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  51. return PHY_INTERFACE_MODE_SGMII;
  52. else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1
  53. + port - FM1_DTSEC1))
  54. return PHY_INTERFACE_MODE_SGMII_2500;
  55. break;
  56. default:
  57. break;
  58. }
  59. /* handle QSGMII */
  60. switch (port) {
  61. case FM1_DTSEC1:
  62. case FM1_DTSEC2:
  63. case FM1_DTSEC3:
  64. case FM1_DTSEC4:
  65. /* check lane A on SerDes1 */
  66. if (is_serdes_configured(QSGMII_FM1_A))
  67. return PHY_INTERFACE_MODE_QSGMII;
  68. break;
  69. default:
  70. break;
  71. }
  72. return PHY_INTERFACE_MODE_NONE;
  73. }