p5040.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <phy.h>
  7. #include <fm_eth.h>
  8. #include <asm/io.h>
  9. #include <asm/immap_85xx.h>
  10. #include <asm/fsl_serdes.h>
  11. u32 port_to_devdisr[] = {
  12. [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
  13. [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
  14. [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
  15. [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
  16. [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
  17. [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
  18. [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
  19. [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
  20. [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
  21. [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
  22. [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
  23. [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
  24. };
  25. static int is_device_disabled(enum fm_port port)
  26. {
  27. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  28. u32 devdisr2 = in_be32(&gur->devdisr2);
  29. return port_to_devdisr[port] & devdisr2;
  30. }
  31. void fman_disable_port(enum fm_port port)
  32. {
  33. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  34. /* don't allow disabling of DTSEC1 as its needed for MDIO */
  35. if (port == FM1_DTSEC1)
  36. return;
  37. setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  38. }
  39. void fman_enable_port(enum fm_port port)
  40. {
  41. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  42. clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  43. }
  44. phy_interface_t fman_port_enet_if(enum fm_port port)
  45. {
  46. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  47. u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
  48. if (is_device_disabled(port))
  49. return PHY_INTERFACE_MODE_NONE;
  50. if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
  51. return PHY_INTERFACE_MODE_XGMII;
  52. if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
  53. return PHY_INTERFACE_MODE_XGMII;
  54. /* handle RGMII first */
  55. if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
  56. FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII))
  57. return PHY_INTERFACE_MODE_RGMII;
  58. if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
  59. FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII))
  60. return PHY_INTERFACE_MODE_MII;
  61. if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
  62. FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII))
  63. return PHY_INTERFACE_MODE_RGMII;
  64. if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
  65. FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII))
  66. return PHY_INTERFACE_MODE_MII;
  67. switch (port) {
  68. case FM1_DTSEC1:
  69. case FM1_DTSEC2:
  70. case FM1_DTSEC3:
  71. case FM1_DTSEC4:
  72. case FM1_DTSEC5:
  73. if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  74. return PHY_INTERFACE_MODE_SGMII;
  75. break;
  76. case FM2_DTSEC1:
  77. case FM2_DTSEC2:
  78. case FM2_DTSEC3:
  79. case FM2_DTSEC4:
  80. case FM2_DTSEC5:
  81. if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
  82. return PHY_INTERFACE_MODE_SGMII;
  83. break;
  84. default:
  85. return PHY_INTERFACE_MODE_NONE;
  86. }
  87. return PHY_INTERFACE_MODE_NONE;
  88. }