p4080.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <phy.h>
  7. #include <fm_eth.h>
  8. #include <asm/io.h>
  9. #include <asm/immap_85xx.h>
  10. #include <asm/fsl_serdes.h>
  11. static u32 port_to_devdisr[] = {
  12. [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
  13. [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
  14. [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
  15. [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
  16. [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
  17. [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
  18. [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
  19. [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
  20. [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
  21. [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
  22. };
  23. static int is_device_disabled(enum fm_port port)
  24. {
  25. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  26. u32 devdisr2 = in_be32(&gur->devdisr2);
  27. return port_to_devdisr[port] & devdisr2;
  28. }
  29. void fman_disable_port(enum fm_port port)
  30. {
  31. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  32. /* don't allow disabling of DTSEC1 as its needed for MDIO */
  33. if (port == FM1_DTSEC1)
  34. return;
  35. setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  36. }
  37. void fman_enable_port(enum fm_port port)
  38. {
  39. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  40. clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  41. }
  42. phy_interface_t fman_port_enet_if(enum fm_port port)
  43. {
  44. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  45. u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
  46. if (is_device_disabled(port))
  47. return PHY_INTERFACE_MODE_NONE;
  48. if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
  49. return PHY_INTERFACE_MODE_XGMII;
  50. if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
  51. return PHY_INTERFACE_MODE_XGMII;
  52. /* handle RGMII first */
  53. if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
  54. FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1))
  55. return PHY_INTERFACE_MODE_RGMII;
  56. if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
  57. FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2))
  58. return PHY_INTERFACE_MODE_RGMII;
  59. if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
  60. FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
  61. return PHY_INTERFACE_MODE_RGMII;
  62. switch (port) {
  63. case FM1_DTSEC1:
  64. case FM1_DTSEC2:
  65. case FM1_DTSEC3:
  66. case FM1_DTSEC4:
  67. if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  68. return PHY_INTERFACE_MODE_SGMII;
  69. break;
  70. case FM2_DTSEC1:
  71. case FM2_DTSEC2:
  72. case FM2_DTSEC3:
  73. case FM2_DTSEC4:
  74. if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
  75. return PHY_INTERFACE_MODE_SGMII;
  76. break;
  77. default:
  78. return PHY_INTERFACE_MODE_NONE;
  79. }
  80. return PHY_INTERFACE_MODE_NONE;
  81. }