ls1043.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <phy.h>
  7. #include <fm_eth.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/fsl_serdes.h>
  10. #define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
  11. #define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
  12. #define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
  13. #define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
  14. #define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
  15. #define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
  16. #define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
  17. #define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
  18. #define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
  19. u32 port_to_devdisr[] = {
  20. [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
  21. [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
  22. [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
  23. [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
  24. [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
  25. [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
  26. [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
  27. [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
  28. [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
  29. [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
  30. [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
  31. [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
  32. };
  33. static int is_device_disabled(enum fm_port port)
  34. {
  35. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  36. u32 devdisr2 = in_be32(&gur->devdisr2);
  37. return port_to_devdisr[port] & devdisr2;
  38. }
  39. void fman_disable_port(enum fm_port port)
  40. {
  41. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  42. setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  43. }
  44. phy_interface_t fman_port_enet_if(enum fm_port port)
  45. {
  46. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  47. u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
  48. if (is_device_disabled(port))
  49. return PHY_INTERFACE_MODE_NONE;
  50. if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
  51. return PHY_INTERFACE_MODE_XGMII;
  52. if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
  53. return PHY_INTERFACE_MODE_NONE;
  54. if (port == FM1_DTSEC3)
  55. if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
  56. FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
  57. return PHY_INTERFACE_MODE_RGMII_ID;
  58. }
  59. if (port == FM1_DTSEC4)
  60. if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
  61. FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
  62. return PHY_INTERFACE_MODE_RGMII_ID;
  63. }
  64. /* handle SGMII */
  65. switch (port) {
  66. case FM1_DTSEC1:
  67. case FM1_DTSEC2:
  68. if ((port == FM1_DTSEC2) &&
  69. is_serdes_configured(SGMII_2500_FM1_DTSEC2))
  70. return PHY_INTERFACE_MODE_SGMII_2500;
  71. case FM1_DTSEC5:
  72. case FM1_DTSEC6:
  73. case FM1_DTSEC9:
  74. if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  75. return PHY_INTERFACE_MODE_SGMII;
  76. else if ((port == FM1_DTSEC9) &&
  77. is_serdes_configured(SGMII_2500_FM1_DTSEC9))
  78. return PHY_INTERFACE_MODE_SGMII_2500;
  79. break;
  80. default:
  81. break;
  82. }
  83. /* handle QSGMII */
  84. switch (port) {
  85. case FM1_DTSEC1:
  86. case FM1_DTSEC2:
  87. case FM1_DTSEC5:
  88. case FM1_DTSEC6:
  89. /* only MAC 1,2,5,6 available for QSGMII */
  90. if (is_serdes_configured(QSGMII_FM1_A))
  91. return PHY_INTERFACE_MODE_QSGMII;
  92. break;
  93. default:
  94. break;
  95. }
  96. return PHY_INTERFACE_MODE_NONE;
  97. }